Atmel AT91FR40162S User manual

Features

•Incorporates the ARM7TDMI®ARM®Thumb®Processor Core

– High-performance 32-bit RISC Architecture

– High-density 16-bit Instruction Set

– Leader in MIPS/Watt

– EmbeddedICE™(In-circuit Emulation)

•256K Bytes of On-chip SRAM

– 32-bit Data Bus, Single-clock Cycle Access

•1024K Words 16-bit Flash Memory (2M bytes)

– Single Voltage Read/Write,

– Sector Erase Architecture

– Erase Suspend Capability

– Low-power Operation

– Data Polling, Toggle Bit and Ready/Busy End of Program Cycle Detection

– Reset Input for Device Initialization

– Sector Program Unlock Command

– 128-bit Protection Register

– Factory-programmed AT91 Flash Memory Uploader Software

•Fully Programmable External Bus Interface (EBI)

– Up to 8 Chip Selects, Maximum External Address Space of 64M Bytes

– Software Programmable 8/16-bit External Data Bus

•8-level Priority, Individually Maskable, Vectored Interrupt Controller

– 4 External Interrupts, Including a High-priority Low-latency Interrupt Request

•32 Programmable I/O Lines

•3-channel 16-bit Timer/Counter

– 3 External Clock Inputs, 2 Multi-purpose I/O Pins per Channel

•2 USARTs

– Two Dedicated Peripheral Data Controller (PDC) Channels per USART

•Programmable Watchdog Timer

•Advanced Power-saving Features

– CPU and Peripherals Can be De-activated Individually

•Fully Static Operation:

– 0 Hz to 75 MHz Internal Frequency Range at VDDCORE = 1.8V, 85°C

•2.7V to 3.6V I/O Operating Range, 1.65V to 1.95V Core Operating Range

•-40°C to 85°C Temperature Range

•Available in a 121-ball 10 x 10 x 1.2 mm BGA Package with 0.8 mm Ball Pitch

1. Description

The AT91FR40162S is a member of the Atmel AT91 16/32-bit Microcontroller family,

which is based on the ARM7TDMI processor core. The processor has a high-perfor-

mance 32-bit RISC architecture with a high-density 16-bit instruction set and very low

power consumption.

The AT91FR40162S ARM microcontroller features 2 Mbits of on-chip SRAM and 2

Mbytes of Flash memory in a single compact 121-ball BGA package. Its high level of

integration and very small footprint make the device ideal for space-constrained appli-

cations. The high-speed on-chip SRAM enables a performance of up to 74 MIPs in

typical conditions with significant power reduction and EMC improvement over an

external SRAM implementation.

The Flash memory may be programmed via the JTAG/ICE interface or the factory-

programmed Flash Memory Uploader (FMU) using a single device supply, making the

AT91FR40162S suitable for in-system programmable applications.

AT91

ARM®Thumb®

Microcontrollers

AT91FR40162S

Preliminary

6174B–ATARM–07-Nov-05

AT91FR40162S Preliminary

2. Pin Configuration

Figure 2-1. AT91FR40162S Pinout for 121-ball BGA Package (Top View)

1110987654321

P19 P16 GND P11

IRQ2 VDDCORE P8

TIOB2

TCLK2

P21/TXD1

NTRI

TIOB0

P20

SCK1 P18 P17 P12

FIQ

P10

IRQ1 VDDIO P7

TIOA2

TIOA1 GND P1

TIOA0

GND NUB

NWR1

P14

TXD0

NBUSY P9

IRQ0

TIOB1

TCLK1 A16

P15

RXD0

TCLK0

MCKI NRST P13

SCK0 D12 D14 VDDIO

P25

MCK0 NWDOVF A3 NC NC D3

TMS GND TCK D8 NC NC

NWE

NWR0 A2 TDI D6 GND NC

VDDCORE VDDIO NC P31/A23

CS4 NC NC

GND P27

NCS3 A5 A19 VDDIO P30/A22

CS5

NLB

A0 GND A7 A17 P29/A21

CS6 VDDCORE

A1 A4 A6 VDDIO A18 A20

VPP NRSTF A14 A15

A8 D11 D10 D13

NOE

NRD A11 D7

NCS0 D2 D5 D4

NCSF NC D0 D1

NC VDDIO GND GND

VDDIO A10 A13 GND

VDDIO A9 A12 GND

P22

RXD1

VDDIO

P23

P24

BMS

GND

TDO

P26

NCS2

NWAIT

NCS1

GND

D15

A1 Corner

6174B–ATARM–07-Nov-05

AT91FR40162S Preliminary

3. Signal Description

Table 3-1. AT91FR40162S Signal Description

Module Name Function Type

Active

Level Comments

EBI

A0 - A23 Address Bus Output – Valid after reset; do not reprogram A20 to

I/O, as it is MSB of Flash address

D0 - D15 Data Bus I/O –

NCS0 - NCS3 External Chip Select Output Low Used to select external devices

CS4 - CS7 External Chip Select Output High A23 - A20 after reset

NWR0 Lower Byte 0 Write Signal Output Low Used in Byte Write option

NWR1 Upper Byte 1 Write Signal Output Low Used in Byte Write option

NRD Read Signal Output Low Used in Byte Write option

NWE Write Enable Output Low Used in Byte Select option

NOE Output Enable Output Low Used in Byte Select option

NUB Upper Byte Select Output Low Used in Byte Select option

NLB Lower Byte Select Output Low Used in Byte Select option

NWAIT Wait Input Input Low

BMS Boot Mode Select Input –

Sampled during reset; must be driven low

during reset for Flash to be used as boot

memory

AIC FIQ Fast Interrupt Request Input – PIO-controlled after reset

IRQ0 - IRQ2 External Interrupt Request Input – PIO-controlled after reset

Timer

TCLK0 - TCLK2 Timer External Clock Input – PIO-controlled after reset

TIOA0 - TIOA2 Multi-purpose Timer I/O Pin A I/O – PIO-controlled after reset

TIOB0 - TIOB2 Multi-purpose Timer I/O Pin B I/O – PIO-controlled after reset

USART

SCK0 - SCK1 External Serial Clock I/O – PIO-controlled after reset

TXD0 - TXD1 Transmit Data Output Output – PIO-controlled after reset

RXD0 - RXD1 Receive Data Input Input – PIO-controlled after reset

PIO P0 - P31 Parallel IO Line I/O –

WD NWDOVF Watchdog Overflow Output Low Open drain

Clock MCKI Master Clock Input Input – Schmidt trigger

MCKO Master Clock Output Output –

Reset NRST Hardware Reset Input Input Low Schmidt trigger

NTRI Tri-state Mode Select Input Low Sampled during reset

ICE

TMS Test Mode Select Input – Schmidt trigger, internal pull-up

TDI Test Data Input Input – Schmidt trigger, internal pull-up

TDO Test Data Output Output –

TCK Test Clock Input – Schmidt trigger, internal pull-up

6174B–ATARM–07-Nov-05

AT91FR40162S Preliminary

Flash

Memory

NCSF Flash Memory Select Input Low Enables Flash Memory when pulled low

NBUSY Flash Memory Busy Output Output Low Flash RDY/BUSY signal; open-drain

NRSTF Flash Memory Reset Input Input Low Resets Flash to standard operating mode

Power

VDDIO Power Power – All VDDIO, VDDCORE and all GND pins

MUST be connected to their respective

supplies by the shortest route

VDDCORE Power Power –

GND Ground Ground –

VPP Write Protection Input Low Provides data protection (Program/Erase)

when VPP input is below 0.4V

Table 3-1. AT91FR40162S Signal Description (Continued)

Module Name Function Type

Active

Level Comments

6174B–ATARM–07-Nov-05

AT91FR40162S Preliminary

4. Block Diagram

Figure 4-1. AT91FR40162S

EBI: External Bus Interface

ASB

Controller

Clock

AMBA Bridge

EBI User

Interface

PIO: Parallel I/O Controller

D0-D15

A1- A19

A0/NLB

NRD/NOE

NWR0/NWE

NWR1/NUB

NWAIT

NCS0

NCS1

P26/NCS2

P27/NCS3

P29/A21/CS6

P30/A22/CS5

P31/A23/CS4

MCKI

P25/MCKO

P12/FIQ

P9/IRQ0

P10/IRQ1

P11/IRQ2

P13/SCK0

P14/TXD0

P15/RXD0

P20/SCK1

P21/TXD1/NTRI

P22/RXD1

P16

P17

P18

P19

P23

P24/BMS

Reset

NRST

WD: Watchdog Timer

NWDOVF

TC: Timer

Counter

TC0

TC1

P0/TCLK0

P3/TCLK1

P6/TCLK2

P1/TIOA0

P2/TIOB0

P4/TIOA1

P5/TIOB1

TC2 P7/TIOA2

P8/TIOB2

AIC: Advanced

Interrupt Controller

USART0

USART1

2 PDC

Channels

2 PDC

Channels

PS: Power Saving

APB

Chip ID

A1 - A19

D0 - D15

NCSF

VDDIO

NRSTF

NBUSY

OE WE

VPP

GND

VCC

BYTE

RESET

RDY/BUSY

VPP

GND

MCU

AT91R40008 FLASH MEMORY

ARM7TDMI Core

ASB

TMS

TDO

TDI

TCK

Embedded

ICE

VDDIO

GND SRAM

256K Bytes

A0 - A18

A20

P28/A20/NCS7

A0/NLB

A19

VDDCORE

D0 - D15

6174B–ATARM–07-Nov-05

AT91FR40162S Preliminary

5. Architectural Overview

The AT91FR40162S integrates Atmel’s AT91R40008 ARM Thumb processor and a 2-Mbyte

(16-Mbit) Flash memory die in a single compact 121-ball BGA package. The address, data and

control signals, except the Flash memory enable, are internally interconnected.

The AT91R40008 architecture consists of two main buses, the Advanced System Bus (ASB)

and the Advanced Peripheral Bus (APB). Designed for maximum performance and controlled by

the memory controller, the ASB interfaces the ARM7TDMI processor with the on-chip 32-bit

SRAM memory, the External Bus Interface (EBI) connected to the encapsulated Flash and the

AMBA™Bridge. The AMBA Bridge drives the APB, which is designed for accesses to on-chip

peripherals and optimized for low power consumption.

The AT91FR40162S implements the ICE port of the ARM7TDMI processor on dedicated pins,

offering a complete, low-cost and easy-to-use debug solution for target debugging.

5.1 Memories

The AT91FR40162S embeds 256K bytes of internal SRAM. The internal memory is directly con-

nected to the 32-bit data bus and is single-cycle accessible. This provides maximum

performance of 67 MIPS at 75 MHz by using the ARM instruction set of the processor, minimiz-

ing system power consumption and improving on the performance of separate memory

solutions.

The AT91FR40162S features an External Bus Interface (EBI), which enables connection of

external memories and application-specific peripherals. The EBI supports 8- or 16-bit devices

and can use two 8-bit devices to emulate a single 16-bit device. The EBI implements the early

read protocol, enabling faster memory accesses than standard memory interfaces.

The AT91FR40162S encapsulates a Flash memory organized as 1024K 16-bit words, accessed

via the EBI. A 16-bit Thumb instruction can be loaded from Flash memory in a single access.

Separate MCU and Flash memory reset inputs (NRST and NRSTF) are provided for maximum

flexibility. The user is thus free to tailor the reset operation to the application.

The AT91FR40162S integrates resident boot software called AT91 Flash Memory Uploader

software in the encapsulated Flash. The AT91 Flash Memory Uploader software is able to

upload program application software into its Flash memory.

5.2 Peripherals

The AT91FR40162S integrates several peripherals, which are classified as system or user

peripherals.

All on-chip peripherals are 32-bit accessible by the AMBA Bridge, and can be programmed with

a minimum number of instructions. The peripheral register set is composed of control, mode,

data, status and enable/disable/status registers.

An on-chip Peripheral Data Controller (PDC) transfers data between the on-chip USARTs and

on- and off-chip memory address space without processor intervention. Most importantly, the

PDC removes the processor interrupt handling overhead, making it possible to transfer up to

64K contiguous bytes without reprogramming the start address, thus increasing the perfor-

mance of the microcontroller, and reducing the power consumption.

6174B–ATARM–07-Nov-05

AT91FR40162S Preliminary

5.2.1 System Peripherals

The External Bus Interface (EBI) controls the external memory or peripheral devices via an 8- or

16-bit databus and is programmed through the APB. Each chip select line has its own program-

ming register.

The Power-saving (PS) module implements the Idle Mode (ARM7TDMI core clock stopped until

the next interrupt) and enables the user to adapt the power consumption of the microcontroller to

application requirements (independent peripheral clock control).

The Advanced Interrupt Controller (AIC) controls the internal interrupt sources from the internal

peripherals and the four external interrupt lines (including the FIQ) to provide an interrupt and/or

fast interrupt request to the ARM7TDMI. It integrates an 8-level priority controller, and, using the

Auto-vectoring feature, reduces the interrupt latency time.

The Parallel Input/Output Controller (PIO) controls up to 32 I/O lines. It enables the user to

select specific pins for on-chip peripheral input/output functions, and general-purpose input/out-

put signal pins. The PIO controller can be programmed to detect an interrupt on a signal change

from each line.

The Watchdog (WD) can be used to prevent system lock-up if the software becomes trapped in

a deadlock.

The Special Function (SF) module integrates the Chip ID, the Reset Status and the Protect

registers.

5.2.2 User Peripherals

Two USARTs, independently configurable, enable communication at a high baud rate in syn-

chronous or asynchronous mode. The format includes start, stop and parity bits and up to 8 data

bits. Each USART also features a Timeout and a Time Guard register, facilitating the use of the

two dedicated Peripheral Data Controller (PDC) channels.

The 3-channel, 16-bit Timer Counter (TC) is highly programmable and supports capture or

waveform modes. Each TC channel can be programmed to measure or generate different kinds

of waves, and can detect and control two input/output signals. The TC has also 3 external clock

signals.

6174B–ATARM–07-Nov-05

AT91FR40162S Preliminary

6. Product Overview

6.1 Power Supply

The AT91FR40162S device has two types of power supply pins:

• VDDCORE pins that power the chip core (i.e., the AT91R40008 with its embedded SRAM

and peripherals)

• VDDIO pins that power the AT91R40008 I/O lines and the Flash memory

An independent I/O supply allows a flexible adaptation to external component signal levels.

6.2 Input/Output Considerations

The AT91FR40162S I/O pads accept voltage levels up to the VDDIO power supply limit. After

the reset, the microcontroller peripheral I/Os are initialized as inputs to provide the user with

maximum flexibility. It is recommended that in any application phase, the inputs to the microcon-

troller be held at valid logic levels to minimize the power consumption.

6.3 Master Clock

The AT91FR40162S has a fully static design and works on the Master Clock (MCK), provided on

the MCKI pin from an external source.

The Master Clock is also provided as an output of the device on the pin MCKO, which is multi-

plexed with a general purpose I/O line. While NRST is active, and after the reset, the MCKO is

valid and outputs an image of the MCK signal. The PIO Controller must be programmed to use

this pin as standard I/O line.

6.4 Reset

Reset restores the default states of the user interface registers (defined in the user interface of

each peripheral), and forces the ARM7TDMI to perform the next instruction fetch from address

zero. Except for the program counter the ARM7TDMI registers do not have defined reset states.

6.4.1 NRST Pin

NRST is an active low-level input. It is asserted asynchronously, but exit from reset is synchro-

nized internally to the MCK. The signal presented on MCKI must be active within the

specification for a minimum of 10 clock cycles up to the rising edge of NRST to ensure correct

operation. The first processor fetch occurs 80 clock cycles after the rising edge of NRST.

6.4.2 Watchdog Reset

The watchdog can be programmed to generate an internal reset. In this case, the reset has the

same effect as the NRST pin assertion, but the pins BMS and NTRI are not sampled. Boot Mode

and Tri-state Mode are not updated. If the NRST pin is asserted and the watchdog triggers the

internal reset, the NRST pin has priority.

6174B–ATARM–07-Nov-05

AT91FR40162S Preliminary

6.5 Emulation Functions

6.5.1 Tri-state Mode

The AT91FR40162S microcontroller provides a tri-state mode, which is used for debug pur-

poses. This enables the connection of an emulator probe to an application board without having

to desolder the device from the target board. In tri-state mode, all the output pin drivers of the

AT91R40008 microcontroller are disabled.

In tri-state mode, direct access to the Flash via external pins is provided. This enables produc-

tion Flash programming using classical Flash programmers prior to board mounting.

To enter tri-state mode, the NTRI pin must be held low during the last 10 clock cycles before the

rising edge of NRST. For normal operation, the NTRI pin must be held high during reset by a

resistor of up to 400 kΩ.

NTRI is multiplexed with I/O line P21 and USART1 serial data transmit line TXD1.

6.5.2 JTAG/ICE Debug

ARM-standard embedded In-circuit Emulation is supported via the JTAG/ICE port. The pins TDI,

TDO, TCK and TMS are dedicated to this debug function and can be connected to a host com-

puter via the external ICE interface. In ICE Debug Mode, the ARM7TDMI core responds with a

non-JTAG chip ID that identifies the microcontroller. This is not fully IEEE1149.1 compliant.

6174B–ATARM–07-Nov-05

AT91FR40162S Preliminary

6.6 Memory Controller

The ARM7TDMI processor address space is 4G bytes. The memory controller decodes the

internal 32-bit address bus and defines three address spaces:

• Internal memories in the four lowest megabytes

• Middle space reserved for the external devices (memory or peripherals) controlled by the EBI

• Internal peripherals in the four highest megabytes

In any of these address spaces, the ARM7TDMI operates in little-endian mode only.

6.6.1 Internal Memories

The AT91FR40162S microcontroller integrates 256K bytes of internal SRAM. It is 32 bits wide

and single-clock cycle accessible. Byte (8-bit), half-word (16-bit) and word (32-bit) accesses are

supported and are executed within one cycle. Fetching either Thumb or ARM instructions is sup-

ported, and internal memory can store two times as many Thumb instructions as ARM

instructions.

The SRAM is mapped at address 0x0 (after the Remap command), allowing ARM7TDMI excep-

tion vectors between 0x0 and 0x20 to be modified by the software.

Placing the SRAM on-chip and using the 32-bit data bus bandwidth maximizes the microcontrol-

ler performance and minimizes system power consumption. The 32-bit bus increases the

effectiveness of the use of the ARM instruction set and the processing of data that is wider than

16 bits, thus making optimal use of the ARM7TDMI advanced performance.

Being able to dynamically update application software in the 256-Kbyte SRAM adds an extra

dimension to the AT91FR40162S.

The AT91FR40162S also integrates a 2-Mbyte Flash memory that is accessed via the External

Bus Interface. All data, address and control lines, except for the Chip Select signal, are con-

nected within the device.

6.6.2 Boot Mode Select

The ARM reset vector is at address 0x0. After the NRST line is released, the ARM7TDMI exe-

cutes the instruction stored at this address. This means that this address must be mapped in

nonvolatile memory after the reset. The input level on the BMS pin during the last 10 clock

cycles before the rising edge of the NRST selects the type of boot memory (see Table 3-1 on

page 3).

If the embedded Flash memory is to be used as boot memory, the BMS input must be pulled

down externally and NCS0 must be connected to NCSF externally.

The pin BMS is multiplexed with the I/O line P24 that can be programmed after reset like any

standard PIO line.

Table 6-1. Boot Mode Select

BMS Boot Memory

1 External 8-bit memory on NCS0

0 Internal or External 16-bit memory on NCS0

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