Atmel ATtiny26 User manual

1477G–AVR–03/05

Features

•High-performance, Low-power AVR®8-bit Microcontroller

•RISC Architecture

– 118 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 16 MIPS Throughput at 16 MHz

•Data and Non-volatile Program Memory

– 2K Bytes of In-System Programmable Program Memory Flash

Endurance: 10,000 Write/Erase Cycles

– 128 Bytes of In-System Programmable EEPROM

Endurance: 100,000 Write/Erase Cycles

– 128 Bytes Internal SRAM

– Programming Lock for Flash Program and EEPROM Data Security

•Peripheral Features

– 8-bit Timer/Counter with Separate Prescaler

– 8-bit High-speed Timer with Separate Prescaler

2 High Frequency PWM Outputs with Separate Output Compare Registers

Non-overlapping Inverted PWM Output Pins

– Universal Serial Interface with Start Condition Detector

– 10-bit ADC

11 Single Ended Channels

8 Differential ADC Channels

7 Differential ADC Channel Pairs with Programmable Gain (1x, 20x)

– On-chip Analog Comparator

– External Interrupt

– Pin Change Interrupt on 11 Pins

– Programmable Watchdog Timer with Separate On-chip Oscillator

•Special Microcontroller Features

– Low Power Idle, Noise Reduction, and Power-down Modes

– Power-on Reset and Programmable Brown-out Detection

– External and Internal Interrupt Sources

– In-System Programmable via SPI Port

– Internal Calibrated RC Oscillator

•I/O and Packages

– 20-lead PDIP/SOIC: 16 Programmable I/O Lines

– 32-lead QFN/MLF: 16 programmable I/O Lines

•Operating Voltages

– 2.7V - 5.5V for ATtiny26L

– 4.5V - 5.5V for ATtiny26

•Speed Grades

– 0 - 8 MHz for ATtiny26L

– 0 - 16 MHz for ATtiny26

•Power Consumption at 1 MHz, 3V and 25°C for ATtiny26L

– Active 16 MHz, 5V and 25°C: Typ 15 mA

– Active 1 MHz, 3V and 25°C: 0.70 mA

– Idle Mode 1 MHz, 3V and 25°C: 0.18 mA

– Power-down Mode: < 1 µA

8-bit

Microcontroller

with 2K Bytes

Flash

ATtiny26

ATtiny26L

Rev. 1477G–AVR–03/05

2ATtiny26(L) 1477G–AVR–03/05

Pin Configuration

Note: Note: The bottom pad under the QFN/MLF package should be soldered to ground.

(MOSI/DI/SDA/OC1A) PB0

(MISO/DO/OC1A) PB1

(SCK/SCL/OC1B) PB2

(OC1B) PB3

VCC

GND

(ADC7/XTAL1) PB4

(ADC8/XTAL2) PB5

(ADC9/INT0/T0) PB6

(ADC10/RESET) PB7

PA0 (ADC0)

PA1 (ADC1)

PA2 (ADC2)

PA3 (AREF)

GND

AVCC

PA4 (ADC3)

PA5 (ADC4)

PA6 (ADC5/AIN0)

PA7 (ADC6/AIN1)

PDIP/SOIC

MLF Top View

(OC1B) PB3

VCC

GND

(ADC7/XTAL1) PB4

(ADC8/XTAL2) PB5

PA2 (ADC2)

PA3 (AREF)

GND

AVCC

PA4 (ADC3)

(ADC9/INT0/T0) PB6

(ADC10/RESET) PB7

(ADC6/AIN1) PA7

(ADC5/AIN0) PA6

(ADC4) PA5

PB2 (SCK/SCL/OC1B)

PB1 (MISO/DO/OC1A)

PB0 (MOSI/DI/SDA/OC1A)

PA0 (ADC0)

PA1 (ADC1)

ATtiny26(L)

1477G–AVR–03/05

Description The ATtiny26(L) is a low-power CMOS 8-bit microcontroller based on the AVR

enhanced RISC architecture. By executing powerful instructions in a single clock cycle,

the ATtiny26(L) achieves throughputs approaching 1 MIPS per MHz allowing the system

designer to optimize power consumption versus processing speed.

The AVR core combines a rich instruction set with 32 general purpose working registers.

All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing

two independent registers to be accessed in one single instruction executed in one clock

cycle. The resulting architecture is more code efficient while achieving throughputs up to

ten times faster than conventional CISC microcontrollers. The ATtiny26(L) has a high

precision ADC with up to 11 single ended channels and 8 differential channels. Seven

differential channels have an optional gain of 20x. Four out of the seven differential

channels, which have the optional gain, can be used at the same time. The ATtiny26(L)

also has a high frequency 8-bit PWM module with two independent outputs. Two of the

PWM outputs have inverted non-overlapping output pins ideal for synchronous rectifica-

tion. The Universal Serial Interface of the ATtiny26(L) allows efficient software

implementation of TWI (Two-wire Serial Interface) or SM-bus interface. These features

allow for highly integrated battery charger and lighting ballast applications, low-end ther-

mostats, and firedetectors, among other applications.

The ATtiny26(L) provides 2K bytes of Flash, 128 bytes EEPROM, 128 bytes SRAM, up

to 16 general purpose I/O lines, 32 general purpose working registers, two 8-bit

Timer/Counters, one with PWM outputs, internal and external Oscillators, internal and

external interrupts, programmable Watchdog Timer, 11-channel, 10-bit Analog to Digital

Converter with two differential voltage input gain stages, and four software selectable

power saving modes. The Idle mode stops the CPU while allowing the Timer/Counters

and interrupt system to continue functioning. The ATtiny26(L) also has a dedicated ADC

Noise Reduction mode for reducing the noise in ADC conversion. In this sleep mode,

only the ADC is functioning. The Power-down mode saves the register contents but

freezes the oscillators, disabling all other chip functions until the next interrupt or hard-

ware reset. The Standby mode is the same as the Power-down mode, but external

oscillators are enabled. The wakeup or interrupt on pin change features enable the

ATtiny26(L) to be highly responsive to external events, still featuring the lowest power

consumption while in the Power-down mode.

The device is manufactured using Atmel’s high density non-volatile memory technology.

By combining an enhanced RISC 8-bit CPU with Flash on a monolithic chip, the

ATtiny26(L) is a powerful microcontroller that provides a highly flexible and cost effec-

tive solution to many embedded control applications.

The ATtiny26(L) AVR is supported with a full suite of program and system development

tools including: Macro assemblers, program debugger/simulators, In-circuit emulators,

and evaluation kits.

4ATtiny26(L) 1477G–AVR–03/05

Block Diagram Figure 1. The ATtiny26(L) Block Diagram

WATCHDOG

TIMER

MCU CONTROL

UNIVERSAL

SERIAL

INTERFACE

TIMER/

COUNTER0

DATA DIR.

REG.PORT A

DATA REGISTER

PORT A

PROGRAMMING

LOGIC

TIMING AND

CONTROL

TIMER/

COUNTER1

MCU STATUS

PORT A DRIVERS

PA0-PA7

VCC

GND

ANALOG

COMPARATOR

8-BIT DATA BUS

ADC

ISP INTERFACE

INTERRUPT

UNIT

EEPROM

INTERNAL

OSCILLATOR

OSCILLATORS

CALIBRATED

OSCILLATOR

INTERNAL

DATA DIR.

REG.PORT B

DATA REGISTER

PORT B

PORT B DRIVERS

PB0-PB7

PROGRAM

COUNTER

STACK

POINTER

PROGRAM

FLASH SRAM

GENERAL

PURPOSE

REGISTERS

INSTRUCTION

DECODER

STATUS

ALU

CONTROL

LINES

AVCC

ATtiny26(L)

1477G–AVR–03/05

Pin Descriptions

VCC Digital supply voltage pin.

GND Digital ground pin.

AVCC AVCC is the supply voltage pin for Port A and the A/D Converter (ADC). It should be

externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be

connected to VCC through a low-pass filter. See page 94 for details on operating of the

ADC.

Port A (PA7..PA0) Port A is an 8-bit general purpose I/O port. PA7..PA0 are all I/O pins that can provide

internal pull-ups (selected for each bit). Port A has alternate functions as analog inputs

for the ADC and analog comparator and pin change interrupt as described in “Alternate

Port Functions” on page 46.

Port B (PB7..PB0) Port B is an 8-bit general purpose I/O port. PB6..0 are all I/O pins that can provide inter-

nal pull-ups (selected for each bit). PB7 is an I/O pin if not used as the reset. To use pin

PB7 as an I/O pin, instead of RESET pin, program (“0”) RSTDISBL Fuse. Port B has

alternate functions for the ADC, clocking, timer counters, USI, SPI programming, and

pin change interrupt as described in “Alternate Port Functions” on page 46.

An External Reset is generated by a low level on the PB7/RESET pin. Reset pulses

longer than 50 ns will generate a reset, even if the clock is not running. Shorter pulses

are not guaranteed to generate a reset.

XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2 Output from the inverting oscillator amplifier.

About Code

Examples This datasheet contains simple code examples that briefly show how to use various

parts of the device. These code examples assume that the part specific header file is

included before compilation. Be aware that not all C compiler vendors include bit defini-

tions in the header files and interrupt handling in C is compiler dependent. Please

confirm with the C compiler documentation for more details.

6ATtiny26(L) 1477G–AVR–03/05

AVR CPU Core

Architectural Overview The fast-access Register File concept contains 32 x 8-bit general purpose working reg-

isters with a single clock cycle access time. This means that during one single clock

cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output

from the Register File, the operation is executed, and the result is stored back in the

Six of the 32 registers can be used as 16-bit pointers for indirect memory access. These

pointers are called the X-, Y-, and Z-pointers, and they can address the Register File

and the Flash program memory.

Figure 2. The ATtiny26(L) AVR Enhanced RISC Architecture

The ALU supports arithmetic and logic functions between registers or between a con-

stant and a register. Single register operations are also executed in the ALU. Figure 2

shows the ATtiny26(L) AVR Enhanced RISC microcontroller architecture. In addition to

the register operation, the conventional memory addressing modes can be used on the

lowermost Data Space addresses ($00 - $1F), allowing them to be accessed as though

they were ordinary memory locations.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control

Registers, Timer/Counters, A/D Converters, and other I/O functions. The I/O Memory

can be accessed directly, or as the Data Space locations following those of the Register

File, $20 - $5F.

1024 x 16

Program

FLASH

Instruction

Decoder

Program

Counter

Control Lines

32 x 8

General

Purpose

Registers

ALU

Direct Addressing

Indirect Addressing

Status

and Test

Control

Registers

Interrupt

Unit

2 x 8-bit

Timer/Counter

Universal

Serial Interface

Watchdog

Timer

Analog

Comparator

I/O Lines

8-bit Data Bus

ISP Unit

ADC

128 x 8

SRAM

128 byte

EEPROM

ATtiny26(L)

1477G–AVR–03/05

The AVR uses a Harvard architecture concept with separate memories and buses for

program and data memories. The program memory is accessed with a two stage

pipelining. While one instruction is being executed, the next instruction is pre-fetched

from the program memory. This concept enables instructions to be executed in every

clock cycle. The program memory is In-System programmable Flash memory.

With the relative jump and relative call instructions, the whole address space is directly

accessed. All AVR instructions have a single 16-bit word format, meaning that every

program memory address contains a single 16-bit instruction.

During interrupts and subroutine calls, the return address program counter (PC) is

stored on the Stack. The Stack is effectively allocated in the general data SRAM, and

consequently the stack size is only limited by the total SRAM size and the usage of the

SRAM. All user programs must initialize the SP in the reset routine (before subroutines

or interrupts are executed). The 8-bit Stack Pointer SP is read/write accessible in the I/O

space. For programs written in C, the stack size must be declared in the linker file. Refer

to the C user guide for more information.

The 128 bytes data SRAM can be easily accessed through the five different addressing

modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control

Registers, Timer/Counters, and other I/O functions. The memory spaces in the AVR

architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional

Global Interrupt Enable bit in the Status Register. All the different interrupts have a sep-

arate Interrupt Vector in the Interrupt Vector table at the beginning of the program

memory. The different interrupts have priority in accordance with their Interrupt Vector

position. The lower the Interrupt Vector address, the higher the priority.

General Purpose

Figure 3. AVR CPU General Purpose Working Registers

7 0 Addr.

R0 $00

R1 $01

R2 $02

…

R13 $0D

General R14 $0E

Purpose R15 $0F

Working R16 $10

Registers R17 $11

…

R26 $1A X-register Low Byte

R27 $1B X-register High Byte

R28 $1C Y-register Low Byte

R29 $1D Y-register High Byte

R30 $1E Z-register Low Byte

R31 $1F Z-register High Byte

8ATtiny26(L) 1477G–AVR–03/05

All of the register operating instructions in the instruction set have direct and single cycle

access to all registers. The only exceptions are the five constant arithmetic and logic

instructions SBCI, SUBI, CPI, ANDI, and ORI between a constant and a register, and

the LDI instruction for load immediate constant data. These instructions apply to the

second half of the registers in the Register File – R16..R31. The general SBC, SUB, CP,

AND, and OR, and all other operations between two registers or on a single register

apply to the entire Register File.

As shown in Figure 3, each register is also assigned a data memory address, mapping

them directly into the first 32 locations of the user Data Space. Although not being phys-

ically implemented as SRAM locations, this memory organization provides flexibility in

access of the registers, as the X-, Y-, and Z-registers can be set to index any register in

the file.

X-register, Y-register, and Z-

These registers are address pointers for indirect addressing of the Data Space. The

three indirect address registers X, Y, and Z are defined as:

Figure 4. X-, Y-, and Z-register

In the different addressing modes, these address registers have functions as fixed dis-

placement, automatic increment and decrement (see the descriptions for the different

instructions).

ALU – Arithmetic Logic

Unit The high-performance AVR ALU operates in direct connection with all 32 general pur-

pose working registers. Within a single clock cycle, ALU operations between registers in

the Register File are executed. The ALU operations are divided into three main catego-

ries – Arithmetic, Logical, and Bit-functions.

15 0

X-register 7 0 7 0

R27 ($1B) R26 ($1A)

15 0

Y-register 7 0 7 0

R29 ($1D) R28 ($1C)

15 0

Z-register 7 0 7 0

R31 ($1F) R30 ($1E)

ATtiny26(L)

1477G–AVR–03/05

Status Register – SREG The AVR Status Register – SREG – at I/O space location $3F is defined as:

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set (one) for the interrupts to be enabled. The

individual interrupt enable control is then performed in the Interrupt Mask Registers –

GIMSK and TIMSK. If the Global Interrupt Enable Register is cleared (zero), none of the

interrupts are enabled independent of the GIMSK and TIMSK values. The I-bit is cleared

by hardware after an interrupt has occurred, and is set by the RETI instruction to enable

subsequent interrupts. The I-bit can also be set and cleared by the application with the

SEI and CLI instructions, as described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source

and destination for the operated bit. A bit from a register in the Register File can be cop-

ied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. See the

Instruction Set Description for detailed information.

• Bit 4 – S: Sign Bit, S = N ⊕V

The S-bit is always an exclusive or between the Negative Flag N and the Two’s Comple-

ment Overflow Flag V. See the Instruction Set Description for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See

the Instruction Set Description for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result after the different arithmetic and logic

operations. See the Instruction Set Description for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result after the different arithmetic and logic opera-

tions. See the Instruction Set Description for detailed information.

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the Instruction

Set Description for detailed information.

Bit 76543210

$3F ($5F) I T H S V N Z C SREG

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

10 ATtiny26(L) 1477G–AVR–03/05

Stack Pointer – SP The ATtiny26(L) Stack Pointer is implemented as an 8-bit register in the I/O space loca-

tion $3D ($5D). As the ATtiny26(L) data memory has 224 ($E0) locations, eight bits are

used.

The Stack Pointer points to the data SRAM stack area where the Subroutine and Inter-

rupt Stacks are located. This Stack space in the data SRAM must be defined by the

program before any subroutine calls are executed or interrupts are enabled. The Stack

Pointer must be set to point above $60. The Stack Pointer is decremented by one when

data is pushed onto the Stack with the PUSH instruction, and it is decremented by two

when an address is pushed onto the Stack with subroutine calls and interrupts. The

Stack Pointer is incremented by one when data is popped from the Stack with the POP

instruction, and it is incremented by two when an address is popped from the Stack with

return from subroutine RET or return from interrupt RETI.

Program and Data

Addressing Modes The ATtiny26(L) AVR Enhanced RISC microcontroller supports powerful and efficient

addressing modes for access to the Flash program memory, SRAM, Register File, and

I/O Data memory. This section describes the different addressing modes supported by

the AVR architecture. In the figures, OP means the operation code part of the instruction

word. To simplify, not all figures show the exact location of the addressing bits.

The operand is contained in register d (Rd).

Bit 76543210

$3D ($5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SP

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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