Atmel ATmega161 User manual

Features

•High-performance, Low-power AVR®8-bit Microcontroller

•Advanced RISC Architecture

– 130 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 8 MIPS Throughput at 8 MHz

– On-chip 2-cycle Multiplier

•Program and Data Memories

– 16K Bytes of Nonvolatile In-System Programmable Flash Endurance: 1,000

Write/Erase Cycles

– Optional Boot Code Memory with Independent Lock Bits Self-programming of

Program and Data Memories

– 512 Bytes of Nonvolatile In-System Programmable EEPROM Endurance: 100,000

Write/Erase Cycles

– 1K Byte of Internal SRAM

– Programming Lock for Software Security

•Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescaler and PWM

– Expanded 16-bit Timer/Counter System with Separate Prescaler, Compare,

Capture Modes and Dual 8-, 9-, or 10-bit PWM

– Dual Programmable Serial UARTs

– Master/Slave SPI Serial Interface

– Real-time Counter with Separate Oscillator

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

•Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– External and Internal Interrupt Sources

– Three Sleep Modes: Idle, Power-save and Power-down

•Power Comsumption at 4 MHz, 3.0V, 25°C

– Active 3.0 mA

– Idle Mode 1.2 mA

– Power-down Mode < 1 µA

•I/O and Packages

– 35 Programmable I/O Lines

– 40-lead PDIP and 44-lead TQFP

•Operating Voltages

– 2.7V - 5.5V for the ATmega161L

– 4.0V - 5.5V for the ATmega161

•Speed Grades

– 0 - 4 MHz for the ATmega161L

– 0 - 8 MHz for the ATmega161

•Commercial and Industrial Temperature Ranges

8-bit

Microcontroller

with 16K Bytes

of In-System

Programmable

Flash

ATmega161

ATmega161L

Rev. 1228B–09/01

2ATmega161(L)

1228B–09/01

Pin Configuration

(OC0/T0) PB0

(OC2/T1) PB1

(RXD1/AIN0) PB2

(TXD1/AIN1) PB3

(SS) PB4

(MOSI) PB5

(MISO) PB6

(SCK) PB7

RESET

(RXD0) PD0

(TXD0) PD1

(INT0) PD2

(INT1) PD3

(TOSC1) PD4

(OC1A/TOSC2) PD5

(WR) PD6

(RD) PD7

XTAL2

XTAL1

GND

VCC

PA0 (AD0)

PA1 (AD1)

PA2 (AD2)

PA3 (AD3)

PA4 (AD4)

PA5 (AD5)

PA6 (AD6)

PA7 (AD7)

PE0 (ICP/INT2)

PE1 (ALE)

PE2 (OC1B)

PC7 (A15)

PC6 (A14)

PC5 (A13)

PC4 (A12)

PC3 (A11)

PC2 (A10)

PC1 (A9)

PC0 (A8)

(MOSI) PB5

(MISO) PB6

(SCK) PB7

RESET

(RXD0) PD0

NC*

(TXD0) PD1

(INT0) PD2

(INT1) PD3

(TOSC1) PD4

(OCIA/TOSC2) PD5

PA4 (AD4)

PA5 (AD5)

PA6 (AD6)

PA7 (AD7)

PE0 (ICP/INT2)

NC*

PE1 (ALE)

PE2 (OC1B)

PC7 (A15)

PC6 (A14)

PC5 (A13)

(WR) PD6

(RD) PD7

XTAL2

XTAL1

GND

NC*

(A8) PC0

(A9) PC1

(A10) PC2

(A11) PC3

(A12) PC4

PB4 (SS)

PB3 (TXD1/AIN1)

PB2 (RXD1/AIN0)

PB1 (OC2/T1)

PB0 (OC0/T0)

NC*

VCC

PA0 (AD0)

PA1 (AD1)

PA2 (AD2)

PA3 (AD3)

* NC = Do not connect

(Can be used in future devices)

TQFP

PDIP

ATmega161(L)

1228B–09/01

Description The ATmega161 is a low-power CMOS 8-bit microcontroller based on the AVR RISC

architecture. By executing powerful instructions in a single clock cycle, the ATmega161

achieves throughputs approaching 1 MIPS per MHz allowing the system designer to

optimize power consumption versus processing speed. The AVR core combines a rich

instruction set with 32 general purpose working registers. All the 32 registers are directly

connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be

accessed in one single instruction executed in one clock cycle. The resulting architec-

ture is more code-efficient while achieving throughputs up to ten times faster than

conventional CISC microcontrollers.

The ATmega161 provides the following features: 16K bytes of In-System or Self-

programmable Flash, 512 bytes EEPROM, 1K byte of SRAM, 35 general-purpose I/O

lines, 32 general purpose working registers, Real-time Counter, 3 flexible timer/counters

with compare modes, internal and external interrupts, 2 programmable serial UARTs,

programmable Watchdog Timer with internal oscillator, an SPI serial port and 3 soft-

ware-selectable power saving modes. The Idle mode stops the CPU while allowing the

SRAM, timer/counters, SPI port and interrupt system to continue functioning. The

Power-down mode saves the register and SRAM contents but freezes the oscillator, dis-

abling all other chip functions until the next external interrupt or hardware reset. In

Power-save mode, the timer oscillator continues to run, allowing the user to maintain a

timer base while the rest of the device is sleeping.

The device is manufactured using Atmel’s high-density nonvolatile memory technology.

The On-chip Flash program memory can be reprogrammed using the self-programming

capability through the boot block and an ISP through the SPI port, or by using a conven-

tional nonvolatile memory programmer. By combining an enhanced RISC 8-bit CPU with

In-System Programmable Flash on a monolithic chip, the Atmel ATmega161 is a power-

ful microcontroller that provides a highly flexible and cost-effective solution to many

embedded control applications.

The ATmega161 AVR is supported with a full suite of program and system development

tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit

emulators and evaluation kits.

4ATmega161(L)

1228B–09/01

Block Diagram Figure 1. The ATmega161 Block Diagram

PROGRAMMING

LOGIC SPI UARTS

PB0 - PB7

VCC

GND

ANALOG

COMPARATOR

8-BIT DATA BUS

DATA DIR.

REG. PORTA

DATA REGISTER

PORTA

PORTA DRIVERS

PA0-PA7

DATA DIR.

REG. PORTC

DATA REGISTER

PORTC

PORTC DRIVERS

PC0-PC7

PORTD DRIVERS

PD0 - PD7

DATA DIR.

REG. PORTD

DATA REGISTER

PORTB

PORTB DRIVERS PORTE DRIVERS

PE0 - PE2

DATA REG.

PORTE

DATA DIR

REG. PORTE

PROGRAM

COUNTER

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

STACK

POINTER

PROGRAM

FLASH

MCU CONTROL

SRAM

GENERAL

PURPOSE

REGISTERS

INSTRUCTION

TIMER/

COUNTERS

INSTRUCTION

DECODER

TIMING AND

CONTROL

OSCILLATOR

INTERRUPT

UNIT

EEPROM

STATUS

ALU

RESET

XTAL2

XTAL1

CONTROL

LINES

DATA DIR.

REG. PORTB

DATA REGISTER

PORTD

ATmega161(L)

1228B–09/01

Pin Descriptions

VCC Supply voltage.

GND Ground.

Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors

(selected for each bit). The Port A output buffers can sink 20 mA and can drive LED dis-

plays directly. When pins PA0 to PA7 are used as inputs and are externally pulled low,

they will source current if the internal pull-up resistors are activated. The Port A pins are

tri-stated when a reset condition becomes active, even if the clock is not running.

Port A serves as a Multiplexed Address/Data port when using external memory

interface.

Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port B output

buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port B also serves the functions of various special features of the ATmega161 as listed

on page 90.

Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port C output

buffers can sink 20 mA. As inputs, Port C pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port C also serves as an address high output when using external memory interface.

Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port D output

buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port D also serves the functions of various special features of the ATmega161 as listed

on page 99.

Port E (PE2..PE0) Port E is a 3-bit bi-directional I/O port with internal pull-up resistors. The Port E output

buffers can sink 20 mA. As inputs, Port E pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port E also serves the functions of various special features of the ATmega161 as listed

on page 105.

RESET Reset input. A low level on this pin for more than 500 ns will generate a reset, even if the

clock is not running. Shorter pulses are not guaranteed to generate a reset.

XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2 Output from the inverting oscillator amplifier.

6ATmega161(L)

1228B–09/01

Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier that can

be configured for use as an on-chip oscillator, as shown in Figure 2. Either a quartz

crystal or a ceramic resonator may be used. To drive the device from an external clock

source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 3.

Figure 2. Oscillator Connections

Figure 3. External Clock Drive Configuration

XTAL2

XTAL1

GND

XTAL2

XTAL1

GND

EXTERNAL

OSCILLATOR

SIGNAL

ATmega161(L)

1228B–09/01

Architectural

Overview

The fast-access register file concept contains 32 x 8-bit general purpose working regis-

ters with a single clock cycle access time. This means that during one single clock cycle,

one Arithmetic Logic Unit (ALU) operation is executed. Two operands are output from

the register file, the operation is executed and the result is stored back in the register file

–in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for

Data Space addressing –enabling efficient address calculations. One of the three

address pointers is also used as the address pointer for the constant table look-up func-

tion. These added function registers are the 16-bit X-register, Y-register and Z-register.

The ALU supports arithmetic and logic functions between registers or between a con-

stant and a register. Single register operations are also executed in the ALU. Figure 4

shows the ATmega161 AVR RISC microcontroller architecture.

Figure 4. The ATmega161 AVR RISC Architecture

8K x 16

Program

Memory

Instruction

Decoder

Program

Counter

Control Lines

32 x 8

General

Purpose

Registers

ALU

Status

and Control

Interrupt

Unit

SPI

Unit

8-bit

Timer/Counter

with PWM

and RTC

Watchdog

Timer

Analog

Comparator

I/O Lines

512 x 8

EEPROM

Data Bus 8-bit

Serial

UART0

16-bit

Timer/Counter

with PWM

8-bit

Timer/Counter

with PWM

1024 x 8

Data

SRAM

Direct Addressing

Indirect Addressing

Serial

UART1

8ATmega161(L)

1228B–09/01

In addition to the register operation, the conventional memory addressing modes can be

used on the register file. This is enabled by the fact that the register file is assigned the

32 lowermost Data Space addresses ($00 - $1F), allowing them to be accessed as

though they were ordinary memory locations.

The I/O memory space contains 64 addresses for CPU peripheral functions such as

Control Registers, Timer/Counters, and other I/O functions. The I/O memory can be

accessed directly or as the Data Space locations following those of the register file,

$20 - $5F.

The AVR uses a Harvard architecture concept –with separate memories and buses for

program and data. The program memory is executed with a two-stage pipeline. While

one instruction is being executed, the next instruction is pre-fetched from the program

memory. This concept enables instructions to be executed in every clock cycle. The pro-

gram memory is Self-programmable Flash memory.

With the jump and call instructions, the whole 8K word address space is directly

accessed. Most AVR instructions have a single 16-bit word format. Every program mem-

ory address contains a 16- or 32-bit instruction.

During interrupts and subroutine calls, the return address program counter (PC) is

stored on the stack. The stack is effectively allocated in the general data SRAM and,

consequently, the stack size is only limited by the total SRAM size and the usage of the

SRAM. All user programs must initialize the SP (stack pointer) in the reset routine

(before subroutines or interrupts are executed). The 16-bit stack pointer is read/write

accessible in the I/O space.

The 1K byte data SRAM can be easily accessed through the five different addressing

modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

ATmega161(L)

1228B–09/01

Figure 5. Memory Maps

A flexible interrupt module has its control registers in the I/O space with an additional

global interrupt enable bit in the status register. All the different interrupts have a sepa-

rate interrupt vector in the interrupt vector table at the beginning of the program

memory. The different interrupts have priority in accordance with their interrupt vector

position. The lower the interrupt vector address, the higher the priority.

32 Gen. Purpose

Working Registers

64 I/O Registers

Internal SRAM

(1024 x 8)

$0000

$001F

$005F

$0060

$045F

$0020

$000

$1FFF

Data Memory

Program Memory

Program Flash

(8K x 16)

$0460

External SRAM

(0 - 63K x 8)

$FFFF

10 ATmega161(L)

1228B–09/01

The General Purpose

Figure 6 shows the structure of the 32 general purpose working registers in the CPU.

Figure 6. AVR CPU General Purpose Working Registers

All the register operating instructions in the instruction set have direct and single cycle

access to all registers. The only exceptions are the five constant arithmetic and logic

instructions SBCI, SUBI, CPI, ANDI, and ORI between a constant and a register, and

the LDI instruction for load immediate constant data. These instructions apply to the

second half of the registers in the register file –R16..R31. The general SBC, SUB, CP,

AND, and OR, and all other operations between two registers or on a single register

apply to the entire register file.

As shown in Figure 6, each register is also assigned a data memory address, mapping

them directly into the first 32 locations of the user Data Space. Although not being phys-

ically implemented as SRAM locations, this memory organization provides great

flexibility in access of the registers, as the X-, Y-, and Z-registers can be set to index any

The X-register, Y-register and

Z-register

The registers R26..R31 have some added functions to their general purpose usage.

These registers are address pointers for indirect addressing of the Data Space. The

three indirect address registers X, Y, and Z are defined as:

Figure 7. X-, Y-, and Z-registers

7 0 Addr.

R0 $00

R1 $01

R2 $02

…

R13 $0D

General R14 $0E

Purpose R15 $0F

Working R16 $10

Registers R17 $11

…

R26 $1A X-register low byte

R27 $1B X-register high byte

R28 $1C Y-register low byte

R29 $1D Y-register high byte

R30 $1E Z-register low byte

R31 $1F Z-register high byte

15 0

X-register 7 0 7 0

R27 ($1B) R26 ($1A)

15 0

Y-register 7 0 7 0

R29 ($1D) R28 ($1C)

15 0

Z-register 7 0 7 0

R31 ($1F) R30 ($1E)

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