Atmel AVR AT90CAN32 User manual

Features

•High-performance, Low-power AVR®8-bit Microcontroller

•Advanced RISC Architecture

– 133 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers + Peripheral Control Registers

– Fully Static Operation

– Up to 16 MIPS Throughput at 16 MHz

– On-chip 2-cycle Multiplier

•Non volatile Program and Data Memories

– 32K/64K/128K Bytes of In-System Reprogrammable Flash (AT90CAN32/64/128)

• Endurance: 10,000 Write/Erase Cycles

– Optional Boot Code Section with Independent Lock Bits

• Selectable Boot Size: 1K Bytes, 2K Bytes, 4K Bytes or 8K Bytes

• In-System Programming by On-Chip Boot Program (CAN, UART, ...)

• True Read-While-Write Operation

– 1K/2K/4K

Bytes EEPROM (Endurance: 100,000 Write/Erase Cycles) (AT90CAN32/64/128)

– 2K/4K/4K Bytes Internal SRAM (AT90CAN32/64/128)

– Up to 64K Bytes Optional External Memory Space

– Programming Lock for Software Security

•JTAG (IEEE std. 1149.1 Compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard

– Programming Flash (Hardware ISP), EEPROM, Lock & Fuse Bits

– Extensive On-chip Debug Support

•CAN Controller 2.0A & 2.0B - ISO 16845 Certified (1)

– 15 Full Message Objects with Separate Identifier Tags and Masks

– Transmit, Receive, Automatic Reply and Frame Buffer Receive Modes

– 1Mbits/s Maximum Transfer Rate at 8 MHz

– Time stamping, TTC & Listening Mode (Spying or Autobaud)

•Peripheral Features

– Programmable Watchdog Timer with On-chip Oscillator

– 8-bit Synchronous Timer/Counter-0

• 10-bit Prescaler

• External Event Counter

• Output Compare or 8-bit PWM Output

– 8-bit Asynchronous Timer/Counter-2

• 10-bit Prescaler

• External Event Counter

• Output Compare or 8-Bit PWM Output

• 32Khz Oscillator for RTC Operation

– Dual 16-bit Synchronous Timer/Counters-1 & 3

• 10-bit Prescaler

• Input Capture with Noise Canceler

• External Event Counter

• 3-Output Compare or 16-Bit PWM Output

• Output Compare Modulation

– 8-channel, 10-bit SAR ADC

• 8 Single-ended Channels

• 7 Differential Channels

• 2 Differential Channels With Programmable Gain at 1x, 10x, or 200x

– On-chip Analog Comparator

– Byte-oriented Two-wire Serial Interface

– Dual Programmable Serial USART

– Master/Slave SPI Serial Interface

• Programming Flash (Hardware ISP)

•Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated RC Oscillator

– 8 External Interrupt Sources

– 5 Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down & Standby

– Software Selectable Clock Frequency

– Global Pull-up Disable

•I/O and Packages

– 53 Programmable I/O Lines

– 64-lead TQFP and 64-lead QFN

•Operating Voltages: 2.7 - 5.5V

•Operating temperature: Industrial (-40°C to +85°C)

•Maximum Frequency: 8 MHz at 2.7V, 16 MHz at 4.5V

Note: 1. Details on section 19.4.3 on page 242. Rev. 7679H–CAN–08/08

8-bit

Microcontroller

with

32K/64K/128K

Bytes of

ISP Flash

and

CAN Controller

AT90CAN32

AT90CAN64

AT90CAN128

27679H–CAN–08/08

AT90CAN32/64/128

1. Description

1.1 Comparison Between AT90CAN32, AT90CAN64 and AT90CAN128

AT90CAN32, AT90CAN64 and AT90CAN128 are hardware and software compatible. They dif-

fer only in memory sizes as shown in Table 1-1.

1.2 Part Description

The AT90CAN32/64/128 is a low-power CMOS 8-bit microcontroller based on the AVR

enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the

AT90CAN32/64/128 achieves throughputs approaching 1 MIPS per MHz allowing the system

designer to optimize power consumption versus processing speed.

The AVR core combines a rich instruction set with 32 general purpose working registers. All 32

registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting

architecture is more code efficient while achieving throughputs up to ten times faster than con-

ventional CISC microcontrollers.

The AT90CAN32/64/128 provides the following features: 32K/64K/128K bytes of In-System Pro-

grammable Flash with Read-While-Write capabilities, 1K/2K/4K bytes EEPROM, 2K/4K/4K

bytes SRAM, 53 general purpose I/O lines, 32 general purpose working registers, a CAN con-

troller, Real Time Counter (RTC), four flexible Timer/Counters with compare modes and PWM, 2

USARTs, a byte oriented Two-wire Serial Interface, an 8-channel 10-bit ADC with optional differ-

ential input stage with programmable gain, a programmable Watchdog Timer with Internal

Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for

accessing the On-chip Debug system and programming and five software selectable power sav-

ing modes.

The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI/CAN ports and

interrupt system to continue functioning. The Power-down mode saves the register contents but

freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware

Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to main-

tain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops

the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise

during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the

rest of the device is sleeping. This allows very fast start-up combined with low power

consumption.

The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On-

chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial

interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program

running on the AVR core. The boot program can use any interface to download the application

program in the application Flash memory. Software in the Boot Flash section will continue to run

while the Application Flash section is updated, providing true Read-While-Write operation. By

Table 1-1. Memory Size Summary

Device Flash EEPROM RAM

AT90CAN32 32K Bytes 1K Byte 2K Bytes

AT90CAN64 64K Bytes 2K Bytes 4K Bytes

AT90CAN128 128K Bytes 4K Byte 4K Bytes

7679H–CAN–08/08

AT90CAN32/64/128

combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip,

the Atmel AT90CAN32/64/128 is a powerful microcontroller that provides a highly flexible and

cost effective solution to many embedded control applications.

The AT90CAN32/64/128 AVR is supported with a full suite of program and system development

tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emula-

tors, and evaluation kits.

1.3 Disclaimer Typical values contained in this datasheet are based on simulations and characterization of

other AVR microcontrollers manufactured on the same process technology. Min and Max values

will be available after the device is characterized.

47679H–CAN–08/08

AT90CAN32/64/128

1.4 Block Diagram

Figure 1-1. Block Diagram

PROGRAM

COUNTER STACK

POINTER

PROGRAM

FLASH MCU CONTROL

SRAM

GENERAL

PURPOSE

REGISTERS

INSTRUCTION

COUNTERS

INSTRUCTION

DECODER

DATA DIR.

REG. PORTB

DATA DIR.

REG. PORTE

DATA DIR.

REG. PORTA

DATA DIR.

REG. PORTD

DATA REGISTER

PORTB

DATA REGISTER

PORTE

DATA REGISTER

PORTA

DATAREGISTER

PORTD

INTERRUPT

UNIT

EEPROM

SPIUSART0

STATUS

ALU

PORTB DRIVERS

PORTE DRIVERS

PORTA DRIVERS

PORTF DRIVERS

PORTD DRIVERS

PORTC DRIVERS

PB7 - PB0PE7 - PE0

PA7 - PA0PF7 - PF0

RESET

VCC

AGND

GND

AREF

XTAL1

XTAL2

CONTROL

LINES

ANALOG

COMPARATOR

PC7 - PC0

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

8-BIT DATA BUS

AVCC

USART1

TIMING AND

CONTROL

OSCILLATOR

CALIB. OSC

DATA DIR.

REG. PORTC

DATA REGISTER

PORTC

ON-CHIP DEBUG

JTAG TAP

PROGRAMMING

LOGIC

BOUNDARY-

SCAN

DATA DIR.

REG. PORTF

DATA REGISTER

PORTF

ADC

POR - BOD

RESET

PD7 - PD0

DATA DIR.

REG. PORTG

DATAREG.

PORTG

PORTG DRIVERS

PG4 - PG0

TWO-WIRE SERIAL

INTERFACE

CAN

CONTROLLER

7679H–CAN–08/08

AT90CAN32/64/128

1.5 Pin Configurations

Figure 1-2. Pinout AT90CAN32/64/128 - TQFP

PC0 (A8)

VCC

GND

PF0 (ADC0)

PF7 (ADC7 / TDI)

PF1 (ADC1)

PF2 (ADC2)

PF3 (ADC3)

PF4 (ADC4 / TCK)

PF5 (ADC5 / TMS)

PF6 (ADC6 / TDO)

AREF

GND

AVCC

(RXD0 / PDI) PE0

(TXD0 / PDO) PE1

(XCK0 / AIN0) PE2

(OC3A / AIN1) PE3

(OC3B / INT4) PE4

(OC3C / INT5) PE5

(T3 / INT6) PE6

(ICP3 / INT7) PE7

(SS) PB0

(SCK) PB1

(MOSI) PB2

(MISO) PB3

(OC2A) PB4

(OC0A / OC1C) PB7

(TOSC2 ) PG3

(OC1B) PB6

(TOSC1 ) PG4

(OC1A) PB5

PC1 (A9)

(T0) PD7

PC2 (A10)

PC3 (A11)

PC4 (A12)

PC5 (A13)

PC6 (A14)

PC7 (A15 / CLKO)

PA7 (AD7)

PG2 (ALE)

PA6 (AD6)

PA5 (AD5)

PA4 (AD4)

PA3 (AD3)

PA0 (AD0)

PA1 (AD1)

PA2 (AD2)

(RXCAN / T1) PD6

(TXCAN / XCK1) PD5

(ICP1) PD4

(TXD1 / INT3) PD3

(RXD1 / INT2) PD2

(SDA / INT1) PD1

(SCL / INT0) PD0

XTAL1

XTAL2

RESET

GND

VCC

PG1 (RD)

PG0 (WR)

(2)

NC = Do not connect (May be used in future devices)

(1)

Timer2 Oscillator

(2)

NC(1)

(64-lead TQFP top view)

INDEX CORNER

67679H–CAN–08/08

AT90CAN32/64/128

Figure 1-3. Pinout AT90CAN32/64/128 - QFN

Note: The large center pad underneath the QFN package is made of metal and internally connected to

GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center

pad is left unconnected, the package might loosen from the board.

1.6 Pin Descriptions

1.6.1 VCC Digital supply voltage.

1.6.2 GND Ground.

NC = Do not connect (May be used in future devices)

(1)

Timer2 Oscillator

(2)

PC0 (A8)

VCC

GND

PF0 (ADC0)

PF7 (ADC7 / TDI)

PF1 (ADC1)

PF2 (ADC2)

PF3 (ADC3)

PF4 (ADC4 / TCK)

PF5 (ADC5 / TMS)

PF6 (ADC6 / TDO)

AREF

GND

AVCC

(RXD0 / PDI) PE0

(TXD0 / PDO) PE1

(XCK0 / AIN0) PE2

(OC3A / AIN1) PE3

(OC3B / INT4) PE4

(OC3C / INT5) PE5

(T3 / INT6) PE6

(ICP3 / INT7) PE7

(SS) PB0

(SCK) PB1

(MOSI) PB2

(MISO) PB3

(OC2A) PB4

(OC0A / OC1C) PB7

(TOSC2 ) PG3

(OC1B) PB6

(TOSC1 ) PG4

(OC1A) PB5

PC1 (A9)

(T0) PD7

PC2 (A10)

PC3 (A11)

PC4 (A12)

PC5 (A13)

PC6 (A14)

PC7 (A15 / CLKO)

PA7 (AD7)

PG2 (ALE)

PA6 (AD6)

PA5 (AD5)

PA4 (AD4)

PA3 (AD3)

PA0 (AD0)

PA1 (AD1)

PA2 (AD2)

(RXCAN / T1) PD6

(TXCAN / XCK1) PD5

(ICP1) PD4

(TXD1 / INT3) PD3

(RXD1 / INT2) PD2

(SDA / INT1) PD1

(SCL / INT0) PD0

XTAL1

XTAL2

RESET

GND

VCC

PG1 (RD)

PG0 (WR)

16 33

(2)

NC(1)

(64-lead QFN top view)

INDEX CORNER

7679H–CAN–08/08

AT90CAN32/64/128

1.6.3 Port A (PA7..PA0)

Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port A output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port A also serves the functions of various special features of the AT90CAN32/64/128 as listed

on page 74.

1.6.4 Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port B output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port B also serves the functions of various special features of the AT90CAN32/64/128 as listed

on page 76.

1.6.5 Port C (PC7..PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port C output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port C also serves the functions of special features of the AT90CAN32/64/128 as listed on page

78.

1.6.6 Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port D output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port D also serves the functions of various special features of the AT90CAN32/64/128 as listed

on page 80.

1.6.7 Port E (PE7..PE0)

Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port E output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port E also serves the functions of various special features of the AT90CAN32/64/128 as listed

on page 83.

1.6.8 Port F (PF7..PF0)

Port F serves as the analog inputs to the A/D Converter.

87679H–CAN–08/08

AT90CAN32/64/128

Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins

can provide internal pull-up resistors (selected for each bit). The Port F output buffers have sym-

metrical drive characteristics with both high sink and source capability. As inputs, Port F pins

that are externally pulled low will source current if the pull-up resistors are activated. The Port F

pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port F also serves the functions of the JTAG interface. If the JTAG interface is enabled, the pull-

up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs.

1.6.9 Port G (PG4..PG0)

Port G is a 5-bit I/O port with internal pull-up resistors (selected for each bit). The Port G output

buffers have symmetrical drive characteristics with both high sink and source capability. As

inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are

activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock

is not running.

Port G also serves the functions of various special features of the AT90CAN32/64/128 as listed

on page 88.

1.6.10 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a

reset. The minimum pulse length is given in characteristics. Shorter pulses are not guaranteed

to generate a reset. The I/O ports of the AVR are immediately reset to their initial state even if

the clock is not running. The clock is needed to reset the rest of the AT90CAN32/64/128.

1.6.11 XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

1.6.12 XTAL2 Output from the inverting Oscillator amplifier.

1.6.13 AVCC AVCC is the supply voltage pin for the A/D Converter on Port F. It should be externally con-

nected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC

through a low-pass filter.

1.6.14 AREF This is the analog reference pin for the A/D Converter.

2. About Code Examples

This documentation contains simple code examples that briefly show how to use various parts of

the device. These code examples assume that the part specific header file is included before

compilation. Be aware that not all C compiler vendors include bit definitions in the header files

and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-

tation for more details.

7679H–CAN–08/08

AT90CAN32/64/128

3. AVR CPU Core

3.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core

is to ensure correct program execution. The CPU must therefore be able to access memories,

perform calculations, control peripherals, and handle interrupts.

3.2 Architectural Overview

Figure 3-1. Block Diagram of the AVR Architecture

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with

separate memories and buses for program and data. Instructions in the program memory are

executed with a single level pipelining. While one instruction is being executed, the next instruc-

tion is pre-fetched from the program memory. This concept enables instructions to be executed

in every clock cycle. The program memory is In-System Reprogrammable Flash memory.

Flash

Program

Memory

Instruction

Decoder

Program

Counter

Control Lines

32 x 8

General

Purpose

Registrers

ALU

Status

and Control

I/O Lines

EEPROM

Data Bus 8-bit

Data

SRAM

Direct Addressing

Indirect Addressing

Interrupt

Unit

SPI

Unit

Watchdog

Timer

Analog

Comparator

I/O Module 2

I/O Module1

I/O Module n

10 7679H–CAN–08/08

AT90CAN32/64/128

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single

clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-

ical ALU operation, two operands are output from the Register File, the operation is executed,

and the result is stored back in the Register File – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data

Space addressing – enabling efficient address calculations. One of the these address pointers

can also be used as an address pointer for look up tables in Flash program memory. These

added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant and

a register. Single register operations can also be executed in the ALU. After an arithmetic opera-

tion, the Status Register is updated to reflect information about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to

directly address the whole address space. Most AVR instructions have a single 16-bit word for-

mat. Every program memory address contains a 16- or 32-bit instruction.

Program Flash memory space is divided in two sections, the Boot Program section and the

Application Program section. Both sections have dedicated Lock bits for write and read/write

protection. The SPM (Store Program Memory) instruction that writes into the Application Flash

memory section must reside in the Boot Program section.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the

Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack

size is only limited by the total SRAM size and the usage of the SRAM. All user programs must

initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack

Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed

through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional Global

Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the

Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector posi-

tion. The lower the Interrupt Vector address, the higher is the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis-

ters, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data

Space locations following those of the Register File, 0x20 - 0x5F. In addition, the

AT90CAN32/64/128 has Extended I/O space from 0x60 - 0xFF in SRAM where only the

ST/STS/STD and LD/LDS/LDD instructions can be used.

3.3 ALU – Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose

working registers. Within a single clock cycle, arithmetic operations between general purpose

registers or between a register and an immediate are executed. The ALU operations are divided

into three main categories – arithmetic, logical, and bit-functions. Some implementations of the

architecture also provide a powerful multiplier supporting both signed/unsigned multiplication

and fractional format. See the “Instruction Set Summary” section for a detailed description.

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