NXP Semiconductors S32K1 Series Instruction Manual

1 Introduction

The S32K series further extends the highly scalable portfolio of ARM®

Cortex®MCUs in the automotive industry. It builds on the legacy of the KEA

series, whilst introducing higher memory options alongside a richer peripheral

set extending capability into a variety of automotive applications.

With a 2.70–5.5 V supply and focus on automotive environment robustness,

the S32K series devices are well suited to a wide range of applications in

electrical harsh environments. These devices are optimized for cost-sensitive

applications offering low pin-count options.

The S32K series offers a broad range of memory, peripherals, and package

options. They share common peripherals and pin counts allowing developers

to migrate easily within the MCU family or among the MCU families to take

advantage of more memory or feature integration. This scalability allows

developers to standardize on the S32K series for their end product platforms,

maximizing hardware and software reuse and reducing timeto-market.

Following are the general features of the S32K series MCUs:

• 32-bit ARM Cortex-M4 core with IEEE-754 compliant FPU, executing up

to 112 MHz

• Scalable memory footprints up to 2 MB flash and up to 256 KB SRAM

• Precision mixed-signal capability with on chip analog comparators and

multiple 12-bit ADCs

• Powerful timers for a broad range of applications including motor control,

lighting control and body applications

• Serial communication interfaces such as LPUART, LPSPI, LPI2C,

FlexCAN, CAN-FD, FlexIO and so on.

• SHE specification compliant security module

• Single power supply (2.70–5.5 V) with full functional flash program/

erase/read operations

• Functional safety compliance with ISO26262, with internal watchdog,

voltage monitors, clock monitors, memory protection and ECC

• Ambient operation temperature range: –40 °C to 125°C

• Software enablement: S32 Software Development Kit (SDK), S32 Design Studio (S32DS)

2S32K family comparison

Please refer to the latest version of the Reference Manual for details.

Contents

1 Introduction..........................................1

2 S32K family comparison..................... 1

3 Power supplies.................................... 2

3.1 Bulk and decoupling

capacitors ............................... 3

4 Clock circuitry......................................3

4.1 EXTAL and XTAL pins.............3

4.2 Suggestions for the PCB

layout of oscillator circuit......... 4

5 Debug and programing interface....... 5

5.1 Debug connector pinouts........ 6

5.2 RESET system...................... 11

6 Analog comparator interface............ 11

7 Communication modules.................. 13

7.1 LIN interface for LPUART

module...................................13

7.2 CAN interface for FlexCAN

module...................................17

7.3 Inter-Integrated Circuit IIC......20

7.4 Ethernet MAC Interface......... 22

8 Quad Serial Peripheral Interface...... 23

9 Unused pins....................................... 26

10 General board layout guidelines.... 27

10.1 Traces recommendations.... 27

10.2 Grounding .......................... 27

10.3 EMI/EMC and ESD

considerations for layout....... 28

11 PCB layer stacking...........................30

12 Injection current...............................31

13 References........................................31

14 Revision history............................... 31

AN5426

Hardware Design Guidelines for S32K1xx Microcontrollers

Rev. 3 — December 2018 Application Note

3 Power supplies

The power and ground pins are described in subsequent sections.

Figure 1. Power supply pins

Table 1. Power domains and decoupling capacitors

Power

Domain

Descripti

Voltage Bulk/Bypass Capacitor for domain Decoupli

Capacito

per pin

Characte

ristics

Package

176

LQFP

144

LQFP

100

LQFP/

BGA

64 LQFP 48 LQFP/

QFN

32 LQFP/

QFN

VDDX1Supply

voltage

5 V/3.3 V 10uF 10uF 10uF 10uF 10uF 10uF 0.1uF X7R

Ceramic

VDDA1Analog

supply

voltage

10uF 10uF 10uF 0.1uF X7R

Ceramic

VREFH1ADC

reference

voltage

high

0.1uF X7R

Ceramic

VSS Ground GND VSS, VSSA and VREFL must be shorted to GND at package level.

Table continues on the next page...

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Power supplies

Hardware Design Guidelines for S32K1xx Microcontrollers , Rev. 3, December 2018

Application Note 2 / 33

Table 1. Power domains and decoupling capacitors (continued)

VSSA Analog

Ground

VREFL ADC

reference

voltage

low

1. VDD and VDDA must be shorted to a common reference on PCB. Appropriate decoupling capacitors to be used to filter

noise on the supplies

3.1 Bulk and decoupling capacitors

The bulk capacitor acts as a local power supply to the power pin, near the decoupling capacitors. Minimize the trace length

between the bulk capacitor and the decoupling capacitors.

Decoupling capacitors make the current loop between supply, MCU, and ground reference as short as possible for high frequency

transients and noise. Therefore, all decoupling capacitors should be placed as close as possible to each of their respective power

supply pin; the ground side of the decoupling capacitor should have a via to the pad which goes directly down to the ground plane.

The capacitor should not route to the power plane through a long trace.

4 Clock circuitry

The S32K1xx has the following clock sources:

• Fast internal reference clock (FIRC): 48 MHz.

• Slow internal reference clock (SIRC): 8 MHz.

• PLL: External oscillator as input source.

• External square wave input clock: up to 50 MHz.

• External oscillator clock (OSC): 4–40 MHz.

FIRC, SIRC are internal and does not have to be considered from the hardware design perspective. The external oscillator works

with a range from 4–40 MHz. It provides an output clock that can be provided to the PLL or used as clock source for some

peripherals. When using the external oscillator as input source for the PLL, the frequency range of the external oscillator should

be 8–40 MHz.

4.1 EXTAL and XTAL pins

These pins provide the interface for a crystal to control the internal clock generator circuitry. EXTAL is the input to the crystal

oscillator amplifier. XTAL is the output of the crystal oscillator amplifier. The pierce oscillator provides a robust, low-noise and low-

power external clock source. It is designed for optimal start-up margin with typical crystal oscillators. S32K1xx supports crystals

or resonators from 4 MHz to 40 MHz. The Input Capacitance of the EXTAL, XTAL pins is 7 pF.

NXP Semiconductors

Clock circuitry

Hardware Design Guidelines for S32K1xx Microcontrollers , Rev. 3, December 2018

Application Note 3 / 33

Figure 2. Reference oscillator circuit

Table 2. Components of the oscillator circuit

Symbol Description

RS Bias Resistor

RF Feedback Resistor

• When Low-gain is selected, internal RF will be selected,

and external RF is not required.

• When High-gain is selected, external RF(1M Ohm) need

to be connected for proper operation of crystal. For

external resistor, up to 5% tolerance is allowed.

X1 Quartz Crystal / Ceramic Resonator

CXTAL Stabilizing Capacitor

CEXTAL Stabilizing Capacitor

The load capacitors are dependent on the specifications of the crystal and on the board capacitance. It is recommended to have

the crystal manufacturer evaluate the crystal on the PCB.

4.2 Suggestions for the PCB layout of oscillator circuit

The crystal oscillator is an analog circuit and must be designed carefully and according to the analog-board layout rules:

• External feedback resistor [Rf] is not needed because it’s already integrated.

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Clock circuitry

Hardware Design Guidelines for S32K1xx Microcontrollers , Rev. 3, December 2018

Application Note 4 / 33

• It is recommended to send the PCB to the crystal manufacturer to determine the negative oscillation margin as well as the

optimum regarding CXTAL and CEXTAL capacitors. The data sheet includes recommendations for the tank capacitors CXTAL

and CEXTAL. These values together with the expected PCB, pin, etc. stray capacity values should be used as a starting

point.

• Signal traces between the XTAL/EXTAL pins, the crystal and the external capacitors must be as short as possible, without

using any via. This minimizes parasitic capacitance and sensitivity to crosstalk and EMI. The capacitance of the signal

traces must be considered when dimensioning the load capacitors.

• In case there is only 1-2 PCB layers, it is recommended to place a guard ring around the oscillator components and to

connect it to the a solid ground plane. A ground area should be placed under the crystal oscillator area. This ground guard

ring must be clean ground. This means that no current from and to other devices should be flowing through the guard ring.

This guard ring should be connected to VSS x of the S32K1xx with a short trace. Never connect the ground guard ring to

any other ground signal on the board. Also avoid implementing ground loops.

• The main oscillation loop current is flowing between the crystal and the load capacitors. This signal path (crystal to CEXTAL

to CXTAL to crystal) should be kept as short as possible and should have a symmetric layout. Hence, both capacitor’s

ground connections should always be as close together as possible.

• The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any

other devices.

The following figure 3, shows the recommended placement and routing for the oscillator layout.

Figure 3. Suggested crystal oscillator layout

5 Debug and programing interface

A number of commonly used debug connectors are shown here. Most of the ARM development tools uses one of these pin out’s.

When developing your ARM circuit board, it is recommended to use a standard debug signal arrangement to make connection

to debugger easier.

The SWD/SWV pins are overlaid on top of the JTAG pins as follows:

NXP Semiconductors

Debug and programing interface

Hardware Design Guidelines for S32K1xx Microcontrollers , Rev. 3, December 2018

Application Note 5 / 33

Table 3. JTAG signal description

JTAG Mode SWD Mode Signal

TCK SWCLK Clock into the core

TDI - JTAG Test Data Input

TDO SWV JTAG Test Data Output / SWV trace data output

(SWO)

TMS SWDIO JTAG Test Mode Select / SWD data in/out

GND GND -

The pull up/down resitors for the JTAG signals are included internally by the default pad configuration. See the device reference

manual and datasheet.

5.1 Debug connector pinouts

5.1.1 20-pin Cortex Debug D ETM connector

Some newer ARM microcontroller board use a 0.05” 20-pin header (Samtec FTSH-110) for both debug and trace. (The signals

greyed out are not available on the Cortex-M3 or Cortex-M4.) The 20-pin Cortex Debug D ETM connector support both JTAG and

Serial Wire debug protocols. When the Serial debug protocol is used, the TDO signal can be used for Serial Wire Viewer output

for trace capture. The connector also provides a 4-bit wide trace port for capturing of trace that require a higher trace bandwidth

(example, when ETM trace is enabled).

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Debug and programing interface

Hardware Design Guidelines for S32K1xx Microcontrollers , Rev. 3, December 2018

Application Note 6 / 33

Figure 4. 20-pin Cortex Debug D ETM connector pin layout

5.1.2 10-pin Cortex Debug connector

For device without ETM, you can use an even smaller 0.05” 10-pin connector (Samtec FTSH-105) for debug. Similar to the 20-

pin Cortex Debug D ETM connector, both JTAG and Serial-Wire debug protocols are supported in the 10-pin version.

NXP Semiconductors

Debug and programing interface

Hardware Design Guidelines for S32K1xx Microcontrollers , Rev. 3, December 2018

Application Note 7 / 33

Figure 5. 10-pin Cortex Debug connector pin layout

5.1.3 Legacy 20-pin IDC connector

A common debug connector used in ARM development boards is the 20-pin IDC connector. The 20-pin IDC connector arrange

support JTAG debug, Serial Wire debug (SWIO and SWCLK), Serial Wire Output (SWO). The nICEDETECT pin allows the target

system to detect if a debugger is connected. When no debugger is attached, this pin is pulled high. A debugger connection

connects this pin to ground. This is used in some development boards that support multiple JTAG con- figurations. The nSRST

connection is optional; debugger can reset a Cortex-M system via the System Control Block (SCB) so this connection is often

omitted from the top level of microcontroller designs.

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Debug and programing interface

Hardware Design Guidelines for S32K1xx Microcontrollers , Rev. 3, December 2018

Application Note 8 / 33

Figure 6. 20-pin IDC connector

5.1.4 38-pin Mictor connector

In some ARM system designs, Mictor connector is used when trace port is required (example, for instruction trace with ETM). It

can also be used for JTAG/SWD connection. The 20-pin IDC connector can be connected in parallel with the Mictor connector

(only one is use at a time).

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Debug and programing interface

Hardware Design Guidelines for S32K1xx Microcontrollers , Rev. 3, December 2018

Application Note 9 / 33

Figure 7. 38-pin Mictor connector

Typically a Cortex-M3 or Cortex-M4 microcontroller only has 4-bit of trace data signals, so most of the trace data pins on the Mictor

connectors are not used. The Mictor connector is used mostly in other ARM Cortex processors (CortexA8/A9, Cortex-R4) or in

some multiprocessor systems the trace system might require a wider trace port. In such cases, some of the other unused pins

on the connector will also be used. For a typical Cortex-M3 or Cortex-M4 system, the Cortex Debug D ETM connector is

recommended.

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Debug and programing interface

Hardware Design Guidelines for S32K1xx Microcontrollers , Rev. 3, December 2018

Application Note 10 / 33

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