NXP Semiconductors P89LPC952 User manual

UM10147

P89LPC952/954 User manual

Rev. 02 — 28 April 2008 User manual

Document information

Info Content

Keywords P89LPC952, P89LPC954

Abstract Technical information for the P89LPC952/954 devices.

User manual Rev. 02 — 28 April 2008 2 of 134

Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: [email protected]

NXP Semiconductors UM10147

P89LPC952/954 User manual

Revision history

Rev Date Description

02 20080428 Added LQFP48 package information

01 20070917 Initial version

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P89LPC952/954 User manual

1. Introduction

1.1 Pin configuration

Fig 1. PLCC44 pin configuration

P89LPC952FA

P89LPC954FA

P1.3/INT0/SDA P0.4/CIN1A/KBI4/AD03

P1.2/T0/SCL P0.5/CMPREF/KBI5

P1.1/RXD0 P0.6/CMP1/KBI6

P1.0/TXD0 VDD

P3.1/XTAL1 P0.7/T1/KBI7

P3.0/XTAL2/CLKOUT P2.2/MOSI

VDD P2.3/MISO

P5.7 P2.4/SS

P5.6 P2.5/SPICLK

P5.5 P4.0

P5.4 P4.1/TRIG

P5.3 P1.4/INT1

P5.2 P1.5/RST

P5.1 P1.6

P5.0 VSS

VSS P1.7/AD04

P4.7/TCLK P2.0/AD07

P4.6 P2.1/AD06

P4.5/TDI P0.0/CMP2/KBI0/AD05

P4.4 P0.1/CIN2B/KBI1/AD00

P4.3/RXD1 P0.2/CIN2A/KBI2/AD01

P4.2/TXD1 P0.3/CIN1B/KBI3/AD02

002aab307

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Fig 2. LQFP44 pin configuration

P89LPC952FBD

P89LPC954FBD

P4.1/TRIG

002aab306

P1.3/INT0/SDA

P1.2/T0/SCL

P1.1/RXD0

P1.0/TXD0

P3.1/XTAL1

P3.0/XTAL2/CLKOUT

VDD

P5.7

P5.6

P5.5

P5.4

P1.4/INT1

P1.5/RST

P1.6

VSS

P1.7/AD04

P2.0/AD07

P2.1/AD06

P0.0/CMP2/KBI0/AD05

P0.1/CIN2B/KBI1/AD00

P0.2/CIN2A/KBI2/AD01

P0.3/CIN1B/KBI3/AD02

P0.4/CIN1A/KBI4/AD03

P0.5/CMPREF/KBI5

P0.6/CMP1/KBI6

VDD

P0.7/T1/KBI7

P2.2/MOSI

P2.3/MISO

P2.4/SS

P2.5/SPICLK

P4.0

P5.3

P5.2

P5.1

P5.0

VSS

P4.7/TCLK

P4.6

P4.5/TDI

P4.4

P4.3/RXD1

P4.2/TXD1

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1.2 Pin description

Fig 3. LQFP48 pin configuration

P89LPC954FBD48

VDD

VREFN

P4.1/TRIG

002aad095

P1.3/INT0/SDA

P1.2/T0/SCL

P1.1/RXD0

P1.0/TXD0

P2.7

P3.1/XTAL1

P3.0/XTAL2/CLKOUT

VDD

P5.7

P5.6

P5.5

P5.4

P5.3

P5.2

P5.1

P5.0

VSS

P4.7/TCLK

P4.6

P4.5/TDI

P4.4

P4.3/RXD1

P4.2/TXD1

P4.0

P0.4/CIN1A/KBI4/AD03

P0.5/CMPREF/KBI5

P0.6/CMP1/KBI6

VREFP

P0.7/T1/KBI7

P2.2/MOSI

P2.3/MISO

P2.4/SS

P2.5/SPICLK

P2.6

P1.4/INT1

P1.5/RST

P1.6

VSS

P1.7/AD04

P2.0/AD07

P2.1/AD06

P0.0/CMP2/KBI0/AD05

P0.1/CIN2B/KBI1/AD00

P0.2/CIN2A/KBI2/AD01

P0.3/CIN1B/KBI3/AD02

Table 1. Pin description

Symbol Pin Type Description

LQFP48 PLCC44 LQFP44

P0.0 to P0.7 I/O Port 0: Port 0 is an 8-bit I/O port with a user-configurable

output type. During reset Port 0 latches are configured in the

input only mode with the internal pull-up disabled. The

operation of Port 0 pins as inputs and outputs depends upon

the port configuration selected. Each port pin is configured

independently. Refer to Section 5.1 “Port configurations”.

The Keypad Interrupt feature operates with Port 0 pins.

All pins have Schmitt triggered inputs.

Port 0 also provides various special functions as described

below:

P0.0/CMP2/

KBI0/AD05 40 43 37 I/O P0.0 — Port 0 bit 0.

OCMP2 — Comparator 2 output.

IKBI0 — Keyboard input 0.

IAD05 — ADC0 channel 5 analog input.

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P0.1/CIN2B/

KBI1/AD00 39 42 36 I/O P0.1 — Port 0 bit 1.

ICIN2B — Comparator 2 positive input B.

IKBI1 — Keyboard input 1.

IAD00 — ADC0 channel 0 analog input.

P0.2/CIN2A/

KBI2/AD01 38 41 35 I/O P0.2 — Port 0 bit 2.

ICIN2A — Comparator 2 positive input A.

IKBI2 — Keyboard input 2.

IAD01 — ADC0 channel 1 analog input.

P0.3/CIN1B/

KBI3/AD02 37 40 34 I/O P0.3 — Port 0 bit 3.

ICIN1B — Comparator 1 positive input B.

IKBI3 — Keyboard input 3.

IAD02 — ADC0 channel 2 analog input.

P0.4/CIN1A/

KBI4/AD03 36 39 33 I/O P0.4 — Port 0 bit 4.

ICIN1A — Comparator 1 positive input A.

IKBI4 — Keyboard input 4.

IAD03 — ADC0 channel 3 analog input.

P0.5/CMPREF/

KBI5 35 38 32 I/O P0.5 — Port 0 bit 5.

ICMPREF — Comparator reference (negative) input.

IKBI5 — Keyboard input 5.

P0.6/CMP1/

KBI6 34 37 31 I/O P0.6 — Port 0 bit 6.

OCMP1 — Comparator 1 output.

IKBI6 — Keyboard input 6.

P0.7/T1/KBI7313529I/OP0.7 — Port 0 bit 7.

I/O T1 — Timer/counter 1 external count input or overflow

output.

IKBI7 — Keyboard input 7.

P1.0 to P1.7 I/O,I

[1] Port 1: Port 1 is an 8-bit I/O port with a user-configurable

output type, except for three pins as noted below. During

reset Port 1 latches are configured in the input only mode

with the internal pull-up disabled. The operation of the

configurable Port 1 pins as inputs and outputs depends upon

the port configuration selected. Each of the configurable port

pins are programmed independently. Refer to Section 5.1

“Port configurations”. P1.2 to P1.3 are open drain when used

as outputs. P1.5 is input only.

All pins have Schmitt triggered inputs.

Port 1 also provides various special functions as described

below:

P1.0/TXD0 4 10 4 I/O P1.0 — Port 1 bit 0.

OTXD0 — Transmitter output for serial port 0.

P1.1/RXD0393I/OP1.1 — Port 1 bit 1.

IRXD0 — Receiver input for serial port 0.

Table 1. Pin description …continued

Symbol Pin Type Description

LQFP48 PLCC44 LQFP44

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P89LPC952/954 User manual

P1.2/T0/SCL282I/OP1.2 — Port 1 bit 2 (open-drain when used as output).

I/O T0 — Timer/counter 0 external count input or overflow output

(open-drain when used as output).

I/O SCL — I2C-bus serial clock input/output.

P1.3/INT0/SDA171I/OP1.3 — Port 1 bit 3 (open-drain when used as output).

IINT0 — External interrupt 0 input.

I/O SDA — I2C-bus serial data input/output.

P1.4/INT1 48 6 44 I/O P1.4 — Port 1 bit 4.

IINT1 — External interrupt 1 input.

P1.5/RST 47 5 43 I P1.5 — Port 1 bit 5 (input only).

IRST — External Reset input during power-on or maybe a

reset input/output if selected via UCFG1 and UCFG2. When

functioning as a reset input or input/output, a LOW on this

pin resets the microcontroller, causing I/O ports and

peripherals to take on their default states, and the processor

begins execution at address 0. When functioning as a reset

output or input/output an internal reset source will drive this

pin LOW. Also used during a power-on sequence to force

ISP mode. When using an oscillator frequency above

12 MHz, the reset input function of P1.5 must be

enabled. An external circuit is required to hold the

device in reset at power-up until VDD has reached its

specified level. When system power is removed VDD will

fall below the minimum specified operating voltage.

When using an oscillator frequency above 12 MHz, in

some applications, an external brownout detect circuit

may be required to hold the device in reset when VDD

falls below the minimum specified operating voltage.

P1.6 46 4 42 I/O P1.6 — Port 1 bit 6.

P1.7/AD04 43 2 40 I/O P1.7 — Port 1 bit 7.

IAD04 — ADC0 channel 4 analog input.

P2.0 to P2.5 I/O Port 2: Port 2 is an 8-bit I/O port with a user-configurable

output type. During reset Port 2 latches are configured in the

input only mode with the internal pull-up disabled. The

operation of Port 2 pins as inputs and outputs depends upon

the port configuration selected. Each port pin is configured

independently. Refer to Section 5.1 “Port configurations”.

All pins have Schmitt triggered inputs.

Port 2 also provides various special functions as described

below:

P2.0/AD07 42 1 39 I/O P2.0 — Port 2 bit 0.

IAD07 — ADC0 channel 7 analog input.

P2.1/AD06414438I/OP2.1 — Port 2 bit 1.

IAD06 — ADC0 channel 6 analog input.

Table 1. Pin description …continued

Symbol Pin Type Description

LQFP48 PLCC44 LQFP44

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P89LPC952/954 User manual

P2.2/MOSI303428I/OP2.2 — Port 2 bit 2.

I/O MOSI — SPI master out slave in. When configured as

master, this pin is output; when configured as slave, this pin

is input.

P2.3/MISO293327I/OP2.3 — Port 2 bit 3.

I/O MISO — When configured as master, this pin is input, when

configured as slave, this pin is output.

P2.4/SS 28 32 26 I/O P2.4 — Port 2 bit 4.

I/O SS — SPI Slave select.

P2.5/SPICLK273125I/OP2.5 — Port 2 bit 5.

I/O SPICLK — SPI clock. When configured as master, this pin is

output; when configured as slave, this pin is input.

P2.6 26 - - I/O P2.6 — Port 2 bit 6.

P2.7 5 - - I/O P2.7 — Port 2 bit 7.

P3.0 to P3.1 I/O Port 3: Port 3 is a 2-bit I/O port with a user-configurable

output type. During reset Port 3 latches are configured in the

input only mode with the internal pull-up disabled. The

operation of Port 3 pins as inputs and outputs depends upon

the port configuration selected. Each port pin is configured

independently. Refer to Section 5.1 “Port configurations”.

All pins have Schmitt triggered inputs.

Port 3 also provides various special functions as described

below:

P3.0/XTAL2/

CLKOUT 7126I/OP3.0 — Port 3 bit 0.

OXTAL2 — Output from the oscillator amplifier (when a crystal

oscillator option is selected via the flash configuration.

OCLKOUT — CPU clock divided by 2 when enabled via SFR

bit (ENCLK -TRIM.6). It can be used if the CPU clock is the

internal RC oscillator, watchdog oscillator or external clock

input, except when XTAL1/XTAL2 are used to generate clock

source for the RTC/system timer.

P3.1/XTAL1 6 11 5 I/O P3.1 — Port 3 bit 1.

IXTAL1 — Input to the oscillator circuit and internal clock

generator circuits (when selected via the flash configuration).

It can be a port pin if internal RC oscillator or watchdog

oscillator is used as the CPU clock source, and if

XTAL1/XTAL2 are not used to generate the clock for the

RTC/system timer.

P4.0 to P4.7 I/O Port 4: Port 4 is an 8-bit I/O port with a user-configurable

output type. During reset Port 4 latches are configured in the

input only mode with the internal pull-up disabled. The

operation of Port 4 pins as inputs and outputs depends upon

the port configuration selected. Each port pin is configured

independently. Refer to Section 5.1 “Port configurations”.

All pins have Schmitt triggered inputs.

Port 4 also provides various special functions as described

below:

Table 1. Pin description …continued

Symbol Pin Type Description

LQFP48 PLCC44 LQFP44

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P89LPC952/954 User manual

[1] Input/output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5.

P4.0 25 30 24 I/O P4.0 — Port 4 bit 0.

P4.1/TRIG242923I/OP4.1 — Port 4 bit 1.

OTRIG — Debugger trigger output.

P4.2/TXD1232822I/OP4.2 — Port 4 bit 2.

OTXD1 — Transmitter output for serial port 1.

P4.3/RXD1222721I/OP4.3 — Port 4 bit 3.

IRXD1 — Receiver input for serial port 1.

P4.4 21 26 20 I/O P4.4 — Port 4 bit 4.

P4.5/TDI 20 25 19 I/O P4.5 — Port 4 bit 5.

I/O TDI — Serial data input/output for debugger interface.

P4.6 19 24 18 I/O P4.6 — Port 4 bit 6.

P4.7/TCLK182317I/OP4.7 — Port 4 bit 7.

ITCLK — Serial clock input for debugger interface.

P5.0 to P5.7 I/O Port 5: Port 5 is an 8-bit I/O port with a user-configurable

output type. During reset Port 5 latches are configured in the

input only mode with the internal pull-up disabled. The

operation of Port 5 pins as inputs and outputs depends upon

the port configuration selected. Each port pin is configured

independently. Refer to Section 5.1 “Port configurations”.

All pins have Schmitt triggered inputs.

Port 5 also provides various special functions as described

below:

P5.0 16 21 15 I/O P5.0 — Port 5 bit 0. High current output.

P5.1 15 20 14 I/O P5.1 — Port 5 bit 1. High current output.

P5.2 14 19 13 I/O P5.2 — Port 5 bit 2. High current output.

P5.3 13 18 12 I/O P5.3 — Port 5 bit 3. High current output.

P5.4 12 17 11 I/O P5.4 — Port 5 bit 4. High current output.

P5.5 11 16 10 I/O P5.5 — Port 5 bit 5. High current output.

P5.6 10 15 9 I/O P5.6 — Port 5 bit 6. High current output.

P5.7 9 14 8 I/O P5.7 — Port 5 bit 7. High current output.

VSS 17, 45 3, 22 16, 41 I Ground: 0 V reference.

VREFN 44 - - negative ADC reference voltage

VDD 8, 32 13, 36 7, 30 I Power supply: This is the power supply voltage for normal

operation as well as Idle and Power-down modes.

VREFP 33 - - positive ADC reference voltage

Table 1. Pin description …continued

Symbol Pin Type Description

LQFP48 PLCC44 LQFP44

User manual Rev. 02 — 28 April 2008 10 of 134

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P89LPC952/954 User manual

(1) 44-pin package.

(2) 48-pin package.

Fig 4. Block diagram

ACCELERATED 2-CLOCK 80C51 CPU

8 kB/16 kB

CODE FLASH

256-BYTE

DATA RAM

PORT 2

CONFIGURABLE I/Os

PORT 1

CONFIGURABLE I/Os

PORT 0

CONFIGURABLE I/Os

KEYPAD

INTERRUPT

PROGRAMMABLE

OSCILLATOR DIVIDER CPU

clock

CONFIGURABLE

OSCILLATOR

ON-CHIP RC

OSCILLATOR WITH

CLOCK DOUBLER

internal

bus

CRYSTAL

RESONATOR

POWER MONITOR

(POWER-ON RESET,

BROWNOUT RESET)

002aab305

UART0

ANALOG

COMPARATORS

256-BYTE

AUXILIARY RAM I2C-BUS

PORT 3

CONFIGURABLE I/Os

DEBUGGER

INTERFACE

P89LPC952/954

WATCHDOG TIMER

AND OSCILLATOR

TIMER 0

TIMER 1

REAL-TIME CLOCK/

SYSTEM TIMER

SPI

ADC0

P3[1:0]

P2[5:0](1)

P2[7:0](2)

PORT 4

CONFIGURABLE I/Os

PORT 5

CONFIGURABLE I/Os

P5[7:0]

P4[7:0]

P1[7:0]

P0[7:0]

XTAL2

XTAL1

TXD0

RXD0

UART1 TXD1

RXD1

SCL

SDA

CMP2 CIN2B

TCLK

TRIG

TDI

CIN2A CMP1

CIN1A CIN1B

AD00 AD01

AD02 AD03

AD04 AD05

AD06 AD07

SPICLK

MOSI

MISO

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