Linear Technology DC1762A-A Quick setup guide

dc1762afb

DEMO MANUAL DC1762A

Description

LTC2165, LTC2164, LTC2163

LTC2162, LTC2161, LTC2160, LTC2159, LTC2269

16-Bit, 20Msps to125Msps ADCs

Demonstration circuit 1762A supports a family of 16-Bit

20Msps to 125Msps ADCs. Each assembly features one

of the following devices: LTC

2165, LTC2164, LTC2163,

LTC2162, LTC2161, LTC2160, LTC2159, or LTC2269 high

speed, high dynamic range ADCs.

Demonstration circuit 1762A supports the LTC2165 family

DDR LVDS output mode.

The versions of the 1762A demo board supporting the

LTC2165 series of A/D converters are listed in Table 1.

L, LT, LTC, LTM, µModule, Linear Technology and the Linear logo are registered trademarks

and PScope is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners.

Depending on the required resolution and sample rate,

the DC1762A is supplied with the appropriate ADC. The

circuitry on the analog inputs is optimized for analog input

frequencies from 5MHz to 140MHz. Refer to the data sheet

for proper input networks for different input frequencies.

Design files for this circuit board are available at

http://www.linear.com/demo

Table 1. DC1762A Variants

DC1762A VARIANTS ADC PART NUMBER RESOLUTION MAXIMUM SAMPLE RATE INPUT FREQUENCY

1762A-A LTC2165 16-Bit 125Msps 5MHz to 140MHz

1762A-B LTC2164 16-Bit 105Msps 5MHz to 140MHz

1762A-C LTC2163 16-Bit 80Msps 5MHz to 140MHz

1762A-D LTC2162 16-Bit 65Msps 5MHz to 140MHz

1762A-E LTC2161 16-Bit 40Msps 5MHz to 140MHz

1762A-F LTC2160 16-Bit 25Msps 5MHz to 140MHz

1762A-G LTC2159 16-Bit 20Msps 5MHz to 140MHz

1762A-H LTC2269 16-Bit 20Msps 5MHz to 140MHz

performance summary

(TA= 25°C)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Supply Voltage – DC1762A Depending on Sampling Rate and the A/D Converter

Provided, this Supply Must Provide up to 500mA.

4.5 6 V

Analog Input Range Depending on SENSE Pin Voltage 1 2 VP-P

Logic Input Voltages Minimum Logic High

Maximum Logic Low

1.3

0.6

Logic Output Voltages (Differential) Nominal Logic Levels (100Ω Load, 3.5mA Mode)

Common Mode

Minimum Logic Levels (100Ω Load, 3.5mA Mode)

Common Mode

350

1.25

247

1.25

Sampling Frequency (Convert Clock Frequency) See Table 1

Convert Clock Level Single-Ended Encode Mode (ENC–Tied to GND)

Differential Encode Mode (ENC–Not Tied to GND)

0.2

3.6

Resolution See Table 1

Input Frequency Range See Table 1

SFDR See Applicable Data Sheet

SNR See Applicable Data Sheet

dc1762afb

DEMO MANUAL DC1762A

Quick start proceDure

Figure 1. DC1762 Setup

Demonstration circuit 1762A is easy to set up to evaluate

the performance of the LTC2165A/D converter family. Refer

to Figure 1 for proper measurement equipment setup and

follow the procedure below:

Setup

If a DC890 USB demonstration circuit was supplied with

the DC1762A demonstration circuit, follow the DC890

Quick Start Guide to install the required software and for

connecting the DC890 to the DC1762A and to a PC.

DC1762 Demonstration Circuit Board Jumpers

The DC1762A demonstration circuit board should have

the following jumper settings as default positions: (as

per Figure 1)

JP2 PAR/SER: Selects parallel or serial programming

mode. (default: serial)

JP3 Duty Cycle Stabilizer: enables/disables duty cycle

stabilizer. (default: enable)

JP4 SHDN: Enables and disables the LTC2165. (default:

enable)

JP5 NAP: Enables and disables NAP mode. (default:

enable)

JP6 LVDS/CMOS: Selects between LVDS and CMOS

output signaling. (default: LVDS)

PARALLEL DATA

OUTPUT TO DC890

NAP

LVDS/CMOS

ANALOG INPUT

PARALLEL/SERIAL

PROGRAMMING MODE

DUTY CYCLE

STABILIZER SHDN

SINGLE-ENDED

ENCODE CLOCK

FROM DC1075 dc1762a F01

4.5V TO 6V

dc1762afb

DEMO MANUAL DC1762A

Quick start proceDure

Applying Power and Signals to the DC1762A

Demonstration Circuit

If a DC890 is used to acquire data from the DC1762A,

the DC890 must FIRST be connected to a powered USB

port or provided an external 6V to 9V BEFORE applying

4.5V to 6V across the pins marked V+and GND on the

DC1762A. DC1762A requires 4.5V for proper operation.

Regulators on the board produce the voltages required for

the ADC. The DC1762A demonstration circuit requires up

to 500mA depending on the sampling rate and the A/D

converter supplied.

The DC890 data collection board is powered by the USB

cable and does require an external power supply when

collecting data from and LVDS demo board. It must be

supplied an external 6V to 9V on turrets G7(+) and G1(–)

or the adjacent 2.1mm power jack.

Analog Input Network

For optimal distortion and noise performance the RC net-

work on the analog inputs may need to be optimized for

different analog input frequencies. For input frequencies

above 140MHz, refer to the respective ADC data sheet

for a proper input network. Other input networks may be

more appropriate for input frequencies less than 5MHz,

or above 140MHz.

In almost all cases, filters will be required on both analog

input and encode clock to provide data sheet SNR. In the

case of the DC1762A, a bandpass filter used for the clock

should be used prior to the DC1075 clock divider board.

The filters should be located close to the inputs to avoid

reflections from impedance discontinuities at the driven

end of a long transmission line. Most filters do not present

50Ω outside the passband. In some cases, 3dB to 10dB

pads may be required to obtain low distortion.

If your generator cannot deliver full-scale signals without

distortion, you maybenefit from a medium power amplifier

based on a Gallium Arsenide Gain block prior to the final

filter. This is particularly true at higher frequencies where

IC based operational amplifiers may be unable to deliver

the combination of low noise figure and High IP3 point

required. A high order filter can be used prior to this final

amplifier, and a relatively lower Q filter used between the

amplifier and the demo circuit.

Apply the analog input signal of interest to the SMA

connector on the DC1762A demonstration circuit board

marked J5 AIN+. This input is capacitively coupled to a

Balun transformer ETC1-1-13 (lead free part number:

MABA007159-000000).

Encode Clock

NOTE: Apply an encode clock to the SMA connector on

the DC1762A demonstration circuit board marked J3

ENC+. As a default the DC1762A is populated to have a

single-ended input.

For the best noise performance, the encode input must

be driven with a very low jitter, square wave source. The

amplitude should be large, up to 3VP-P or 13dBm. When

using a sinusoidal signal generator a squaring circuit can

be used. Linear Technology also provides demo board

DC1075 that divides a high frequency sine wave by four,

producing a low jitter square wave for best results with

the LTC2165.

Using bandpass filters on theclock and the analoginput will

improve the noise performance by reducing the wideband

noise power of the signals. In the case of the DC1762A a

bandpass filter used for the clock should be used prior to

the DC1075. Datasheet FFT plots are taken with 10 pole LC

filters made by TTE (Los Angeles, CA) to suppress signal

generator harmonics, non-harmonically related spurs and

broadband noise. Low phase noise Agilent 8644B genera-

tors are used with TTE bandpass filters for both the clock

input and the analog input.

An internally generated conversion clockoutput is available

on J1 which could be collected via a logic analyzer, or other

data collection system if populated with a SAMTEC MEC8-

150 type connector or collected by the DC890 QuikEval-II

Data Acquisition Board using PScope™ software.

dc1762afb

DEMO MANUAL DC1762A

Software

The DC890 is controlled by the PScope System Software

provided or downloaded from the Linear Technology

website at http://www.linear.com/software/. If a DC890

was provided, follow the DC890 Quick Start Guide and

the instructions below.

To start the data collection software if PScope.exe, is in-

stalled (by default) in \Program Files\LTC\PScope\, double

click the PScope icon or bring up the run window under

the start menu and browse to the PScope directory and

select PScope.

If the DC1762Ademonstration circuit is properly connected

to the DC890, PScope should automatically detect the

DC1762A, and configure itself accordingly. If necessary

the procedure below explains how to manually configure

PScope.

Under the Configure menu, go to ADC Configuration…

Check the Config Manually box and use the following

configuration options, see Figure 2.

Manual Configuration settings:

Bits: 16

Alignment: 16

FPGA Ld: DDR LVDS

Channs: 2

Bipolar: Unchecked

Positive-Edge Clk: Unchecked

If everything is hooked up properly, powered and a suit-

able convert clock is present, clicking the Collect button

should result in time and frequency plots displayed in

the PScope window. Additional information and help for

PScope is available in the DC890 Quick Start Guide and in

the online help available within the PScope program itself.

Serial Programming

PScope has the ability to program the DC1762A board

serially through the DC890. There are several options

available in the LTC2165 family that are only available

through serially programming. PScope allows all of these

features to be tested.

These options are available by first clicking on the Set

Demo Bd Options icon on the PScope toolbar (Figure 3).

This will bring up the menu shown in Figure 4.

Figure 2: ADC Configuration

Figure 3: PScope Toolbar

Quick start proceDure

dc1762afb

DEMO MANUAL DC1762A

Figure 4: Demobd Configuration Options

Quick start proceDure

This menu allows any of the options available for the

LTC2165 family to be programmed serially. The LTC2165

family has the following options:

Power Down: Selects between normal operation, nap,

and sleep modes:

• Normal(Default):EntireADCispowered,andactive.

• Nap: ADC core powers down while references stay

active.

• Shutdown:TheentireADCispowereddown.

Clock Inversion: Selects the polarity of the CLKOUT signal:

• Normal(Default):NormalCLKOUTpolarity

• Inverted:CLKOUTpolarityisinverted

Clock Delay: Selectsthe phasedelay ofthe CLKOUTsignal:

• None(Default):NoCLKOUTdelay

• 45deg:CLKOUTdelayedby45degrees

• 90deg:CLKOUTdelayedby90degrees

• 135deg:CLKOUTdelayedby135degrees

Clock Duty Cycle: Enables or disables duty cycle stabilizer

• Stabilizeroff(Default):Dutycyclestabilizerdisabled

• Stabilizeron:Dutycyclestabilizerenabled

Output Current: Selects the LVDS output drive current

• 1.75mA(Default):LVDSoutputdrivercurrent

• 2.1mA:LVDSoutputdrivercurrent

• 2.5mA:LVDSoutputdrivercurrent

• 3.0mA:LVDSoutputdrivercurrent

• 3.5mA:LVDSoutputdrivercurrent

• 4.0mA:LVDSoutputdrivercurrent

• 4.5mA:LVDSoutputdrivercurrent

Internal Termination: Enables LVDS internal termination

• Off(Default):Disablesinternaltermination

• On:Enablesinternaltermination

Outputs: Enables digital outputs

• Enabled(Default):Enablesdigitaloutputs

• Disabled:Disablesdigitaloutputs

dc1762afb

DEMO MANUAL DC1762A

Quick start proceDure

Output Mode: Selects digital output mode

• FullRate:FullrateCMOSoutputmode(Thismodeis

not supported by the DC1762A)

• DoubleLVDS(Default):DoubledatarateLVDSoutput

mode

• DoubleCMOS:DoubledatarateCMOSoutputmode

(This mode is not supported by the DC1762A)

Test Pattern: Selects digital output test patterns

• Off(Default):ADCdatapresentedatoutput

• Allout=1:Alldigitaloutputsare1

• Allout=0:Alldigitaloutputsare0

• Checkerboard:OF,andD13-D0Alternatebetween101

0101 1010 0101 and 010 1010 0101 1010 on alternat-

ing samples.

• Alternating:Digitaloutputsalternatebetweenall1’sand

all0’sonalternatingsamples.

Alternate Bit: Alternate Bit Polarity (ABP) Mode

• Off(Default):Disablesalternatebitpolarity

• On:Enablesalternatebitpolarity(BeforeenablingABP,

be sure the part is in offset binary mode)

Randomizer: Enables Data Output Randomizer

• Off(Default):Disablesdataoutputrandomizer

• On:Enablesdataoutputrandomizer

Two’s complement:Enablestwo’scomplementmode

• Off(Default):Selectsoffsetbinarymode

• On:Selectstwo’scomplementmode

Once the desired settings are selected hit OK and PScope

will automatically update the register of the device on the

DC1762A demo board.

dc1762afb

DEMO MANUAL DC1762A

parts List

ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER

Required Circuit Components

1 1 CN1 Capacitor, Array, 0508, 2.2µF, 20%, 10V, X5R AVX W2L14D225MAT1A

2 7 C1, R28, R32, R47, R48, R53, R54 Resistor, 0402, 0Ω, Jumper Vishay CRCW04020000Z0ED

3 7 C2, C3, C6, C7, C8, C59, C60 Capacitor, 0402, 0.01µF, 10%, 16V, X7R AVX 0402YC103KAT

4 2 C9, C10 Capacitor, 0402, 8.2pF, 5%, 50V, COG AVX 04025A8R2JAT2A

5 8 C12, C13, C15, C18, C19, C21, C37, C61 Capacitor, 0402, 0.1µF, 10%, 10V, X5R TDK C1005X5R1A104K

6 2 C14, C22 Capacitor, 0603, 1µF, 10%, 16V, X7R TDK C1608X7R1C105K

7 2 C17, C23 Capacitor, 0402, 2.2µF, 20%, 6.3V, X5R Taiyo Yuden JMK105BJ225MV-T

8 1 C24 Capacitor, 0603, 4.7µF, 20%, 6.3V, X5R TDK C1608X5R0J475MT

9 11 C26-C32, C34-C36, C62 Capacitor, 0603, 0.1µF, 10%, 50V, X7R TDK C1608X7R1H104K

10 0 C33, C40, C41 Capacitor, 0603, 0.1µF, 10%, 50V, X7R Option TDK C1608X7R1H104K Option

11 2 C38, C39 Capacitor, 0402, 22pF, 5%, 16V, NPO AVX 0402YA220JAT2A

12 1 C51 Capacitor, 0402, 4.7pF, ±0.25pF, 50V, NPO AVX 04025A4R7CAT2A

13 2 C54, C55 Capacitor, 1206, 1µF, 10%, 16V, X7R AVX 1206YC105KAT2A

14 5 JP2, JP3, JP4, JP5, JP6 Header, 3-Pin, 2mm Samtec TMM-103-02-L-S

15 3 J5, J7, J9 Connector, BNC, SMA, 50Ω, Edge-Lanch E. F. Johnson, 142-0701-851

16 2 L1, L5 Inductor, 0603, 56µH, 5% Murata LQP18MN56NG02D

17 3 L2, L3, L4 Ferrite Bead, 1206 Murata BLM31PG330SN1L

18 1 RN2 Resistor, Array, 33Ω Vishay CRA04SS08333R0JTD

19 2 R1, R2 Resistor, 0402, 49.9Ω, 1%, 1/16W Vishay CRCW040249R9FKED

20 0 R4, R5 Resistor, 0402, 5.1Ω, 1%, 1/16W Option Vishay CRCW04025R10FNED Option

21 1 R6 Resistor, 0402, 10kΩ, 5%, 1/16W Vishay CRCW040210K0JNED

22 1 R7 Resistor, 0402, 180kΩ, 1%, 1/16W Vishay CRCW0402180KFKED

23 1 R8 Resistor, 0402, 330kΩ, 1%, 1/16W Vishay CRCW0402330KFKED

24 4 R9, R10, R11, R12 Resistor, 0402, 10Ω, 1%, 1/16W Vishay CRCW040210R0FKED

25 6 R14, R33, R34, R35, R37, R38 Resistor, 0402, 1kΩ, 5%, 1/16W Vishay CRCW04021K00JNTDE3

26 2 R15, R41 Resistor, 0402, 3kΩ, 1%, 1/16W Vishay CRCW04023K00FKED

27 4 R16, R27, R46, R55 Resistor, 0402, 100Ω, 5%, 1/16W Vishay CRCW0402100RJNED

28 9 R17-R23, R30, R31 Resistor, 0201, 100Ω, 5%, 1/16W Vishay CRCW0201100RFNTD

29 1 R24 Resistor, 0402, 100kΩ, 5%, 1/16W Vishay CRCW0402100KJNED

30 3 R25, R26, R29 Resistor, 0603, 4.99kΩ, 1%, 1/16W AAC CR16-4991FM

31 3 R36, R44, R45 Resistor, 0402, 86.6Ω, 1%, 1/16W Vishay CRCW040286R6FKED

32 2 R39, R40 Resistor, 0402, 33.2Ω, 1%, 1/16W Vishay CRCW040233R2FKED

33 0 R49, R50, R51, R52 Resistor, 0402, 100Ω, 5%, 1/16W Option Vishay CRCW0402100RJNED Option

34 5 TP1, TP2, TP3, TP4, TP5 Turrets Millmax 2501-2-00-80-00-00-07-0

dc1762afb

DEMO MANUAL DC1762A

parts List

ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER

35 1 T1 XFMR, 1:1 Macom MABA-007159-000000

36 1 T2 XFMR, 1:1 CT M/A-C0M MABAES0060

T2 - Alternate XFMR, 1:1 CT Coilcraft WBC1-1LB

37 1 T3 XFMR, 1:1 Macom MABA-007159-000000

38 1 U1 IC, EEPROM Microchip Tech. 24LC025-I/ST

39 1 U2 Refer to Schematic Table Linear, Technology

40 1 U3 IC, FIN1108 Fairchild FIN1108

41 2 U4, U6 IC, Adjustable 1.1A Regulators Linear, Technology LT3080EDD

42 1 U5 IC, 8-Bit I/0 Expander Philips Semi PCF8574TS/3

43 1 U8 IC, LVDS Single Port High Speed Repeater Fairchild FIN1101K8X

44 5 JP2, JP3, JP4, JP5, JP6 Shunt, 2mm Samtec 2SN-BK-G

45 4 Standoff, Snap On KEYSTONE_8831

dc1762afb

DEMO MANUAL DC1762A

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

schematic Diagram

D D

C C

B B

A A

GND

FAST DAACS BOARD ID CIRCUITRY

0201

0603 0603 0603 0603

0603 0603 0603 0603 0603 0603 0603 0603

0603 0603

NOTES: UNLESSOTHERWISE SPECIFIED,

1. ALL CAPACITORS AND RESISTORS ARE 0402.

0603 0603

0603

1206

LTC2163CUP

5 < AIN < 170

SAMPLE RATE

5 < AIN < 170

LTC2160CUP

-C

5 < AIN < 170

125Msps

80Msps

-F

LTC2162CUP

FREQUENCY RANGEASSY

-D

-A

65Msps

LTC2161CUP

LTC2165CUP

-E

5 < AIN < 170

25Msps

LTC2164CUP

40Msps

No. of BITS

-B 5 < AIN < 170105Msps

5 < AIN < 170

16 5 < AIN < 17020Msps

LTC2159CUP

-G

16 5 < AIN < 17020Msps

LTC2269CUP

-H

C6, C7 C13, C15, C21 C51

0.1uF

1.0uF

0.01uF

0.01uF 4.7puF

4.7puF

10puF

SCL

VCC_IN

SDA

VSS

VCC_IN

PAR/SER

SDO

D12/13-

OUT-ENABLE1

D12/13+

D14/15+

D14/15-

SCL

SDA

SCK

SDI

AIN-

ENC+

ENC-

SDI

PAR/SER

AIN+

SCL

SDA

SCL

VSS

SDA

OUT-ENABLE1

CLK+

CLK-

D10/11+

D10/11-

D8/09+

D8/09-

D6/07+

D6/07-

D4/05+

D4/05-

D2/03+

D2/03-

D0/01+

D0/01-

SDA

VCM1

SDI

SDO

SCKCS

+3.3V

VDD

OVDD

+3.3V

VDD

OVDD

VDD

+3.3V

VDD

+3.3V

VDD

+3.3V

VDD

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TECHNOLOGY

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



























HIGH SPEED LOW POWER





N/A LTC21XXCUP FAMILY

DEMO CIRCUIT 1762A

ADC FAMILY, LVDS





 

 









TECHNOLOGY











































HIGH SPEED LOW POWER





N/A LTC21XXCUP FAMILY

DEMO CIRCUIT 1762A

ADC FAMILY, LVDS





 

 









TECHNOLOGY











































HIGH SPEED LOW POWER





N/A LTC21XXCUP FAMILY

DEMO CIRCUIT 1762A

ADC FAMILY, LVDS

REVISION HISTORY

DESCRIPTION DATE APPROVEDECO REV

CLARENCE M.

PROTO

001

112/13/10

1.1 Part Added 06/08/12 Clarence M.

REVISION HISTORY

DESCRIPTION DATE APPROVEDECO REV

CLARENCE M.

PROTO

001

112/13/10

1.1 Part Added 06/08/12 Clarence M.

REVISION HISTORY

DESCRIPTION DATE APPROVEDECO REV

CLARENCE M.

PROTO

001

112/13/10

1.1 Part Added 06/08/12 Clarence M.

R5 5.1 1%R5 5.1 1%

C18

0.1uF

C18

0.1uF

JP4

SHDN

DIS

JP4

SHDN

DIS

C6*C6*

C59

0.01uF

C59

0.01uF

R27

100

R27

100

R22

100

R22

100

C14

1uF

C14

1uF

U6 LT3080EDDU6 LT3080EDD

VOUT 9

VCTRL

VOUT 1

REST 4

VIN

VOUT 2

VIN

8VOUT 3

R23

100

R23

100

C36

0.1uF

C36

0.1uF

U1 24LC02STU1 24LC02ST

4SDA 5

SCL 6

WP 7

VCC 8

180K 1%

FIN1101K8X

RIN-

GND

4DOUT- 5

DOUT+ 6

VCC 7

RIN+ 8

R29 4.99K 1%R29 4.99K 1%

MABAES0060

R32

0.01uF

C12

0.1uF

C12

0.1uF

R18

100

R18

100

C25

OPT

C25

OPT

R52

OPT

R52

OPT

R14

R26 4.99K 1%R26 4.99K 1%

OPT

C27 0.1uFC27 0.1uF

R21

100

R21

100

C26

0.1uF

C26

0.1uF

R51

100

R51

100

TP4TP4

MABA-007159-000000

R47

R33

MABA-007159-000000

R30

100

R30

100

C28

0.1uF

C28

0.1uF

ENC+

C39

22pF

C39

22pF

C32

0.1uF

C32

0.1uF

C20

0.1uF

C20

0.1uF

C17

2.2uF

C17

2.2uF

R16

100

R16

100

R28

P1 EDGE-CON-100P1 EDGE-CON-100

100

R50 OPTR50 OPT

JP6

LVDS/CMOS

DIS

JP6

LVDS/CMOS

DIS

C61

OPT

C61

OPT

C34

0.1uF

C34

0.1uF

R36

86.6

R36

86.6

C31

0.1uF

C31

0.1uF

C19

0.1uF

C19

0.1uF

R39

33.2

R39

33.2

R11 10 1%R11 10 1%

8.2pF

C21*C21*

C40

OPT

C40

OPT

C33

OPT

C33

OPT

C55

10uF

C55

10uF

330K 1%

R48 OPTR48 OPT

C24

4.7uF

C24

4.7uF

R4 5.1 1%R4 5.1 1%

0.01uF

OPT

FIN1108

OUT6- 32

VE1

VE2

EN12

IN1-

IN1+

IN2+

IN2-

IN3-

IN3+

IN4+

IN4-

VC1 12

IN5-

IN5+

IN6+

IN6-

IN7-

IN7+

IN8+

IN8-

EN34

VE3

VBB

VC2 25

VC3 26

EN56

OUT8- 28

OUT8+ 29

OUT7+ 30

OUT7- 31

OUT6+ 33

OUT5+ 34

VE4

OUT5- 35

VE5

OUT4- 38

OUR4+ 39

OUT3+ 40

OUT3- 41

OUT2- 42

OUT2+ 43

OUT1+ 44

OUT1- 45

EN78

VC5 48

VC4 47

R9 10 1%R9 10 1%

C37

0.1uF

C37

0.1uF

C22

1uF

C22

1uF

R55

100

R55

100

C62

0.1uF

C62

0.1uF

R12 10 1%

R37

C41

OPT

C41

OPT

TP3

GND

TP3

GND

R54 OPTR54 OPT

R31 100

49.9

BEAD

R35

C13*C13*

R40

33.2

R40

33.2

C30

0.1uF

C30

0.1uF

49.9

R44

86.6

R44

86.6

TP5

GND

TP5

GND

R57

OPT

R57

OPT

R53 0R53 0

C51*C51*

OVDD 32

VCM

AIN+

AIN-

GND

REFH

REFL

REFH

REFL

PAR/SER

GND

VDD

GND

ENC+

ENC-

SCK

SDI

GND

D0_1-

D0_1+

D2_3-

D2_3+

D4_5- 25

D4_5+ 26

D6_7- 27

D6_7+ 28

CLKOUT- 29

CLKOUT+ 30

OGND 31

D8_9- 33

D8_9+ 34

D10_11+ 36

D10_11- 35

D12_13- 37

D12_13+ 38

D14_15- 39

D14_15+ 40

OF- 41

OF+ 42

GND 43

SDO 44

VREF 45

SENSE 46

VDD 47

VDD 48

GND

C7*C7*

C15*C15*

L3 BEADL3 BEAD

AIN+

CN1

2.2uF

CN1

2.2uF

R46 OPTR46 OPT

C54

10uF

C54

10uF

R24

100K

R24

100K

L1 56nH

C38

22pF

C38

22pF

U4 LT3080EDDU4 LT3080EDD

VOUT 9

VCTRL

VOUT 1

REST 4

VIN

VOUT 2

VIN

8VOUT 3

C16

0.1uF

C16

0.1uF

RN2 33RN2 33

R15

R25 4.99K

C23 2.2uFC23 2.2uF

C60

OPT

C60

OPT R6

10K

PCF8574TS/3

P0 10

P1 11

P2 12

P3 14

SDA

P4 16

P5 17

P6 19

P7 20

GND

SCL

INT

VDD 5

8NC

NC 13

NC 18

ENC-

R20

100

R20

100

R34

R38

C10

8.2pF

C10

8.2pF

JP2

PAR

SER

PAR/SER

JP2

PAR

SER

PAR/SER

TP2

V+

3.5V - 6V

TP2

V+

3.5V - 6V

R45 86.6 1%R45 86.6 1%

R19

100

R19

100

C29

0.1uF

C29

0.1uF

JP5

NAP

DIS

JP5

NAP

DIS

TP1

EXT REF

TP1

EXT REF

R17

100

R17

100

R49

OPT

R49

OPT

BEAD

R10 10 1%R10 10 1%

C35

0.1uF

C35

0.1uF

JP3

DUTY CYCLE STAB.

DIS

JP3

DUTY CYCLE STAB.

DIS

R56

OPT

R56

OPT

R41

dc1762afb

DEMO MANUAL DC1762A

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ●FAX: (408) 434-0507 ●www.linear.com

 LINEAR TECHNOLOGY CORPORATION 2011

LT 0912 REV B • PRINTED IN USA

DEMONSTRATION BOARD IMPORTANT NOTICE

Linear Technology Corporation (LTC) provides the enclosed product(s) under the following AS IS conditions:

This demonstration board (DEMO BOARD) kit being sold or provided by Linear Technology is intended for use for ENGINEERING DEVELOPMENT

OR EVALUATION PURPOSES ONLY and is not provided by LTC for commercial use. As such, the DEMO BOARD herein may not be complete

in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety

measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union

directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations.

If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 30 days from the date

of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU

OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS

FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR

ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.

The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user releases LTC from all claims

arisingfromthehandlingoruseofthegoods.Duetotheopenconstructionoftheproduct,itistheuser’sresponsibilitytotakeanyandall

appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or

agency certified (FCC, UL, CE, etc.).

No License is granted under any patent right or other intellectual property whatsoever. LTC assumes no liability for applications assistance,

customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.

LTC currently services a variety of customers for products around the world, and therefore this transaction is not exclusive.

Please read the DEMO BOARD manual prior to handling the product. Persons handling this product must have electronics training and

observe good laboratory practice standards. Common sense is encouraged.

This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a LTC applica-

tion engineer.

Mailing Address:

Linear Technology

1630 McCarthy Blvd.

Milpitas, CA 95035

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