Alinx AXU2CGB-E User manual

ZYNQ UltraScale+ MPSoC

FPGA Development Board

AXU2CGB-E

User Manual

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Version Record

Version

Date

Release By

Description

Rev 1.0

2022-09-08

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Table of Contents

Version Record .............................................................................................2

Part 1: FPGA Development Board Introduction .......................................... 6

Part 2: ACU2CG core board ...................................................................... 10

Part 2.1: ACU2CG core board Introduction ....................................... 10

Part 2.2: ZYNQ Chip ...........................................................................11

Part 2.3: DDR4 DRAM ........................................................................13

Part 2.4: QSPI Flash ...........................................................................18

Part 2.5: eMMC Flash .........................................................................19

Part 2.6: Clock configuration .............................................................. 21

Part 2.7: LED ...................................................................................... 23

Part 2.8: Power Supply .......................................................................24

Part 2.9: ACU2CG Core Board Form Factor ..................................... 25

Part 2.10: Board to Board Connectors pin assignment .....................25

Part 3: Carrier Board ..................................................................................35

Part 3.1: Carrier Board Introduction ................................................... 35

Part 3.2: M.2 Interface ........................................................................36

Part 3.3: DP Interface ......................................................................... 37

Part 3.4: USB3.0 interface ..................................................................39

Part 3.5: Gigabit Ethernet Interface ................................................... 40

Part 3.6: USB to Serial Port ................................................................42

Part 3.7: SD Card Slot Interface .........................................................43

Part 3.8: Expansion Header ............................................................... 44

Part 3.9: CAN communication interface .............................................46

Part 3.10: 485 communication interface ............................................ 47

Part 3.11: MIPI camera interface ........................................................48

Part 3.12: JTAG Debug Port ...............................................................49

Part 3.13: Real-time clock .................................................................. 50

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Part 3.14: EEPROM and Temperature sensor ...................................51

Part 3.15: User LEDs ..........................................................................52

Part 3.16: Keys ................................................................................... 53

Part 3.17: DIP Switch Configuration ...................................................54

Part 3.18: Power Supply .....................................................................55

Part 3.19: ALINX Customized Fan ..................................................... 56

Part 3.20: Carrier Board Size Dimension ...........................................57

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This MPSoCs FPGA development platform adopts the core board + carrier

board mode, which is convenient for users to use the core board for secondary

development. The core board uses XILINX Zynq UltraScale+ CEG chip ZU2CG

solution, uses Processing System(PS)+Programmable Logic(PL) technology to

integrate dual-core ARM ARM Cortex-A53 and FPGA programmable logic on a

single chip. In addition, the PS side of the core board has 4 pieces of 1GB

high-speed DDR4 SDRAM chips, 1 piece of 8GB eMMC memory chip and 1

piece of 256Mb QSPI FLASH chip.

In the design of carrier board, we have extended a wealth of interfaces for

users, such as 1 SATA M.2 interface, 1 DP interface, 4 USB 3.0 Interface, 2

Gigabit Ethernet interfaces, 1 SD card slot,2-Channel 40-pin expansion header,

2-Channel CAN bus interfaces, 2-Channel RS485 bus interfaces, 1 MIPI

Camera Interface. It meets users' requirements for high-speed data exchange,

data storage, Video transmission processing, deep learning, artificial

intelligence and industrial control. It is a "professional" ZYNQ development

platform. For high-speed data transmission and exchange, pre-verification and

post-application of data processing is possible. This product is very suitable for

students, engineers and other groups engaged in MPSoCs development.

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Part 1: FPGA Development Board Introduction

The entire structure of the AXU2CGB-E FPGA development board is

inherited from our consistent core board + carrier board model. A high-speed

inter-board connector is used between the core board and the carrier board.

The core board is mainly composed of the smallest system of XCZU2CG

+ 4 DDR4 + eMMC + QSPI FLASH, ACU2CG uses Xilinx's Zynq UltraScale+

MPSoCs CG chip, the model number is XCZU2CG-1SFVC784E. XCZU2CG

chip can be divided into processor system part Processor System (PS) and

programmable logic part Programmable Logic (PL). On the PS side of the

ZU2CG chip, there are 4 DDR4, each with a capacity of up to 512MB. The 8GB

eMMC FLASH memory chip and a 256Mb QSPI FLASH which are on the PS

side, used to statically store the operating system, file system and user data of

MPSoCs.

The AXU2CGB-E carrier board expands its rich peripheral interface,

including 1 SATA M.2 interface, 1 DP interface, 4 USB 3.0 Interface, 2 Gigabit

Ethernet interfaces, 1 SD card slot,2-Channel 40-pin expansion header,

2-Channel CAN bus interfaces, 2-Channel RS485 bus interfaces, 1 MIPI

Camera Interface and some keys and LEDs.

The following figure shows the structure of the entire development system:

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Figure 1-1-1: The Schematic Diagram of the AXU2CGB-E

Through this diagram, you can see the interfaces and functions that the

AXU2CGB-E FPGA Development Board contains:

ACU2CG core board

It consists of ACU2CG +4GB DDR4（PS）+8GB eMMC FLASH + 256Mb

QSPI FLASH, and there are 2 crystal oscillators to provide the clock, a

single-ended 33.3333MHz crystal oscillator for the PS system, and a

differential 200MHz crystal oscillator for the PL logic DDR reference

clock.

M.2 Interface1 PCIEx1 standard M.2 interface, used to connect M.2

SSD solid state drives, with a communication speed of up to 6Gbps.

DP Output Interface

1 standard Display Port output display interface, used for video image

display. Supports up to 4K@30Hz or 1080P@60Hz output

USB 3.0 Interface

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4-channel USB3.0 HOST interface, USB interface type is TYPE A. Used

to connect external USB peripherals, such as connecting a mouse,

keyboard, U disk, etc.

Gigabit Ethernet Interface

2-Channel 10/100M/1000M Ethernet RJ45 interface for Ethernet data

exchange with computers or other network devices. The network

interface chip uses JLSemi JL2121-N040I industrial grade GPHY chip.

USB Uart Interface

Two Uart to USB ports, one for PS and one for PL. It is used to

communicate with the computer, which is convenient for users to debug.

The serial port chip adopts Silicon Labs CP2102GM's USB-UAR chip,

and the USB interface adopts MINI USB interface.

SD Card Slot Interface

1 Micro SD card holder, used to store operating system image and file

system.

40-pin expansion port

2 40-pin 0.1-inch pitch expansion port can be connected to various

ALINX modules (binocular camera, TFT LCD screen, high-speed AD

module, etc.). The expansion port contains 1-channel 5V power supply,

2-channel 3.3V power supply, 3-channel way ground, 34 IOs port.

CAN Communication Interface

Two-way CAN bus interface, using TI's SN65HVD232 chip, the

interface uses 4Pin green terminal blocks.

485 Communication Interface

Two-way 485 communication interface, using MAX3485 chip of MAXIM

company. The interface uses 6Pin green terminal blocks.

MIPI Interface

MIPI camera input interfaces, used to connect MIPI camera module

(AN5641).

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JTAG debug port

A 10-pin 0.1 spacing standard JTAG ports for FPGA program download

and debugging. Users can debug and download the ZU2CG system

through the XILINX downloader.

Temperature and humidity sensor chip LM75

On-board temperature and humidity sensor chip LM75, used to detect

the temperature and humidity of the surrounding environment around

the FPGA development board

EEPROM

One EEPROM 24LC04 with IIC interface

Real Time Clock (RTC)

1 built-in RTC real-time clock

LED Lights

5 LEDs, include 2 LEDs on the core board, 3 LED on the carrier board.

There are 1 power indicator and 1 DONE Configuration indicator on the

core board, 1 power indicator on the carrier board. There are 1 power

indicator and 2 user indicators on the carrier board.

KEYs

3 KEYs, include 1 Rest KEY and 2 User KEYs.

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Part 2: ACU2CG core board

Part 2.1: ACU2CG core board Introduction

ACU2CG (core board model, the same below) FPGA core board, ZYNQ

chip is based on XCZU2CG-1SFVC784E of XILINX company Zynq UltraScale+

MPSoCs CG series.

This core board uses 4 Micron DDR4 chips MT40A512M16GE on the PS

side, to form a 64-bit data bus bandwidth and 2GB capacity. The highest

operating speed of DDR4 SDRAM on the PS side can reach 1200MHz (data

rate 2400Mbps). In addition, a 256MBit QSPI FLASH and an 8GB eMMC

FLASH chip are also integrated on the core board to start storage configuration

and system files.

In order to connect with the carrier board, the four board-to-board

connectors of this core board expand the PS side USB2.0 interface, Gigabit

Ethernet interface, SD card interface and other remaining MIO ports; also

expand 4 pairs of PS MGT high-speed transceiver interface; and almost all IO

ports on the PL side (HP I/O: 96, HD I/O: 84). The wiring between the

XCZU2CG chip and the interface has been processed with equal length and

differential, and the core board size is only 3.15*2.36 (inch), which is very

suitable for secondary development.

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