SBS CM4 User manual

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Preliminary

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CM4 User’s Guide—SBS Technologies ii

Preliminary

CM4 User's Manual - Rev. F

This document and its contents are provided as is, with no warranties of any kind, whether express or implied, includ-

ing warranties of design, merchantability, and fitness for a particular purpose, or arising from any course of dealing,

usage, or trade practice.

The content of this manual is furnished for informational use only and is subject to change without notice. Reverse

engineering of any SBS product is strictly prohibited.

In no event will SBS be liable for any lost revenue or profits or other special, indirect, incidental and consequential

damage, even if SBS has been advised of the possibility of such damages, as a result of the usage of this document

and the product that this document describes.

SBS shall have no liability with respect to the infringement of copyrights, trade secrets, or any patents by this docu-

ment or any part thereof.

SBS and the SBS logo are trademarks of SBS Technologies.

Intel is a trademark of Intel Corporation.

IBM and PowerPC are trademarks of International Business Machines (IBM).

CompactPCI is a trademark of the PCI Industrial Computer Manufacturers Group.

VxWorks is a trademark of WindRiver Systems, Inc.

SBS Technologies

7401 Snaproll

Albuquerque, NM 87109-4358

Tel 505.875.0600 Fax 505.478.1400

Email [email protected]

Document #:70000340-800 Rev. E and 70000345-800 Rev. E

Conventions

The following conventions are used in this user’s guide:

• Signal names are designated with all capital letters (e.g. SYSEN#)

• Signal names followed by the pound sign (#) are active-low (e.g. SYSEN#)

• Data addresses written in hexadecimal are designated with the prefix 0x (e.g. 0xF000_0000)

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CM4 User’s Guide—SBS Technologies iii

Preliminary

Table of Contents

Chapter 1: Introduction

1.1 Overview ...............................................................................................................1-1

1.2 Specification .........................................................................................................1-3

1.3 Block Diagram ......................................................................................................1-4

1.4 Technical Support .................................................................................................1-5

1.5 Related Documents ...............................................................................................1-5

Chapter 2: Getting Started

2.1 What is included ...................................................................................................2-1

2.2 Equipment Needed ................................................................................................2-1

2.3 Power ....................................................................................................................2-2

2.4 Installation ............................................................................................................2-3

Chapter 3: Board Description

3.1 Physical Description .............................................................................................3-1

3.2 Power ....................................................................................................................3-1

3.3 Connector Locations .............................................................................................3-2

3.4 Front Panel ............................................................................................................3-2

3.5.1 CompactPCI Connectors ...........................................................................3-3

3.5.2 PMC Connectors ........................................................................................3-5

3.5.3 JTAG/COP Port (P1100) ...........................................................................3-7

3.6 Memory/X-bus ......................................................................................................3-8

3.7 Memory Map ......................................................................................................3-10

3.7.1 I/O Devices ..............................................................................................3-11

3.8 PCI Arbitration ...................................................................................................3-11

3.9 PCI IDSEL ..........................................................................................................3-12

3.10 Serial I/O Communications ................................................................................ 3-12

3.11 Digital I/O Communications ............................................................................... 3-14

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iv CM4 User’s Guide—SBS Technologies

Preliminary

3.12 Ethernet I/O Communications ............................................................................3-16

3.13 System Controller vs. Peripheral Operation .......................................................3-16

3.14 Reset Circuitry ....................................................................................................3-17

3.14.1 Hard Resets ..............................................................................................3-17

3.14.2 Soft Resets ...............................................................................................3-20

3.14.3 PCI Resets ................................................................................................3-20

3.14.4 Watchdog Timer ......................................................................................3-21

3.15 Interrupt Circuitry ...............................................................................................3-22

3.15.1 PCI Interrupts ...........................................................................................3-22

3.15.2 On-board Interrupts ..................................................................................3-25

3.16 Clock Circuitry ...................................................................................................3-26

3.16.1 24MHz and 14.318MHz Clocks ..............................................................3-26

3.16.2 Real-Time Clock ......................................................................................3-26

3.16.3 Tsi107 Clock Distribution .......................................................................3-27

3.16.4 PCI 6254 PCI Bridge Clock Operation—Transparent Mode ..................3-29

3.16.5 PCI 6254 PCI Bridge Clock Operation—Non-Transparent Mode ..........3-29

Chapter 4: Components

4.1 Component Location .............................................................................................4-1

4.2 Processors .............................................................................................................4-2

4.3 Tsi107 Host Bridge ...............................................................................................4-3

4.3.1 System Bus Interface .................................................................................4-3

4.3.2 Memory Controller and Bus Interface .......................................................4-3

4.3.3 PCI Bus Interface .......................................................................................4-3

4.3.4 Interrupt Controller ....................................................................................4-3

4.4 PCI 6254 PCI Bridge ............................................................................................4-4

4.5 SDRAM ................................................................................................................4-4

4.6 Flash Memory .......................................................................................................4-4

4.6.1 Boot Flash ..................................................................................................4-4

4.6.2 Extended Flash ...........................................................................................4-4

4.7 Decoder CPLD ......................................................................................................4-5

4.8 82559ER Ethernet Controller ...............................................................................4-5

4.9 ST16C2550 Dual Channel UARTs .......................................................................4-5

4.10 STK14C88 NVSRAM ..........................................................................................4-6

4.11 DS1685 Real-Time Clock .....................................................................................4-6

Chapter 5: CPLD Registers

5.1 Watchdog Control Register ..................................................................................5-1

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CM4 User’s Guide—SBS Technologies v

Preliminary

5.2 MCP Ticker Control Register ...............................................................................5-2

5.3 MCP Ticker Reset Register ..................................................................................5-2

5.4 Interrupt Status Register .......................................................................................5-3

5.5 Interrupt Mask Register ........................................................................................5-4

5.6 Status Input Port Register .....................................................................................5-5

5.7 Status Output Port Register ...................................................................................5-6

5.8 CPLD Version Register ........................................................................................5-6

5.9 Digital I/O Registers .............................................................................................5-7

5.9.1 DOUT Register ..........................................................................................5-7

5.9.2 DOUTEN Register .....................................................................................5-8

5.9.3 DINQ Register ...........................................................................................5-8

5.10 DI/O Interrupt Status Register ..............................................................................5-9

5.11 DI/O Interrupt Mask Register .............................................................................5-10

Chapter 6: Customer Service

6.1 Introduction ...........................................................................................................6-1

6.2 Updated User Guides and Data Sheets .................................................................6-1

6.3 Customer Service ..................................................................................................6-2

6.4 Warranty Information ...........................................................................................6-2

6.4.1 Warranty ....................................................................................................6-2

6.4.2 Non-Warranty Terms and Conditions ........................................................6-3

6.5 Return Material Authorization (RMA) .................................................................6-3

6.6 Documentation Feedback Form ............................................................................6-5

Index

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CM4 User’s Guide—SBS Technologies vii

Preliminary

List of Figures

Figure 1-1 Convection-cooled configuration.............................................................................1-2

Figure 1-2 Conduction-cooled configuration ............................................................................1-2

Figure 1-3 CM4 Block diagram.................................................................................................1-4

Figure 2-1 Power regulation recommendations.........................................................................2-2

Figure 3-1 Connector locations (convection-cooling version)..................................................3-2

Figure 3-2 Front panel (convection-cooled configuration)........................................................3-2

Figure 3-3 JTAG/COP port (P1100)..........................................................................................3-7

Figure 3-4 Memory/X-bus network...........................................................................................3-9

Figure 3-5 Serial port circuitry ................................................................................................3-13

Figure 3-6 Digital I/O circuit (digital port 0)...........................................................................3-15

Figure 3-7 Ethernet circuitry....................................................................................................3-16

Figure 3-8 PCI 6254 PCI Bridge in transparent and non-transparent mode............................3-17

Figure 3-9 Power-up reset circuitry.........................................................................................3-18

Figure 3-10 Reset circuitry........................................................................................................3-19

Figure 3-11 PCI reset when CM4 is a system controller...........................................................3-21

Figure 3-12 PCI reset when CM4 is a peripheral card ..............................................................3-21

Figure 3-13 Interrupt circuitry...................................................................................................3-23

Figure 3-14 Decoder CPLD PCI interrupt circuitry ..................................................................3-24

Figure 3-15 Decoder CPLD interrupt circuitry..........................................................................3-25

Figure 3-16 CPU interrupt circuitry...........................................................................................3-26

Figure 3-17 Primary clock circuitry...........................................................................................3-27

Figure 3-18 PCI clock circuitry.................................................................................................3-28

Figure 3-19 cPCI clock circuitry ...............................................................................................3-30

Figure 4-1 CM4 components (front view).................................................................................4-1

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CM4 User’s Guide—SBS Technologies viii

Preliminary

Figure 4-2 CM4 components (back side)...................................................................................4-2

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CM4 User’s Guide—SBS Technologies ix

Preliminary

List of Tables

Table 3-1 Processor voltages.................................................................................................... 3-1

Table 3-2 CompactPCI connector P7201 pin assignments ...................................................... 3-3

Table 3-3 CompactPCI connector P7202 pin assignments ...................................................... 3-4

Table 3-4 PMC connectors P7101 and P7102 pin assignments............................................... 3-5

Table 3-5 PMC-P7103 pin assignments................................................................................... 3-6

Table 3-6 JTAG/COP port pin assignments............................................................................. 3-7

Table 3-7 Tsi107 memory map—processor view .................................................................. 3-10

Table 3-8 Tsi107 memory map—PCI bus master view......................................................... 3-11

Table 3-9 X-bus I/O address map........................................................................................... 3-11

Table 3-10 PCI bus arbitration ................................................................................................. 3-11

Table 3-11 PCI IDSEL configuration registers........................................................................ 3-12

Table 3-12 Serial port addresses............................................................................................... 3-12

Table 3-13 Rotated PMC interrupt connections....................................................................... 3-22

Table 3-14 Processor system clocks......................................................................................... 3-27

Table 4-1 Processor parameters................................................................................................ 4-2

Table 4-2 Real-Time Clock time, calendar and alarm data modes .......................................... 4-7

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CM4 User’s Guide—SBS Technologies 1-1

Preliminary

Chapter 1: Introduction

1.1 Overview

The CM4 is a 3U CompactPCI Single Board Computer (SBC) designed for network switching,

routing, and front-end processing applications. It is available with multiple processor options and

offers the flexibility of functioning as a system controller or peripheral card. The CM4 is available

in configurations for convection-cooled or conduction-cooled environments.

The CM4 offers two PowerPC Reduced Instruction Set Computer (RISC) processor options:

• MPC755—400MHz

• MPC7410—500MHz

Each processor includes 32KB L1 instruction and 32KB L1data caches. The MPC755 comes with

1MB of backside L2 cache; the MPC7410 processor comes with 2MB of backside L2 cache.

The CM4 implements the Tsi107 Host Bridge (replacing the MPC107 PCI Bridge chip) that

includes a 64-bit 100MHz system bus interface, a memory controller with a 64-bit 100MHz mem-

ory interface, and a 32-bit 33MHz PCI interface. The memory interface accesses up to four 16M x

16 SDRAM chips for a total on-board system memory of 128MB to 512MB. Error Checking and

Correction (ECC) is also included. It also accesses four 64Mb StrataFlash devices for a total

on-board flash memory of 64MB. The memory bus also connects with the X-bus to access the

8MB StrataFlash boot flash, 32KB NVSRAM, Real Time Clock, and Decoder CPLD.

The Tsi107 Host Bridge also provides a 32-bit PCI bus interface that connects with the

10/100Mbps 82559ER Ethernet Controller, PCI 6254 PCI Bridge, and a single PMC site.

The 82559ER Ethernet Controller with integrated Medial Access Control (MAC) and physical

layer (PHY) provides a 10Base-T and 100Base-TX network communications interface through

the cPCI P7202 (P2) connector to the backplane or an optional CM4 Transition Module (TM),

which provides either a RJ-45 connector mounted on a rear panel or a surface-mounted connector.

The CM4 includes two ST16C2550 Dual Channel UART Transceivers that provide two RS-232

serial ports and two RS-422/485 serial ports. All four channels operate in full-duplex mode and

include 16 bytes of FIFO transmit and 16 bytes of FIFO receive memory.

In addition to serial and Ethernet I/O, the CM4 offers four programmable digital I/O channels that

can be used for manufacturing process control lines.

The PCI 6254 PCI Bridge connects the PCI bus (bus 0) to the cPCI backplane (bus1). Because the

CM4 can function as a system controller or a peripheral card, the PCI 6254 PCI Bridge (formerly

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