ON Semiconductor NCN51205GEVB User manual
©Semiconductor Components Industries, LLC, 2013
May, 2013 −Rev. 0
1Publication Order Number:
EVBUM2186/D
NCN51205GEVB
KNX Evaluation Board
User'sManual
Introduction
The NCN5120 Development Board is the ideal solution
for developing your KNX application with the
ON Semiconductor KNX transceiver NCN5120. The
development board contains the NCN5120 KNX
Transceiver which handles the transmission and reception of
data on the bus. It will also generate all necessary voltages
to power the board and external loads.
It also contains a microcontroller with debug interface for
custom firmware development. Up to 8 external switches
can be monitored and up to 4 external loads can be
controlled. A voltage between 3.3 V and 21 V is available to
drive the external loads.
The NCN5120 Development Board assures safe coupling
to and decoupling from the KNX bus. Bus monitoring warns
the external microcontroller for loss of power so that critical
data can be stored in time.
Figure 1. NCN5120 Development Board
Key Features
•9,600 baud KNX Communication Speed
•Supervision of KNX Bus Voltage
•High Efficient 3.3 V to 21 V Selectable DC−DC
Converter to Drive External Loads
•Monitoring of Power Regulators
•No Additional Power Supply Required
•Buffering of Sent Data Frames
(Extended Frames Supported)
•Selectable UART or SPI Interface to Host Controller
•Selectable UART and SPI Baud Rate to Host Controller
•Optional CRC on UART to the Host
•Optional MARKER Character to the Host
•Optional Direct Coupling of RxD and TxD to Host
(Analog Mode)
•Auto Polling (Optional)
•Temperature Monitoring
•Contains Freely Programmable Microcontroller for
Custom Applications
•Monitoring of 8 External Switches
•Controlling of 4 External (High Voltage) Loads
(e.g. LED’s)
•One Freely Usable Push Button
•3 Freely Usable LED’s
•Operating Temperature Range −25°C to +85°C
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EVAL BOARD USER’S MANUAL
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BLOCK DIAGRAM
Figure 2. NCN5120 Development Board Block Diagram
Connector J4
MSP430
3.3 V
Adj.
Reg.
NCN5120
J1
Reverse Protection
Diode + TVS
Clock
RESETb, SAVEb
Interface
UART or SPI
Connector J3
ESD Protection
Low Side
Drive
3 LED +
Switch
LED1,2,3, SW1
CONNECTOR DESCRIPTION
Table 1. CONNECTOR LIST AND DESCRIPTION
Connector Description
J1 KNX Bus Connection
J2 Power Supply and UART Connection
J3 External Switch Inputs and External Outputs
J4 Microcontroller Debug Interface
TYPICAL APPLICATION
Figure 3. Typical Application
4 Push Buttons
(with each one blue LED)
KNX Bus
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ELECTRICAL SPECIFICATION
Recommend Operation Conditions
Operating ranges define the limits for functional
operation and parametric characteristics of the development
board. Note that the functionality of the development board
outside these operating ranges is not guaranteed. Operating
outside the recommended operating ranges for extended
periods of time may affect device reliability.
Table 2. OPERATING RANGES
Symbol Parameter Min Max Unit
VBUS Voltage on Positive Pin of J1 (Note 1) +20 +33 V
VDIG1 Input Voltage on J4 and J3 (Pins 9, 11, 13 and 15) and J2 (Pin 8) 0 3.3 V
VDIG2 Input Voltage on J3 (Pins 1, 3, 5 and 7) (Note 2) 0 5 V
VDD1 Output Voltage on J2 (Pin 1) 0 3.3 V
VDD2 Output Voltage on J3 (Pins 2, 4, 6 and 8) and J2 (Pins 3 and 7)
(Note 3)
3.3 21 V
V20V Output Voltage on J2 (Pin 5) 0 22 V
TaAmbient Temperature −25 +85 °C
1. Voltage indicates DC value. With equalization pulse bus voltage must be between 11 V and 45 V
2. Higher voltages are possible. See Adjustable DC−DC Converter page 15 for more details. Only valid if R12, R17, R22 and R25 are not
mounted.
3. See Adjustable DC−DC Converter page 15 for the limitations!
Table 3. DC PARAMETERS
(The DC parameters are given for a development board operating within the Recommended Operating Conditions unless otherwise
specified.)
Convention: currents flowing in the circuit are defined as positive.
Symbol
Con-
nector Pin(s) Parameter
Remark/Test
Conditions Min Typ Max Unit
Power Supply
VBUS J1 1 Bus DC Voltage Excluding Active and
Equalization Pulse
20 33 V
IBUS Bus Current Consumption Normal Operating Mode,
No External Load, DC1
and DC2 Enabled,
Continuous Transmission
of ‘0’ on the KNX Bus by
another KNX Device
5 mA
VBUSH Undervoltage Release Level VBUS Rising
(Figure NO TAG)
18.0 V
VBUSL Undervoltage Trigger Level VBUS Falling
(Figure NO TAG)
16.8 V
VBUS_Hyst Undervoltage Hysteresis 0.6 V
KNX Bus Coupler
Icoupler_lim J1 1 Bus Coupler Current
Limitation
J5 open 13 30 mA
J5 shorted 26 60 mA
Fixed DC−DC Converter
VDD1 J2 1 Output Voltage 3.13 3.3 3.47 V
VDD1_rip Output Voltage Ripple VBUS =26V,I
DD1 =40mA 40 mV
IDD1_lim Overcurrent Threshold −100 −200 mA
ηVDD1 Power Efficiency Vin =26V,I
DD1 =35mA 90 %
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Table 3. DC PARAMETERS (continued)
(The DC parameters are given for a development board operating within the Recommended Operating Conditions unless otherwise
specified.)
Convention: currents flowing in the circuit are defined as positive.
Symbol UnitMaxTypMin
Remark/Test
Conditions
ParameterPin(s)
Con-
nector
Adjustable DC−DC Converter
VDD2 J2, J3 3 (J2),
2, 4, 6
and
8 (J3)
Output Voltage VBUS >V
DD2 3.3 21 V
VDD2H Undervoltage Release Level VDD2 Rising
(Figure NO TAG)
0.9 ×VDD2 V
VDD2L Undervoltage Trigger Level VDD2 Faling
(Figure NO TAG)
0.8 ×VDD2 V
VDD2_rip Output Voltage Ripple VBUS =26V,V
DD2 = 3.3 V,
IDD2 =40mA
40 mV
IDD2_lim Overcurrent Threshold −100 −200 mA
ηVDD2 Power Efficiency Vin =26V,V
DD2 = 3.3 V,
IDD2 =35mA
90 %
20 V Regulator
V20V J2 5 20 V Output Voltage I20V < 4 mA, VBUS > 25 V 18 20 22 V
I20V_Lim 20 V Output Current
Limitation
−4−11 mA
V20VH 20 V Undervoltage Release
Level
20 V Rising 12.6 13.4 14.2 V
V20VL 20 V Undervoltage Trigger
Level
20 V Falling 11.8 12.6 13.4 V
V20V_hys Overcurrent Threshold V20V_hyst = V20VH −V20VL 0.8 V
Digital Inputs
VIL J2 7 Logic Low Threshold Pin 1, 3, 5 and 7 (J3) only
valid if R12, R17, R22
and/or R25 are mounted
and Q1, Q2, Q3 and/or Q4
are not mounted.
0 0.7 V
J3 1, 3,
5, 7, 9, 11,
13, 15
J4 2, 3, 4, 5,
6, 8
VIH J2 7 Logic High Threshold 2.65 3.3 V
J3 1, 3,
5, 7, 9, 11,
13, 15
J4 2, 3, 4, 5,
6, 8
Digital Outputs
VOL J2 7 Logic Low Output Level 0−0.6 V
VOH Logic High Output Level VDD1 −0.6 −VDD1 V
VOL_OD J3 1, 3, 5, 7 Logic Low Level Open Drain IOL =5mA − − 0.4 V
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Table 4. AC PARAMETERS
(The AC parameters are given for a development board operating within the Recommended Operating Conditions unless otherwise
specified.)
Symbol Pin(s) Parameter Remark/Test Conditions Min Typ Max Unit
Power Supply
tBUS_FILTER VBUS1 VBUS1 Filter Time (Figure x3) −2−ms
MASTER Serial Peripheral Interface (MASTER SPI)
tsck SCK SPI Clock Period SPI Baudrate Depending on
Configuration Input Bits (see Interface
Mode page 16). Tolerance is Equal to
Xtal Oscillator Tolerance. (Figure 7)
−2−ms
−8−ms
tSCK_HIGH SPI Clock High Time −tsck /2 −
tSCK_LOW SPI Clock Low Time −tsck /2 −
tSDI_SET SDI SPI Data Input Setup Time 125 − − ns
tSDI_HOLD SPI Data Input Hold Time 125 − − ns
tSDO_VALID SDO SPI Data Output Valid Time CL= 20 pF (Figure 7) − − 100 ns
tCS_HIGH
CSBCSB
SPI Chip Select High Time (Figure 7) 0.5 ×tSCK − −
tCS_SET SPI Chip Select Setup Time 0.5 ×tSCK − −
tCS_HOLD SPI Chip Select Hold Time 0.5 ×tSCK − −
tTREQ_LOW
TREQ
TREQ Low Time (Figure 7) 125 − − ns
tTREQ_HIGH TREQ High Time 125 − − ns
tTREQ_SET TREQ Setup Time 125 − − ns
tTREQ_HOLD TREQ Hold Time 125 − − ns
Universal Asynchronous Receiver/Transmitter (UART)
fUART TXD,
RXD
UART Interface Baudrate Baudrate Depending on Configuration
Input Pins (see Interface Mode
page 16).
Tolerance is equal to tolerance of Xtal
oscillator tolerance.
−19,200 −Baud
−38,400 −Baud
Figure 4. Bus Voltage Undervoltage Threshold
VBUS
t
VBUSH
VBUSL
tBUS_FILTER
<VBUS>
Comments:
<VBUS> is an internal signal which can be verified with the Internal State Service.
tBUS_FILTER
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Figure 5. VDD2 Undervoltage Threshold
t
VDD2
VDD2L
VDD2H
<VDD2>
Comments:
<VDD2> is an internal signal which can be verified with the System State Service.
t
V20V
V20VL
V20VH
<V20V>
Comments:
<V20V> is an internal signal which can be verified with the System State Service.
V20V_hyst
Figure 6. V20V Undervoltage Threshold levels
Figure 7. SPI Bus Timing Diagram
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
DO
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
CLK
DI
CS
tSCK
tSDI_SET tSDI _HOLD
tCS _SET tSCK _HIGH tSCK _LOW
tCS_HOLD
tCS _HIGH
tSDO_VALID
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Figure 8. Temperature Monitoring Levels
Figure 9. TREQ Timing Diagram
<TW>
SAVEB
RESETB
Comments :
−<TW> is an internal signal which can be verified with the System State Service.
−No SPI / UART communication possible when RESETB is low!
−It’s assumed all voltage supplies are within their operating condition.
t
T
TTW
TTSD
THyst
THyst
DT
No rm a l
Stand−By
Reset
Sta rt−Up
No rm a l
Stand−By
Analog State
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
DO
CLK
DI
CS
TREQ
tTREQ _SET
LSB 1 72
Dummy Dummy Dummy Dummy
tTREQ _LOW tTREQ_HIGH
tTREQ_HOLD
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APPLICATION SCHEMATIC
Figure 10. Schematic of NCN5120 Development Board (Part 1)
NCN51205GEVB
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APPLICATION SCHEMATIC
Figure 11. Schematic of NCN5120 Development Board (Part 2)
NCN51205GEVB
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Figure 12. Top Layer of NCN5120 Development Board
Figure 13. Bottom Layer of NCN5120 Development Board
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