NXP Semiconductors LPC553 Series Instruction Manual

AN13707

Hardware Design Guidelines for LPC553x/LPC55S3x Microcontrollers

Rev. 1 — 4 September 2023 Application note

Document Information

Information Content

Keywords Hardware Design Guidelines, LPC553x

Abstract This document guides hardware engineers to design and test their LPC553x/S3x controller-based

designs. The document provides information about board layout recommendations and design

checklists.

NXP Semiconductors AN13707

Hardware Design Guidelines for LPC553x/LPC55S3x Microcontrollers

1 Introduction

This document helps the hardware engineers to design and test their LPC553x/S3x controller-based designs.

The document provides information about board layout recommendations and design checklists to ensure first-

pass success and avoid any board bring-up problems.

This document only focuses on LPC553x/S3x.

Note: LPC553x/S3x devices are not pin-to-pin compatible with other LPC55 series devices.

This guide is released with the relevant device-specific hardware documentation such as data sheets, reference

manuals, and application notes available on www.nxp.com.

2 LPC553x/S3x family comparison

All LPC553x/S3x family is based on the Arm Cortex-M33 core, with PowerQuad Accelerator, enhanced timer,

and analog features to support motor control applications. The ‘S’ in the middle of the part name means that this

part provides more security features, such as TrustZone Support.

Type number Flash/

Total

RAM/KB

CAN FD USB GPIO Flex SPI ADC

channel

DAC

outputs

Internal

DAC

Comparator Tamper

pins

OP Amp CRC/1/2/3 DMIC

LPC5536JBD100 256 128 Y FS 66 Y 23 2 1 4 4 3 Y Y

LPC5536JBD64 256 128 Y - 39 Y 13 1 2 4 2 3 Y y

LPC5534JBD100 128 96 Y FS 66 Y 23 2 1 4 4 3 Y Y

LPC5534JBD64 128 96 Y - 39 Y 12 1 2 4 2 3 Y y

LPC5534JHI48 128 96 Y - 32 Y 10 - 1 4 2 3 Y Y

LPC5536JHI48 256 128 Y - 32 Y 10 - 1 4 2 3 Y Y

Table 1. LPC553x/S3x family core features

Note: The last 18 pages (9 KB) are reserved on the 256 KB flash devices for the Protected Flash Region

(PFR), resulting in 247 KB of internal flash memory for the user.

For more information, refer to the latest version of the Datasheet and Reference Manual (RM) from

www.nxp.com.

3 Power supply

This section gives details of the power supply for the LPC553x/S3x series.

3.1 Introduction

LPC553x/S3x series require a single operating voltage supply on MCU VDD_MAIN/VDD_MAIN_PWR pins

(1.8 V to 3.6 V), two main I/O supplies on VDDIO_1 (1.8 V to 3.6 V) and VDDIO_2 (1.08 V to 3.6 V) pins, and a

separate Battery Supply (VBAT) on VBAT pin (1.71 V to 3.6 V).

LPC553x/S3x internal core’s voltage is supplied by an internal DC-DC regulator or selectable LDO such that the

DC-DC converter can be bypassed.

Refer to Using the DC-DC and LDO Features on the LPC553x/LPC55S3x Family (document AN13528) for

details.

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NXP Semiconductors AN13707

Hardware Design Guidelines for LPC553x/LPC55S3x Microcontrollers

47 pF

100 nF

22 μF

47 pF

100 nF

4.7 μF

22 μF

4.7 μH

LPC553x

VDD_MAIN_PWR

VDD_MAIN VBAT

VSS_MAIN VSS_MAIN_PWR

VDD_CORE(1.0-1.2 V)

MCU MAIN

1.9 V/3.3 V

MCU VBAT

1.9 V/3.3 V

Figure 1. Using internal DC-DC converter

47 pF

100 nF

22 μF

47 pF

100 nF

4.7 μF

LPC553x

VDD_MAIN_PWR

VDD_MAIN VBAT

VSS_MAIN VSS_MAIN_PWR

VDD_CORE

MCU MAIN

1.9 V/3.3 V

MCU VBAT

1.9 V/3.3 V

Figure 2. Using internal LDO

3.2 Two I/O power supplies

LPC553x/S3x have two I/O supplies, VDDIO_1 and VDDIO_2.

VDDIO_1 supports 1.8 V to 3.6 V.

VDDIO_2 supports 1.08 V to 3.6 V.

Pin GPIO pins

VDDIO_1 PIO0_1

PIO0_7 to PIO0_8

PIO0_10 to PIO0_12

PIO0_15 to PIO0_17

PIO0_23

PIO0_27

PIO0_31

PIO1_0

PIO1_5 to PIO1_10

PIO1_19 to PIO1_24

Table 2. LPC553x/S3x power supply for pins

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NXP Semiconductors AN13707

Hardware Design Guidelines for LPC553x/LPC55S3x Microcontrollers

Pin GPIO pins

PIO2_0 to PIO2_1

RESETN

VDDIO_2 P0_0

P0_2 to P0_6

P0_9

P0_13 to P0_14

P0_18 to P0_22

P0_24 to P0_26

P0_28 to P0_30

P1_1 to P1_4

P1_11 to P1_18

P1_25 to P1_31

Table 2. LPC553x/S3x power supply for pins...continued

3.3 Separate VBAT

LPC553x/S3x’s VBAT pin requires a separate power supply with the range from 1.71 V to 3.6 V.

3.4 Bulk and decoupling capacitors

The effectiveness of the bulk and the decoupling capacitors depends on the optimum placement and connection

type. The bulk capacitors are used for a local power supply to the power pin, near the decoupling capacitors,

and as close as possible to the assigned reference voltage pin. Decoupling capacitors make the current loop

between supply, MCU, and reference ground as short as possible to reduce high-frequency transients and

noises. Therefore, all decoupling capacitors must be placed as close as possible to the devices power supply

pins. In two-layer and multilayer PCBs, the ground side of the decoupling capacitor must have a via to the pad,

which goes directly down to the internal ground plane. The route distance between the capacitors to the power

plane must be as short as possible.

Figure 3. Bulk and decoupling capacitor connection

4 Clock circuitry

This section gives details of the clock circuitry.

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NXP Semiconductors AN13707

Hardware Design Guidelines for LPC553x/LPC55S3x Microcontrollers

4.1 Introduction

The LPC553x/S3x has the following clock sources:

•Internal Free Running Oscillator (FRO). This oscillator provides a selectable 96 MHz output, and a 12 MHz

output (divided down from the selected higher frequency) that can be used as a system clock. The FRO

is trimmed to +/- 1 % accuracy over the entire voltage and 0 °C to 85 °C. The FRO is trimmed to +/- 2 %

accuracy over the entire voltage and -40 °C to 105 °C.

•32 kHz Internal Free Running Oscillator FRO. The FRO is trimmed to +/- 2 % accuracy over the entire voltage

and temperature range.

•Internal low-power oscillator (FRO 1 MHz) trimmed to +/- 15 % accuracy over the entire voltage and

temperature range.

•Crystal oscillator with an operating frequency of 12 MHz to 32 MHz, and an option for the external clock input

(bypass mode) for clock frequencies of up to 25 MHz.

•Crystal oscillator with 32.768 kHz operating frequency.

•PLL0 and PLL1 allow CPU operation up to the maximum CPU rate without the need for a high-frequency

external clock. PLL0 and PLL1 can run from the internal FRO 12 MHz output the external oscillator, internal

FRO 1 MHz output, or the 32.768 kHz RTC oscillator.

•Clock output function with a divider to monitor internal clocks.

•Frequency measurement unit for measuring the frequency of any on-chip or off-chip clock signal.

•Each crystal oscillator has one embedded capacitor bank, where each can be used as an integrated

load capacitor for the crystal oscillators. Using APIs, the capacitor banks on each crystal pin can tune the

frequency for crystals with a Capacitive Load (CL) leading to conserving board space and reducing costs.

Note: For external crystal oscillator and RTC oscillator, LPC553x/S3x have a capacitor bank feature. It means

that the stabilizing capacitors can be unsoldered on both 32 kHz and 16 MHz XTAL. We also suggest the user

keep the two stabilizing capacitors as “DNP/Do Not Populate” on PCB.

4.2 Capacitor bank

Each crystal oscillator has one embedded capacitor bank, which is always enabled, and its capacitance can

be adjusted in certain range (IEC equivalent capacitive load: 6 - 10 pF). The capacitor bank can be used as

integrated load capacitors for the crystal oscillators. It helps save external load capacitors of the crystal and

therefore the system BOM cost.

For the capacitor bank usage, refer to Understanding Cap Bank in LPC55(S)xx (document AN13057).

4.3 Crystal oscillator

The crystal oscillator has one embedded capacitor bank that can be used as an integrated load capacitor for the

crystal oscillators. The capacitor bank on each crystal pin can tune the frequency for crystals with a Capacitive

Load (CL) between 6 to 10 pF (IEC equivalent). Simple APIs can be used to configure the capacitor bank based

on the crystal Capacitive Load (CL) and measured PCB parasitic capacitances on the XIN and XOUT pins.

In the crystal oscillator circuit, only the crystal (XTAL) must be connected while the CX1 and CX2 on

XTAL32M_P and XTAL32M_N pins can optionally be connected. No additional capacitance needs to be added

to the PCB when the computation of the required Capacitance Load is less than 20 pF (10 pF equivalent IEC),

When the aforesaid load is greater than 20 pF (10 pF equivalent IEC), additional capacitance is required. (see

Figure 4.) For more information, refer to the Cap Bank API chapter in the LPC553x/S3x Reference Manual.

In bypass mode, an external clock (maximum frequency of up to 25 MHz) can also be connected to

XTAL32M_P if XTAL32M_N is left open. The external [0 – VH] square signal can be applied on the XTAL32M_P

pin from 0 V to 850 mV.

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NXP Semiconductors AN13707

Hardware Design Guidelines for LPC553x/LPC55S3x Microcontrollers

LPC

XTAL32M_P XTAL32M_N

CX1 CX2

XTAL

Figure 4. Reference oscillator circuit

Symbol Description

XTAL Quartz Crystal / Ceramic Resonator

CX1 Stabilizing Capacitor

CX2 Stabilizing Capacitor

Table 3. Components of the oscillator circuit

For best results, it is critical to select a matching crystal for the on-chip oscillator. Load Capacitance (CL), Series

Resistance (RS), and Drive Level (DL) are important parameters to consider while choosing the crystal. After

selecting the proper crystal, the external load capacitor CX1 and CX2 values can also be generally determined by

the following expression:

CX1 = CX2 = 2CL - (CPad + CParasitic + Ccapbank)

Where:

CL - Crystal load capacitance

CPad - Pad capacitance of the XTAL32M_P and XTAL32M_N pins (~3 pF).

CParasitic – Parasitic or stray capacitance of external circuit.

Ccapbank – Cap Bank

Although CParasitic can be ignored in general, the actual board layout and placement of external components

influence the optimal values of external load capacitors. Therefore, it is recommended to fine-tune the values

of external load capacitors on the actual hardware board to get an accurate clock frequency. For fine-tuning,

output the RTC Clock to one of the GPIOs and optimize the values of external load capacitors for minimum

frequency deviation. The load capacitors are dependent on the specifications of the crystal and the board

capacitance. It is recommended to have the crystal manufacturer evaluate the crystal on the PCB.

4.3.1 Crystal Printed Circuit Board (PCB) design guidelines

•Connect the crystal and external load capacitors on the PCB as close as possible to the oscillator input and

output pins of the chip.

•The length of traces in the oscillation circuit must be as short as possible and must not cross other signal

lines.

•Ensure that the load capacitors CX1 and CX2, in case of third overtone crystal usage, have a common ground

plane.

•Loops must be made as small as possible to minimize the noise coupled through the PCB and to keep the

parasitic as small as possible.

•Lay out the ground (GND) pattern under the crystal unit.

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NXP Semiconductors AN13707

Hardware Design Guidelines for LPC553x/LPC55S3x Microcontrollers

•Do not lay out other signal lines under the crystal unit for multi-layered PCB.

4.4 RTC oscillator

The crystal oscillator has an embedded capacitor bank that can be used as an integrated load capacitor for the

crystal oscillators. The capacitor banks on each crystal pin can tune the frequency for crystals with a Capacitive

Load (CL) between 6 to 10 pF (IEC equivalent). Simple APIs can be used to configure the capacitor banks

based on the crystal Capacitive Load (CL) and measured PCB parasitic capacitances on the XIN and XOUT

pins.

In the RTC crystal oscillator circuit, only the 32.768 kHz crystal (XTAL) needs to be connected while the CX1

and CX2 on XTAL32K_P and XTAL32K_N pins (See Figure 5.) can also optionally be connected. No additional

capacitance needs to be added to the PCB when the computation of the required capacitance load is less

than 20 pF (10 pF equivalent IEC). When this load is greater than 20 pF (10 pF equivalent IEC), additional

capacitance is required. Refer to the Cap Bank API chapter in the LPC553x/S3x Reference Manual.

In bypass mode, an external clock (maximum frequency of up to 100 kHz) can also be connected to

XTAL32K_P if XTAL32K_N is left open. An external [0 – VH] square signal can be applied on the XTAL32K_P

pin with 1.1 V +/-10 %.

An external signal below 1.0 V or above 1.2 V cannot be applied.

LPC

XTAL32K_P XTAL32K_N

CX1 CX2

XTAL

Figure 5. Reference oscillator circuit

For best results, it is critical to select a matching crystal for the on-chip oscillator. Load Capacitance (CL), Series

Resistance (RS), and Drive Level (DL) are important parameters to consider while choosing the crystal. After

selecting the proper crystal, the external load capacitor CX1 and CX2 values can also be generally determined by

the following expression:

CX1 = CX2 = 2CL - (CPad + CParasitic + Ccapbank)

Where:

CL - Crystal load capacitance

CPad - Pad capacitance of the XTAL32K_P and XTAL32K_N pins (~3 pF).

CParasitic – Parasitic or stray capacitance of external circuit.

Ccapbank – Cap Bank

Although CParasitic can be ignored in general, the actual board layout and placement of external components

influences the optimal values of external load capacitors. Therefore, it is recommended to fine-tune the values

of external load capacitors on the actual hardware board to get the accurate clock frequency. For fine-tuning,

output the RTC Clock to one of the GPIOs and optimize the values of external load capacitors for minimum

frequency deviation.

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NXP Semiconductors AN13707

Hardware Design Guidelines for LPC553x/LPC55S3x Microcontrollers

4.4.1 RTC Printed Circuit Board (PCB) design guidelines

•Connect the crystal and external load capacitors on the PCB as close as possible to the oscillator input and

output pins of the chip.

•The length of traces in the oscillation circuit must be as short as possible and must not cross other signal

lines.

•Ensure that the load capacitors CX1, CX2, and CX3, in case of third overtone crystal usage, have a common

ground plane.

•Loops must be made as small as possible to minimize the noise coupled through the PCB and to keep the

parasitic as small as possible.

•Lay out the ground (GND) pattern under the crystal unit.

•Do not lay out other signal lines under the crystal unit for multi-layered PCB.

4.5 Common suggestions for the PCB layout of the oscillator circuit

The crystal oscillator is an analog circuit and must be designed carefully and according to the analog-board

layout rules, see Figure 6.

•Send the PCB to the crystal manufacturer to determine the negative oscillation margin as well as the optimum

value of CXTAL and CEXTAL capacitors. The data sheet includes recommendations for the tank capacitors

CXTAL and CEXTAL. These values together with the expected PCB, pin, and stray capacitors values must be

used as an initial point.

•The crystal or resonator oscillator is sensitive to stray capacitance and noise from other signals. It must be

placed away from high-frequency devices and traces to avoid and reduce the capacitive coupling between the

XTAL and EXTAL pins and their PCB traces.

•The main oscillation loop current is flowing between the crystal and the load capacitors. This signal path

(Oscillator to CEXTAL and CXTAL to Oscillator) must be kept as short and symmetric tracing as possible.

Therefore, both the capacitor's ground connections must always be closer to the VSS pin using the copper-

poured ground plane and there must be several vias to the internal ground layer in the PCB for efficient

grounding.

•Connect the EXTAL and XTAL pins to the required oscillator components only, and not to any other devices.

The following figure shows the recommended placement and routing for the oscillator layout.

Cooper pour

GROUND plane

GROUND via

GROUND

2nd layer

Crystal/

oscillator

All VSS pins should

be connected to

common GROUND

at the PCB level

VSS

XTAL

EXTAL

CXTAL

CEXTAL

Figure 6. Suggested crystal oscillator layout

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NXP Semiconductors AN13707

Hardware Design Guidelines for LPC553x/LPC55S3x Microcontrollers

5 Boot mode configuration

This section gives information about boot mode selection and configuration.

5.1 Boot mode selection

The internal ROM memory is used to store the boot code called boot ROM. After a reset, the Arm processor

starts its code execution from this memory. The boot ROM code is executed every time the part is powered-ON,

is reset, or wakes up from a deep power-down mode of low-power modes.

Images can be stored either in the internal flash as the LPC553x/S3x has an internal flash for code and data

storage or in the Serial NOR connected to the FLEXSPI controller. The code is then validated, and the boot

ROM vectors to on-chip flash or the off-chip FLASH. Depending on the values of the CMPA bits, ISP pin, and

the image header type definition, the bootloader decides whether to boot from the internal flash, off-chip flash,

or run into ISP mode. The LPC553x/S3x reads the status of the ISP pins to determine the boot source. See

Table 4.

Boot mode ISP1 (PIO0_7

pin)

ISP0 (PIO0_5

pin)

Description

Internal

Flash boot

LOW LOW The LPC553x looks for a valid image from the internal flash; if there is no

valid image, the LPC553x looks for a valid image in the recovery boot device

if recovery boot is enabled (4:0, word 1 in CMPA) in CMPA. If it still fails, the

LPC553x enters ISP boot mode based on DEFAULT_ISP_MODE bits.

ISP boot LOW HIGH One of the serial interfaces (UART0, I2C1, HS_SPI, USB0-FS, CAN) is used

to download the image from the host into the internal flash. The first valid

probe message on USART, I2C, SPI, CAN, or USB locks in that interface

FLEXSPI

boot

HIGH LOW The LPC553x looks for a valid image in the external flash; if there is no valid

image, the LPC553x looks for a valid image in the recovery boot device if

recovery boot is enabled (4:0, word 1 in CMPA) in CMPA. If it still fails, the

LPC553x enters ISP boot mode based on DEFAULT_ISP_MODE bits.

AUTO boot HIGH HIGH The LPC553x looks for a valid image in the internal flash; if there is no valid

image, the LPC553x looks for a valid image in the external NOR flash; if no

valid image, the LPC553x looks for a valid image in the recovery boot device

if recovery boot is enabled d (4:0, word 1 in CMPA) in CMPA. If it still fails,

the LPC553x enters ISP boot mode based on DEFAULT_ISP_MODE bits.

Table 4. Boot mode and ISP download modes based on ISP pins

Table 5 shows the ISP pin assignments and is the default pin assignment used by the Boot ROM that cannot be

changed.

ISP pin Port pin assignment

ISP0 PIO0_5

ISP1 PIO0_7

USART_ISP mode

FC0_TXD PIO0_30

FC0_RXD PIO0_29

I2C_ISP mode

FC1_SDA PIO0_13

FC1_SCL PIO0_14

Table 5. ISP pin assignment

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NXP Semiconductors AN13707

Hardware Design Guidelines for LPC553x/LPC55S3x Microcontrollers

ISP pin Port pin assignment

SPI Flash Recovery mode

FC0_TXD_SCL_MISO_WS PIO0_30

FC0_RXD_SDA_MOSI_DATA PIO0_24

FC0_CTS_SDA_SSELN0 PIO0_31

FC0_SCK PIO0_28

HS_SPI_SCK PIO1_2

HS_SPI_SSEL1 PIO1_1

HS_SPI_MISO PIO1_3

HS_SPI_MOSI PIO0_26

FC3_TXD_SCL_MISO_WS PIO0_2

FC3_RXD_SDA_MOSI_DATA PIO0_3

FC3_CTS_SDA_SSELN0 PIO0_4

FC3_SCK PIO0_6

SPI ISP mode

HS_SPI_SCK PIO1_2

HS_SPI_SSEL1 PIO1_1

HS_SPI_MISO PIO1_3

HS_SPI_MOSI PIO0_26

USB0-FS ISP mode

USB0_VBUS PIO1_31(if [bit_22] @0x3FC14 is set to 1, use P0_22)

USB0_DP Dedicated pin per package

USB0_DM Dedicated pin per package

CAN ISP mode

CAN_TXD PIO0_30

CAN_RXD PIO1_22

FlexSPI Pins

FLEXSPI_SSEL PIO0_21

FLEXSPI_CLK PIO0_19

FLEXSPI_DQS PIO0_25

FLEXSPI_CLK_N PIO0_22

FLEXSPI_D0 PIO0_6

FLEXSPI_D1 PIO0_4

FLEXSPI_D2 PIO0_3

FLEXSPI_D3 PIO0_2

FLEXSPI_D4 PIO1_16

FLEXSPI_D5 PIO1_15

Table 5. ISP pin assignment...continued

Application note Rev. 1 — 4 September 2023

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