NXP Semiconductors MPC5746R Guide

NXP Semiconductors

Application Note

Document Number: AN4998

Rev. 1, 07/2019

Contents

1 Introduction

MPC5746R is a multi-core 32-bit microcontroller

intended for automotive powertrain applications. It is

based upon e200z4 Power® Architecture cores running at

up to 200 MHz.

Throughout this application note, MPC5746R refers to

the family of devices: MPC5743R, MPC5745R, and

MPC5746R.

This application note details the options of MPC5746R

power supplies and the correct external circuitry required

for each supply, including digital, analog, and SRAM

standby. It also discusses configuration options for clock,

reset, and ADCs, as well as recommended debug and

peripheral communication connections, and other major

external hardware required for the device.

Please note that information from the MPC5746R

Reference Manual, Data Sheet, and/or Errata report may

be repeated in this application note for the convenience

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2 MPC5746R Package Options Overview . . . . . . . . . 2

3 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

4 Clock Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5 Device Reset Configuration. . . . . . . . . . . . . . . . . . 22

6 Input/Output Pins. . . . . . . . . . . . . . . . . . . . . . . . . . 24

7 Debug Options available . . . . . . . . . . . . . . . . . . . . 28

8 Emulation device . . . . . . . . . . . . . . . . . . . . . . . . . . 32

9 ADC and Analog . . . . . . . . . . . . . . . . . . . . . . . . . . 34

10 Example Communication Peripheral connections . 40

11 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

12 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . 51

MPC5746R Hardware Design

Guide

by: NXP Semiconductors

MPC5746R Hardware Design Guide, Rev. 1

MPC5746R Package Options Overview

NXP Semiconductors2

of the reader. The Reference Manual, Data Sheet and Errata report are the official specifications for

MPC5746R and should be reviewed for the most up-to-date information available for this device.

2 MPC5746R Package Options Overview

The MPC5746R is available in four different package options; three of these are intended for production

and one is intended to provide additional features to support debug and calibration.

The package selection should be based on the number of input/output pins required for the application and

the area available for the target system. The following table shows the sizes of different packages. See the

MPC5746R Data Sheet for complete package dimensions and ball placement. Drawings are also available

on the NXP web site; search for the case outline number shown in Table 2.

3 Power Supply

MPC5746R provides several options for providing power supply voltages. The main power supplies

required are 1.25 V, 5 V and 3.3 V depending on the requirements of the application. The on-chip flash

memory supply is generated internally. The SRAM has a separate supply input for data retention features,

if they are required.

In addition the MPC5746R microcontroller includes a robust power management infrastructure that

enables applications to select among various user modes and to monitor internal voltages for high- and

Table 1. MPC5746R Package Options

Package Target Description

144 LQFP

Production

Provides access to the primary features of the device. Packages with additional pins provide

additional features and/or additional GPIO. No Nexus High Speed Aurora Trace interface is

provided on any production package, only JTAG.

176 LQFP

252 MAPBGA

292 MAPBGA Development

Provides access to primary features of device, plus Nexus High Speed Aurora Trace and

overlay/trace memory that can be used for calibration. This package is designed for debug

and calibration development use and is typically provided mounted to an interposer/adapter

system to connect to either a 144LQFP, 176 LQFP or 252 MAPBGA footprint. The Aurora

debug interface connector is provided on this adapter board, eliminating the need for the

customer to route the high speed Aurora differential pairs and allowing use on the customer

PCB.

Table 2. Package Sizes

Package Physical Size (mm) Case Outline Number

144 LQFP 20 x 20 98ASS23177W

176 LQFP 24 x 24 98ASS23479W

252 MAPBGA 17 x 17 98ASA00468D

292 MAPBGA1

1Only for development purpose and not intended for production.

17 x 17 98ASA00261D

Power Supply

MPC5746R Hardware Design Guide, Rev. 1

NXP Semiconductors 3

low-voltage conditions. The monitoring capability is also used to ensure supply voltages and internal

voltages are within the required ranges before the microcontroller can exit reset. The MPC5746R MCU

supports three different input voltages:

• 1.25 V (required) for the internal logic. This supply may be provided externally or generated from

either the 3.3 V or 5.0 V supply using an external NPN Bipolar Junction Transistor (BJT) ballast

transistor and the internal 1.25 V regulator control.

• 5 V (required) for the Power Management controller, I/O, Debug, ADCs and external

communication interfaces

• 3.3 V (optional) for I/O, Debug and external communication interfaces

The 3.3 V supply required for the flash memory is generated by an on-chip regulator. This regulator

requires an external decoupling capacitor on VDD_HV_FLA.

3.1 Power Supply Signals and Pins

Table 3 lists all power domains with corresponding pin names.

Table 3. MCU Supply Pins

Domain Name Supply Voltage1

1Nominal voltage, see MPC5746R Data Sheet for actual voltage specifications.

Description

VDD_LV2

2This supply may be optionally provided by the on-chip regulator using a pass transistor. See Section 3.1.2

1.25 V Core Logic Low Voltage Supply

VDD_HV_IO_MAIN 5.0 V Main I/O Voltage Supply

VDD_HV_ADV_SAR 5.0 V SAR ADC Voltage Supply

VDD_HV_ADR_SAR 5.0 V SAR ADC Voltage Reference

VDD_HV_ADV_SD 5.0 V Sigma-Delta ADC Voltage Supply

VDD_HV_ADR_SD 5.0 V Sigma-Delta ADC Voltage Reference

VDD_HV_IO_JTAG 3.3 V or 5.0 V Production Device JTAG I/O and External Oscillator

Voltage Supply

VDD_HV_IO_FEC 3.3 V or 5.0 V Ethernet I/O Supply

VDD_HV_IO_MSC 3.3 V or 5.0 V Microsecond Channel I/O Supply

VDD_HV_PMC 5.0 V Power Management Controller Supply

VDD_HV_FLA3

3No connection to external supply required, but it does require a bypass capacitor.

3.3 V PMC Flash Regulator Bypass Capacitor

VDD_LV_BD4

4Only present on the 292 MAPBGA emulation device.

1.25 V Emulation Device Core Logic Low Voltage Supply

VDD_HV_IO_BD43.3 V or 5.0 V Emulation Device Main I/O Voltage Supply

VDDSTBY5

5Ramp rate must be less than 16.6 kV/s as per limitation for the 0N94H mask set. Refer to the latest MPC5746R Data

Sheet for additional requirements.

1.3 V–5.9 V Standby RAM Supply Input

MPC5746R Hardware Design Guide, Rev. 1

Power Supply

NXP Semiconductors4

Some of the supplies can be powered with different supply voltages. In particular, the MCU allows

flexibility in the supply of voltages that power selected input and output pins. These supplies are “high”

supplies and can be connected to either a nominal 3.3 V or 5.0 V supply. In addition we recommend

keeping all supply slew rates below 25 V/ms.

Refer to the MPC5746R Data Sheet to learn what voltages can be connected to the power pins. Supply

pins/balls differ from package to package. Please refer to section 3.1.1 for package differences.

The following table shows several power supply design schemes. The flexibility of the supply

configurations provides the board designer several options for optimizing the design.

Please refer to the IO description attached to the MPC5746R Reference Manual for more details.

3.1.1 Power supply package differences

There are different numbers of balls/pins available for the power supplies in each of the MPC5746R

package options. In addition, for some package options, some power supplies are not available. The table

below shows, for each package, the number of balls available for the power supply input to the device.

All supply balls that are available on the package should be connected to a supply voltage.

Table 4. Power supply schemes

Supply options Reference

Single 5 V supply Section 3.1.2

Multi supply with 5 V and 3.3 V Section 3.1.3

Multi supply with 5 V and 1.25 V Section 3.1.4

Table 5. Number of power supply balls/pins versus package

Supply Domain Nominal Voltage 144LQFP 176LQFP 252BGA

VDD_LV11.25 V 6 6 14

VDD_HV_IO_MAIN 5.0 V 5 5 7

VDD_HV_ADV_SAR 5.0 V 1 1 2

VDD_HV_ADR_SAR 5.0 V 1 1 1

VDD_HV_ADV_SD 5.0 V 1 1 1

VDD_HV_ADR_SD 5.0 V 1 1 1

VDD_HV_IO_JTAG 3.3 V or 5.0 V 1 1 1

VDD_HV_IO_FEC 3.3 V or 5.0 V 1 1 1

VDD_HV_IO_MSC 3.3 V or 5.0 V 1 1 1

VDD_HV_PMC 5.0 V 1 1 1

VDD_HV_FLA23.3 V 1 1 1

VDD_LV_BD31.25 V - - -

Power Supply

MPC5746R Hardware Design Guide, Rev. 1

NXP Semiconductors 5

3.1.2 Single 5 V Supply

This topology uses a single 5 V supply for all I/O, with the internal regulator providing the 1.25 V for the

VDD_LV core supply. Note that most Fast Ethernet Controller (FEC) physical layer interfaces require 3.3

V signals, so the FEC would not normally be operational in this configuration.

Figure 1. Single 5 V Supply (no Ethernet)

1 VDDSTBY may need to be powered by a separate supply in the case where the standby SRAM data retention feature is required. This figure is intended to illustrate that a single 5 V supply

may be used where appropriate for the design.

2 VDD_HV_IO_JTAG is typically powered by a 3.3 V supply for compatibility with many debug tools. However if tools support 5 V or JTAG access is not required, a 5 V supply may be used and

the JTAG pins can be used as normal GPIO.

VDD_HV_IO_BD43.3 V or 5.0 V - - -

VDDSTBY41.3 V - 5.9 V 1 1 1

1This supply may be optionally provided by the on-chip regulator using a pass transistor. See Section 3.1.2

2Except bypass capacitor no connection to external supply required.

3Only present on the 292 MAPBGA emulation device.

4Ramp rate must be less than 16.6 kV/s as per limitation for the 0N94H mask set. Refer to the latest

MPC5746R Data Sheet for additional requirements.

Table 5. Number of power supply balls/pins versus package

Supply Domain Nominal Voltage 144LQFP 176LQFP 252BGA

MPC5746R Hardware Design Guide, Rev. 1

Power Supply

NXP Semiconductors6

3.1.3 Multi Supply - 5 V and 3.3 V

In this configuration there are dual supply voltages, 5 V and 3.3 V. The 5 V supply provides the I/O supply,

the internal regulator provides the 1.25 V core supply and the 3.3 V supply is used to power the FEC

subnet.

Figure 2. Multi Supply, 5 V and 3.3 V with Ethernet

NOTE

VDD_HV_IO_JTAG and/or VDD_HV_IO_MSC could also be powered by

3.3 V.

3.1.4 Multi Supply: 5.0 V and 1.25 V

In this configuration there are dual supply voltages, 5 V and 1.25 V. I/O is powered by the 5 V supply and

the core voltage is powered by the 1.25 V supply. Note that most Fast Ethernet Controller (FEC) physical

layer interfaces require 3.3 V signals, so the FEC would not normally be operational in this configuration.

Power Supply

MPC5746R Hardware Design Guide, Rev. 1

NXP Semiconductors 7

Figure 3. Multi Supply, 5 V and 1.25 V without Ethernet

3.1.5 Decoupling Capacitor Recommendation for supply domains

Table 6 shows all power domains and the suggested decoupling and/or filter capacitors for their

corresponding pins. These values are provided as a guideline and will vary depending on the application

and capability of the power supplies used.

Table 6. Supply Decoupling Requirements

Domain Supply Voltage Bulk Bypass (each pin)

VDD_LV11.25 V 4.7 μF2220nF ~ 47 nF

VDD_HV_IO_MAIN 5.0 V 4.7 uF3100nF ~ 10 nF

VDD_HV_ADV_SAR 5.0 V 10 μF 220nF ~ 100 nF

VDD_HV_ADR_SAR 5.0 V – 220nF ~ 100 nF

VDD_HV_ADV_SD 5.0 V 4.7 μF 220nF ~ 100 nF

VDD_HV_ADR_SD 5.0 V – 220nF ~ 100 nF

VDD_HV_IO_JTAG 3.3 V or 5.0 V 4.7 μF 220nF ~ 100 nF

VDD_HV_IO_FEC 5.0 V or 3.3 V 4.7 μF 220nF ~ 100 nF

VDD_HV_IO_MSC 5.0 V or 3.3 V 4.7 μF 220nF ~ 100 nF

VDD_HV_PMC 5.0 V 4.7 μF 220nF ~ 47 nF

MPC5746R Hardware Design Guide, Rev. 1

Power Supply

NXP Semiconductors8

3.2 On-chip 1.25 V Regulator

In order to lower system cost, MPC5746R provides an on-chip regulator that can use an external NPN pass

transistor to provide the 1.25 V core supply voltage from either a 5.0 V or 3.3 V supply. The recommended

external circuits are shown in Figure 4.

Figure 4. 1.25 V Supply with external pass Transistor

When the 5.0 V supply configuration is in use, the internal regulator regulates the BJT emitter voltage to

1.25[V], which is used as the core supply (VDD_LV). The remaining energy needs to be dissipated via the

transistor as heat. The capability of the transistor package to dissipate heat degrades as the temperature

increases. To overcome such problems, the user should analyze the thermal capabilities of the transistor and

add sufficient heat dissipation options as needed.

VDD_HV_FLA43.3 V 1 μF~2.2 μF 1 nF

VDD_LV_BD51.25 V 4.7 μF 100 nF

VDD_HV_IO_BD55.0 V 4.7 μF 100 nF

VDDSTBY 1.3 V–5.9 V 1 μF 100 nF

1This supply may be optionally provided by the on-chip regulator using a bipolar junction transistor (BJT). See Section 3.1.2.

2Recommend 4 x 4.7 uF bulk capacitors with lower ESR (each < 200 mΩ) for VDD_LV supply domain.

3Recommend 5 x 4.7 uF bulk capacitors for VDD_HV_IO_MAIN supply domain.

4No connection to external supply required.

5Only present on the 292 MAPBGA emulation device.

Table 6. Supply Decoupling Requirements

Domain Supply Voltage Bulk Bypass (each pin)

Power Supply

MPC5746R Hardware Design Guide, Rev. 1

NXP Semiconductors 9

There are several options available: 1) use a heat sink 2) populate a copper layer(s) beneath the transistor with

thermal VIAS to improve the heat dissipation. NXP recommends consulting the transistor vendor to obtain

optimal thermal design.

As another option, an external resistor can be used to minimize the extra heat. The resistor will drop the

collector voltage to mitigate the heat dissipation of the pass transistor (BJT). In this case, the collector voltage

needs to be maintained at 3 V or above.

NXP recommends a low inductance between the transistor base and the VRC_CTRL pin/pad. This should be

less than 100nH. An inductance of 15nH is an optimal value.

The following examples explain how to calculate the power dissipation of the BJT with different resistor (R)

values.

Example.1:

Supply voltage is 5.0 V, R=1.8 Ω, Max current consumption at VDD_LV (Ivdd_lv) = 700 [mA] and

nominal VDD_LV = 1.25 [V]

Voltage drop across the R = 1.8 Ω x 700mA = 1.260 [v], voltage at collector 5 V-1.26 V = 3.74 [V] (>

3 V)

Power dissipation on BJT transistor P (Tr): P (Tr) = (5 - 1.25 - 1.26) x 0.7 = 1.743 [w]

Power dissipation on resistor P(R): P(R)= 1.26 x 0.7 = 0.882 [w]

Example.2:

Supply voltage is 5.0 V, R=2.0 Ω, Max current consumption at VDD_LV (Ivdd_lv) = 700 [mA] and

nominal VDD_LV = 1.25 [V]

Voltage drop across the R = 2.0 Ω x 700mA = 1.400 [V], voltage at collector 5 V-1.4 V = 3.6 [V] (> 3

Power dissipation on BJT transistor P (Tr) given by: P (Tr) = (5 - 1.25 - 1.40) x 0.7 = 1.645 [w]

Power dissipation on resistor P(R) given by: P(R)= 1.40 x 0.7 = 0.980 [w]

3.2.1 Recommended Pass Transistor

The on-chip 1.25 V regulator requires an external BJT for operation. Refer to the following table for

recommended pass transistors. Please refer to the MPC5746R Data Sheet to obtain the requirements for

the BJT device.

Table 7. Recommended pass Transistors

Transistor Collector capacitor (CC)Base capacitor Resistor Supply options

ON semiconductor

NJD2873T4

4.7 uF (min) ESR<200 mΩ-2 Ω 5.0 V

ON semiconductor

NJD2873T4

4.7 uF (min) ESR<200 mΩ - - 3.3 V

ROHM 2SCR574D3 A07 4.7 uF (min) ESR<200 mΩ1 uF - 3.3 V

MPC5746R Hardware Design Guide, Rev. 1

Power Supply

NXP Semiconductors10

3.3 External 1.25 V Supply

If an external regulator is used for the VDD_LV supply, the pass transistor is not required. In this case, the

internal voltage regulator driver should be disabled by setting the REG_SEL bit in the Miscellaneous

Device Configuration Format (DCF) client. This is accomplished via a DCF record programmed into the

UTEST flash memory. See the DCF Chapter of the MPC5746R Reference Manual for complete

information regarding the use of DCF records and UTEST flash memory.

Note that the VRC_CTRL will remain active until the Reset Generation Module (RGM) enters the reset

phase 3, where the UTEST configuration is read. When using an external VDD_LV supply, the

VRC_CTRL pin should be left floating (no connect). See the RGM chapter of the MPC5746R Reference

Manual for more information.

3.4 Input and output pins power supply segmentation

Each I/O pin is associated with one of the power domains. The majority of the I/O pins are powered by the

VDD_HV_IO_MAIN. The VDD_HV_IO_JTAG, VDD_HV_IO_FEC, and VDD_HV_IO_MSC domains

are primarily intended to allow the JTAG, FEC and MSC interfaces to be operated at a voltage level

different from the VDD_HV_IO_MAIN domain if desired. However, they can also be used to power a

limited amount of I/O pins at an alternative voltage level.

The voltage level supplied on any I/O domain determines the output voltage level and input transition

levels for the I/O pins associated with that domain. Each power domain with corresponding I/O pins is

shown in Table 8. Each power domain needs to be maintained below 80 mA. In addition, the sum of all

I/O power domains should be maintained below 200mA as described in the MPC5746R Data Sheet. Note

that, not all of the listed I/O pins are available on some packages.1

Table 8. Power Domains vs. I/O

Power Domain I/O Pins

VDD_HV_IO_MAIN

PD[0–15]

PE[0]

PF[0–13]

PG[1–7, 9–15]

PH[0–15]

PI[0–5]

PJ[0–15]

PK[0–2, 4–5, 7–14]

PL[0–1]

VDD_HV_IO_JTAG PB[0–1]

VDD_HV_IO_FEC PC[0–13]

VDD_HV_IO_MSC PA[0–13]

VDD_HV_ADV_SAR

PW[0–3]

PX[0–15]

PY[0–15]

VDD_HV_ADV_SD PZ[0–15]

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