Linear Technology DC1732 Series Quick setup guide

dc1732f

DEMO MANUAL DC1732

DESCRIPTION

LTM9012

14-Bit, 125Msps Quad ADC

with Integrated Drivers

Demonstration circuit DC1732 supports the LTM

9012

high speed, quad ADC modules.

The versions of the 1732B demo board are listed in Table 1.

Depending on the required resolution and sample rate, the

DC1732 is supplied with the appropriate ADC. The circuitry

on the analog inputs is optimized for full bandwidth. Refer

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

to the data sheet for proper input networks for different

input frequencies.

Design files for this circuit board are available at

http://www.linear.com/demo

(TA= 25°C)

Table 1. DC1732 Variants

DC1732 VARIANTS ADC PART NUMBER RESOLUTION MAXIMUM SAMPLE RATE INPUT RANGE*

1732B-AB LTM9012-AB 14-BIT 125 Msps 220mVP-P

*With SENSE pin tied to 1.8V.

PERFORMANCE SUMMARY

PARAMETER CONDITION VALUE

Supply Voltages – DC1732B Depending on Sampling Rate, This Supply Must Provide Up to 700mA. 3V to 6V, 5V to 6V

Analog Input Range Depending on SENSE Pin Voltage 110mVP-P to 220mVP-P

Logic Input Voltages Minimum Logic High 1.3V

Maximum Logic Low 0.6V

Logic Output Voltages (Differential) Nominal Logic Levels (100Ω Load, 3.5mA Mode) 350mV/1.25V Common Mode

Minimum Logic Levels (100Ω Load, 3.5mA Mode) 247mV/1.25V Common Mode

Sampling Frequency (Convert Clock

Frequency)

See Table 1

Encode Clock Level Single-Ended Encode Mode (ENC–Tied to GND) 0V to 3.6V

Encode Clock Level Differential Encode Mode (ENC–not Tied to GND) 0.2V to 3.6V

Resolution See Table 1

Input Frequency Range See Table 1

SFDR See Applicable Data Sheet

SNR See Applicable Data Sheet

This datasheet has been downloaded fromhttp://www.digchip.com at this page

dc1732f

DEMO MANUAL DC1732

QUICK START PROCEDURE

Figure 1. DC1732 Setup

Demonstration circuit 1732 is easy to set up to evaluate the

performance of the LTM9012 modules. Refer to Figure 1

for proper measurement equipment setup and follow the

procedure below. Figure 2 shows the pinout of the analog

input header.

Setup

If a DC1371 data acquisition and collection system was

supplied with the DC1732 demonstration circuit, follow the

DC1371 quick start guide to install the required software

and for connecting the DC1371 to the DC1732 and to a PC.

DC1732 Demonstration Circuit Board Jumpers

The DC1732 demonstration circuit board should have

the following jumper settings as default positions. (as

per Figure 1)

J2: PAR/SER:Selects parallel or serial programmingmode.

(default – serial)

Optional Jumpers

J1: Term: Enables/disable optional output termination.

(default – removed)

J5: ILVDS: Selects either 1.75mA or 3.5mA of output cur-

rent for the LVDS drivers. (default – removed)

J3: LANE: Selects either 1-lane or 2-lane output modes

(default – removed) NOTE: The DC1371 does not support

1-lane operation.

J4: SHDN: Enables and disables the LTM9012.

(default – removed)

J10: WP: Enable/disables write protect for the EEPROM.

(default – removed)

Note: optional jumper should be left open to ensure proper

serial configuration.

Applying Power and Signals to the DC1732

Demonstration Circuit

The DC1371 is used to acquire data from the DC1732. The

DC1371 must FIRST be connected to a powered USB port

and have 5V applied power BEFORE applying DC power

to the DC1732. DC1732 requires 3V to 6V at TP1 and 5V

to 6V at TP4 for proper operation.

The DC1732 demonstration circuit requires up to 700mA

depending on the sampling rate and the A/D converter

supplied.

The DC1732 should not be removed, or connected to the

DC1371 while power is applied.

DC1732 F01

dc1732f

DEMO MANUAL DC1732

QUICK START PROCEDURE

Analog Input Network

For optimal distortion and noise performance the RC

network on the analog inputs may need to be optimized

for different analog input frequencies. For full bandwidth

operation, no series RC elements should be used.

In almost all cases, filters will be required on both analog

input and encode clock to provide data sheet SNR.

The filters should be located close to the inputs to avoid

reflections from impedance discontinuities at the driven

end of a long transmission line. Most filters do not present

50Ω outside the passband. In some cases, 3dB to 10dB

pads may be required to obtain low distortion.

If your generator cannot deliver full-scale signals without

distortion, you may benefit from a medium power amplifier

based on a gallium arsenide gain block prior to the final

filter. This is particularly true at higher frequencies where

IC based operational amplifiers may be unable to deliver

the combination of low noise figure and high IP3 point

required. A high order filter can be used prior to this final

amplifier, and a relatively lower Q filter used between the

amplifier and the demo circuit.

Apply the analog input signal of interest to the header on

the DC1732 demonstration circuit board marked “J15”.

There is access to the eight analog inputs. For a pin out

of this header see Figure 2 in this quick start guide, or the

attached schematic.

Encode Clock

NOTE: Apply an encode clock to the SMA connector on

the DC1732 demonstration circuit board marked “J11

CLK+”. As a default the DC1732 is populated to have a

single-ended input.

For the best noise performance, the ENCODE INPUT must

be driven with a very low jitter, square wave source. The

amplitude should be large, up to 3VP-P or 13dBm. When

using a sinusoidal signal generator a squaring circuit can

be used. Linear Technology also provides demo board

DC1075A that divides a high frequency sine wave by four,

producing a low jitter square wave for best results with

the LTM9012.

Using bandpass filters on theclock and the analoginput will

improve the noise performance by reducing the wideband

noise power of the signals. In the case of the DC1732 a

bandpass filter used for the clock should be used prior

to the DC1075A. Data sheet FFT plots are taken with 10

pole LC filters made by TTE (Los Angeles, CA) to suppress

signal generator harmonics, non harmonically related

spurs and broadband noise. Low phase noise Agilent

8644B generators are used for both the clock input and

the analog input.

Digital Outputs

Data outputs, data clock, and frame clock signals are

available on J9 of the DC1732. This connector follows the

VITA-57/FMC standard, but all signals should be verified

when using an FMC carrier card other than the DC1371.

Figure 2. Pinout for Analog Input Header (J15)

J15

HDR-2X50-2MM-THTH

DC1732a F02

GND GND

IN1+

IN1–

IN2+

IN2–

IN3+

IN3–

IN4+

IN4–

dc1732f

DEMO MANUAL DC1732

Software

The DC1371 is controlled by the PScope system software

provided or downloaded from the Linear Technology

website at http://www.linear.com/software/.

To start the data collection software if “PScope.exe”, is

installed (by default)in \Program Files\LTC\PScope\, double

click the PScope icon or bring up the run window under

the start menu and browse to the PScope directory and

select PScope.

If the DC1732 demonstration circuit is properly connected

to the DC1371, PSCOPE should automatically detect the

DC1732, and configure itself accordingly.

If everything is hooked up properly, powered and a suit-

able convert clock is present, clicking the “Collect” button

should result in time and frequency plots displayed in

the PScope window. Additional information and help for

PScope is available in the DC1371 quick start guide and in

the online help available within the PScope program itself.

Serial Programming

PScope has the ability to program the DC1732 board

serially through the DC1371. There are several options

available in the LTM9012 family that are only available

through serially programming. PScope allows all of these

features to be tested.

These options are available by first clicking on the “Set

Demo Bd Options” icon on the PScope toolbar (Figure 3).

This will bring up the menu shown in Figure 4.

Randomizer: Enables data output randomizer

Off (default): Disables data output randomizer

On: Enables data output randomizer

Two’s Complement: Enables two’s complement mode

Off (default): Selects offset binary mode

On: Selects two’s complement mode

Sleep Mode: Selects between normal operation, sleep

mode:

Off (default): Entire ADC is powered, and active

On: The entire ADC is powered down.

Channel 1 Nap: Selects between normal operation and

putting channel 1 in nap mode.

Off (default): Channel 1 is active

On: Channel 1 is in nap mode

QUICK START PROCEDURE

Figure 3. PScope Toolbar

Figure 4. Demobd Configuration Options.

This menu allows any of the options available for the

LTM9012 family to be programmed serially. The LTM9012

family has the following options:

dc1732f

DEMO MANUAL DC1732

Channel 2 Nap: Selects between normal operation and

putting channel 2 in nap mode.

Off (default): Channel 2 is active

On: Channel 2 is in nap mode

Channel 3 Nap: Selects between normal operation and

putting channel 3 in nap mode.

Off (default): Channel 3 is active

On: Channel 3 is in nap mode

Channel 4 Nap: Selects between normal operation and

putting channel 4 in nap mode.

Off (default): Channel 4 is active

On: Channel 4 is in nap mode

Output Current: Selects the LVDS output drive current

1.75mA (default): LVDS output driver current

2.1mA: LVDS output driver current

2.5mA: LVDS output driver current

3.0mA: LVDS output driver current

3.5mA: LVDS output driver current

4.0mA: LVDS output driver current

4.5mA: LVDS output driver current

QUICK START PROCEDURE

Internal Termination: Enables LVDS internal termination

Off (default): Disables internal termination

On: Enables internal termination

Outputs: Enables digital outputs

Enabled (default): Enables digital outputs

Disabled: Disables digital outputs

Test Pattern: Selects digital output test patterns. The

desired test pattern can be entered into the text boxes

provided.

Off (default): ADC input data is displayed

On: Test pattern is displayed

Once the desired settings are selected hit OK and PScope

will automatically update the register of the device on the

DC1732 demo board.

dc1732f

DEMO MANUAL DC1732

ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER

Required Circuit Components

1 1 T1 BALUN, 1:1, SMT, SM-22 MACOM MABA-007159-000000

2 6 C2, C3, C4, C11, C12, C13 CAP, X5R, 1µF, 10V, 10%, 0603 AVX 0603ZD105KAT

3 1 C7 CAP, X5R, 2.2µF, 10V, 10%, 0603 AVX 0603ZD225KAT

4 2 C5, C14 CAP, TANT, 100µF, 10V, 10%, C 6032 VISHAY 293D107X9010C2TE3

5 8 C33, C34, C35, C37 to C41 CAP, X7R, 0.01µF, 16V, 10%, 0603 AVX 0603YC103KAT

6 3 C21, C30, C31 CAP, X7R, 0.01µF, 16V, 10%, 0402 AVX 0402YC103KAT

7 1 C8 CAP, X5R, 1µF, 10V, 10%, 0402 AVX 0402ZD105KAT

8 8 C6, C9, C23 to C27, C36 CAP, X5R, 0.1µF, 10V, 10%, 0402 AVX 0402ZD104KAT

9 2 C1, C10 CAP, X5R, 4.7µF, 10V, 10%, 0603 AVX 0603ZD475KAT

10 0 C20, C28, C32 CAP, DNI, 0402 OPT

11 0 D1 DIODE, DNI, SOT-23 OPT

12 1 J9 CONNECTOR, FMC MEZZAININE SAMTEC ASP-134606-01

13 2 J6, J8 CONN, SMA 50Ω PC MOUNT, FEMALE AMPHENOL 132134

14 10 J1 to J5, J10,

J11, J12, J13, J14

HEADER, 3 × 1, 2mm SAMTEC TMM-103-02-L-S

15 1 J15 HEADER, 2 × 25, 2mm SAMTEC SQT-125-01-F-D

16 1 J7 HEADER, 2 × 7, 2mm MOLEX 87831-1421

17 0 L4 IND, DNI, 0603 OPT

18 1 R69 RES, 0Ω JUMPER, 0603 VISHAY CRCW06030000Z0ED

19 3 R70, R71, R72 RES, 0Ω JUMPER, 0805 VISHAY CRCW08050000Z0ED

20 3 L1, L2, L3 IND, BEAD, 1206 MURATA BL31PG330SN1L

21 11 R2, R4, R5, R6, R9, R10, R11,

R61 to R64

RES, 1k, 1%, 1/16W, 0402 PANASONIC ERJ-2RKF1001X

22 1 R3 RES, 31.6k, 1%, 1/16W, 0402 PANASONIC ERJ-2RKF3162X

23 8 R39 to R46 RES, 33k, 1%, 1/16, 0402 PANASONIC ERJ-2RKF3302X

24 1 R7 RES, 1.74k, 1%, 1/16W, 0402 PANASONIC ERJ-2RKF1741X

25 4 R65, R66, R67, R68 RES, 33.0, 1%, 1/16W, 0402 PANASONIC ERJ-2RKF33R0X

26 4 R1, R31, R32, R33 RES, 10k, 1%, 1/16, 0402 PANASONIC ERJ-2RKF1002X

27 0 R12 to R15, R17, R21, R23 to R26,

R48 to R56, R60

RES, DNI, 0402 OPT

28 14 C22, C29, R16, R18, R22, R29,

R34, R36, R37, R38, R47, R57,

R58, R59

RES, 0Ω JUMPER, 0402 VISHAY CRCW04020000Z0ED

29 2 R19, R20 RES, 49.9, 1%, 1/16, 0402 PANASONIC ERJ-2RKF49R9X

30 5 R8, R27, R28, R30, R35 RES, 100, 1%, 1/16, 0402 PANASONIC ERJ-2RKF1000X

31 5 TP1, TP2, TP3, TP4, TP5 TURRET, 0.093 MILL MAX 2501-2-00-80-00-00-07-0

32 1 U1 IC, VREG, 1.8V, 500MA, SO8 LINEAR TECHNOLOGY LT1763CS8-1.8

PARTS LIST

dc1732f

DEMO MANUAL DC1732

PARTS LIST

ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER

33 1 U2 MODULE, LTM9012 LINEAR TECHNOLOGY LTM9012-AB

34 1 U4 IC, SERIAL_EEPROM, TSSOP8 MICROCHIP 24LC32-IST

35 1 U3 IC, VREG, ADJ, 500MA, SO8 LINEAR TECHNOLOGY LT1763CS8

36 1 STENCIL SET STENCIL DC1732B

37 1 FAB, PCB, DC1732B DEMO CIRCUIT DC1732B

dc1732f

DEMO MANUAL DC1732

D D

C C

B B

A A

2 LANE

GND

PAR/SER

SHDN

RUN

SHDN

LANE

V+

GND

EXT REF

5V - 6V

1.75mA

DIS

PAR

ILVDS

SER

3.5mA

1 LANE

V+

TERM

3V - 6V

CLK+

CLK-

SHDN1

SHDN

RUN RUN

SHDN2

SHDN SHDN

SHDN3

RUN

SHDN4

RUN

SHDN

DO NOT STUFF

DO NOT STUFF DO NOT STUFF DO NOT STUFF

<Doc> E1

LTM9012 DEMO BOARD

11Wednesday, February 16, 2011

Title

Size Document Number Rev

Date: Sheet of

MOSI

CS0

MISO

PAR/SER

SCK

CS0

3.3_AUX

MOSI

MISO

SCK

PAR/SER

VREF

MISO

SCK

CS0

CLK-

CLK+

SENSE

AIN4+

AIN4-

AIN3+

AIN3-

AIN2+

AIN2-

AIN1+

AIN1-

MOSI

CLK+

CLK-

DCO-

DCO+

SHDN3

SHDN2

OUT2B+

OUT2B-

FR+

FR-

OUT3A+

OUT3A-

SHDN4

SHDN1

OUT1A-

OUT1A+

OUT4A-

OUT4A+

OUT3B+

OUT3B-

VREF

SENSE

OUT4B+

OUT4B-

OUT1B-

OUT1B+

OUT2A+

OUT2A-

SHDN1 SHDN2 SHDN3 SHDN4

VCC1

OVDD1

VDD1

VDD

OVDD1

VDD

OVDD

VDD

VDD VD D VDD VDD

VCC

VDD1

1uF

C12

1uF

R71

R21

opt

R67 33

C28

opt

1.00K

TP3

R63

OPT

SCK/SCL

GND

EEVCC

EEGND

VUNREG

GND

MISO

MOSI/SDA

EESDA

EESCL

GND

TP4

C25

0.1uF

TP2

R68 33

R22

R16

R70

2.00K

TP5

J14

R62

C22 0

C32

opt

100uF

R14

OPT

BEAD

OPT

0.1uF

LTM9012

B10

B11

B12

B13

A10

A11

A12

A13

C10

C11

C12

C13

D10

D11

D12

D13

E10

E11

E12

E13

F10

F11

F12

F13

G10

G11

G12

G13

H10

H11

H12

H13

J10

J11

J12

J13

K10

K11

K12

K13

L10

L11

L12

L13

M10

M11

M12

M13

N10

N11

N12

N13

P10

P11

P12

P13

Q10

Q11

Q12

Q13

R10

R11

R12

R13

S10

S11

S12

S13

GND

CH4+

CH4-

GND

CH3+

CH3-

GND

CH2+

CH2-

GND

CH1+

CH1-

GND

VCC3A

GND

VCC3B

GND

VCC2A

GND

VCC2B

GND

SHDN3

GND

SHDN2

GND

SHDN4

GND

SHDN1

GND

VCC4A

GND

VCC4B

GND

VCC1A

GND

VCC1B

GND

CLK+

GND

VDD

GND

VDD

SENSE

GND

CLK-

GND

SDI

CSB

SCK

GND

SDO

PAR/SER

VREF

GND

04BN

04BP

GND

01AN

01AP

GND

04AN

04AP

03BN

03BP

OGND

OVDD

02AN

02AP

01BN

O1BP

GND

03AN

03AP

FRN

FRP

OGND

OVDD

DCON

DCOP

02BN

02BP

GND

OPT

C21

0.01uF

R25

OPT

R10

1K C31

0.01uF

TP8

VDD FEED TO ADC ONLY

R12

opt

1uF

C23

0.1uF

J13

opt

J12

100

31.6K

R15

opt

C11

1uF

R17

opt

R72

R13

OPT

C20

OPT

R26

OPT

C13

1uF

MABA-007159-000000

4 3

10K

R19

49.9

R23

opt

C24

0.1uF

C10

4.7uF

TP6

VCC FEED TO ADC ONLY

R18

R61

2.2uF

C14

100uF

R20

49.9

LT1763CS8-1.8

8OUT

SEN/ADJ

GND

BYP

SHDN

GND

IN R4

R24

opt

LT1763CS8

8OUT

SEN/ADJ

GND

BYP

SHDN

GND

BEAD

R65 33

R11

OPT

C30

0.01uF

R60

DNS

1uF

0.1uF

opt

TP7

OVDD FEED TO ADC ONLY

4.7uF

R66 33

C27

0.1uF

OPT

R64

J11

C26

0.1uF

R69

BEAD

TP1

C29 0

SCHEMATIC DIAGRAM

dc1732f

DEMO MANUAL DC1732

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

SCHEMATIC DIAGRAM

D D

C C

B B

A A

CHANNEL 1

CHANNEL 2

CHANNEL 3

CHANNEL 4

FRAME

CLOCK DATA

CLOCK

DIS

Wednesday, February 16, 2011

LTM9012 Demo Board

ANTONINA

D. STUETZLE

LTM9012

SIZE

DATE:

IC NO. REV

SHEET OF

TITLE:

CONTRACT NO.

APPROVALS

PCB DES.

ENG.

TECHNOLOGY

Fax: (408)434-0507

Milpitas, CA 95035

Phone: (408)432-1900

1630 McCarthy Blvd.

LTC Confidential-For Customer Use Only

CUSTOMER NOTICE

LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A

CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;

HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO

VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL

APPLICATION. COMPONENT SUBSTITUTION AND PRINTED

CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT

PERFORMANCE OR RELIABILITY. CONTACT LINEAR

TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.

THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND

SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.

SCHEMATIC

AIN3 -

MISO

OUT1 A-

OUT3 B+

SCK

OUT4 A+

OUT4 B+

OUT1 B-

AIN4 -

CS0

AIN3 +

OUT3 B-

OUT2 B+

MOSI

OUT1 A+

OUT2 A+

FR+

DCO+

AIN2 -

OUT3 A-

OUT3 A+

OUT2 B-

FR-

OUT1 B+

3.3_AUX

DCO-

AIN2 +

OUT2 A-

OUT4 B-

AIN4 +

OUT4 A-

AIN1 -

AIN1 +

IN1+

IN1-

IN2-

IN2+

IN3-

IN3+

IN4+

IN4-

IN4+

IN4-

IN3+

IN3-

IN2+

IN2-

IN1-

IN1+

VDD

3.3_AUX

C35

0.01uF

R43

33K

R46

33K

R28 100

R51

opt

J9A

SEAM-10X40PIN

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

A32

A33

A34

A35

A36

A37

A38

A39

A40

GND

DP1_M2C_P

DP1_M2C_N

GND

DP2_M2C_P

DP2_M2C_N

GND

DP3_M2C_P

DP3_M2C_N

GND

DP4_M2C_P

DP4_M2C_N

GND

DP5_M2C_P

DP5_M2C_N

GND

DP1_C2M_P

DP1_C2M_N

GND

DP2_C2M_P

DP2_C2M_N

GND

DP3_C2M_P

DP3_C2M_N

GND

DP4_C2M_P

DP4_C2M_N

GND

DP5_C2M_P

DP5_C2M_N

GND

J9G

SEAM-10X40PIN

G10

G11

G12

G13

G14

G15

G16

G17

G18

G19

G20

G21

G22

G23

G24

G25

G26

G27

G28

G29

G30

G31

G32

G33

G34

G35

G36

G37

G38

G39

G40

GND

CLK0_C2M_P

CLK0_C2M_N

GND

LA00_P_CC

LA00_N_CC

GND

LA03_P

LA03_N

GND

LA08_P

LA08_N

GND

LA12_P

LA12_N

GND

LA16_P

LA16_N

GND

LA20_P

LA20_N

GND

LA22_P

LA22_N

GND

LA25_P

LA25_N

GND

LA29_P

LA29_N

GND

LA31_P

LA31_N

GND

LA33_P

LA33_N

GND

VADJ

GND

C36

0.1uF

R29 0

24LC32-IST

VSS

SDA

SCL

VCC

R47 0

C40

0.01uF

R45

33K

R35

100

C37

0.01uF

R42

33K

R32

10K

J9C

SEAM-10X40PIN

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

C27

C28

C29

C30

C31

C32

C33

C34

C35

C36

C37

C38

C39

C40

GND

DP0_C2M_P

DP0_C2M_N

GND

DP0_M2C_P

DP0_M2C_N

GND

LA06_P

LA06_N

GND

LA10_P

LA10_N

GND

LA14_P

LA14_N

GND

LA18_P_CC

LA18_N_CC

GND

LA27_P

LA27_N

GND

SCL

SDA

GND

GA0

12P0V

GND

12P0V

GND

3P3V

GND

R50

opt

J9K

SEAM-10X40PIN

K10

K11

K12

K13

K14

K15

K16

K17

K18

K19

K20

K21

K22

K23

K24

K25

K26

K27

K28

K29

K30

K31

K32

K33

K34

K35

K36

K37

K38

K39

K40

VREF_B_M2C

GND

CLK1_M2C_P

CLK1_M2C_N

GND

HA02_P

HA02_N

GND

HA06_P

HA06_N

GND

HA10_P

HA10_N

GND

HA17_P_CC

HA17_N_CC

GND

HA21_P

HA21_N

GND

HA23_P

HA23_N

GND

HB00_P_CC

HB00_N_CC

GND

HB06_P_CC

HB06_N_CC

GND

HB10_P

HB10_N

GND

HB14_P

HB14_N

GND

HB17_P_CC

HB17_N_CC

GND

VIO_B_M2C

R48

opt

J15

HEADER 25X2

MOLE X25X2

J9F

SEAM-10X40PIN

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

F21

F22

F23

F24

F25

F26

F27

F28

F29

F30

F31

F32

F33

F34

F35

F36

F37

F38

F39

F40

PG_M2C

GND

HA00_P_CC

HA00_N_CC

GND

HA04_P

HA04_N

GND

HA08_P

HA08_N

GND

HA12_P

HA12_N

GND

HA15_P

HA15_N

GND

HA19_P

HA19_N

GND

HB02_P

HB02_N

GND

HB04_P

HB04_N

GND

HB08_P

HB08_N

GND

HB12_P

HB12_N

GND

HB16_P

HB16_N

GND

HB19_P

HB19_N

GND

VADJ

R41

33K

R39

33K

R56

opt

R36 0

R33

10K

R38

R54

opt

J9B

SEAM-10X40PIN

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

B31

B32

B33

B34

B35

B36

B37

B38

B39

B40

RES1

GND

DP9_M2C_P

DP9_M2C_N

GND

DP8_M2C_P

DP8_M2C_N

GND

DP7_M2C_P

DP7_M2C_N

GND

DP6_M2C_P

DP6_M2C_N

GND

GBTCLK1_M2C_P

GBTCLK1_M2C_N

GND

DP9_C2M_P

DP9_C2M_N

GND

DP8_C2M_P

DP8_C2M_N

GND

DP7_C2M_P

DP7_C2M_N

GND

DP6_C2M_P

DP6_C2M_N

GND

RES0

C33

0.01uF

R55

opt

C41

0.01uF

J9J

SEAM-10X40PIN

J10

J11

J12

J13

J14

J15

J16

J17

J18

J19

J20

J21

J22

J23

J24

J25

J26

J27

J28

J29

J30

J31

J32

J33

J34

J35

J36

J37

J38

J39

J40

GND

CLK1_C2M_P

CLK1_C2M_N

GND

HA03_P

HA03_N

GND

HA07_P

HA07_N

GND

HA11_P

HA11_N

GND

HA14_P

HA14_N

GND

HA18_P

HA18_N

GND

HA22_P

HA22_N

GND

HB01_P

HB01_N

GND

PB07_P

HB07_N

GND

HB11_P

HB11_N

GND

HB15_P

HB15_N

GND

HB18_P

HB18_N

GND

VIO_B_M2C

GND

J10

R40

33K

R57 0

R31

10K

C34

0.01uF

R27 100

J9E

SEAM-10X40PIN

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

E22

E23

E24

E25

E26

E27

E28

E29

E30

E31

E32

E33

E34

E35

E36

E37

E38

E39

E40

GND

HA01_P_CC

HA01_N_CC

GND

HA05_P

HA05_N

GND

HA09_P

HA09_N

GND

HA13_P

HA13_N

GND

HA16_P

HA16_N

GND

HA20_P

HA20_N

GND

HB03_P

HB03_N

GND

HB05_P

HB05_N

GND

HB09_P

HB09_N

GND

HB13_P

HB13_N

GND

HB21_P

HB21_N

GND

HB20_P

HB20_N

GND

VADJ

GND

R53

opt

R58 0

R49

opt

R59 0

C39

0.01uF

R44

33K

J9H

SEAM-10X40PIN

H10

H11

H12

H13

H14

H15

H16

H17

H18

H19

H20

H21

H22

H23

H24

H25

H26

H27

H28

H29

H30

H31

H32

H33

H34

H35

H36

H37

H38

H39

H40

VREF_A_M2C

PRSNT_M2C_N

GND

CLK0_M2C_P

CLK0_M2C_N

GND

LA02_P

LA02_N

GND

LA04_P

LA04_N

GND

LA07_P

LA07_N

GND

LA11_P

LA11_N

GND

LA15_P

LA15_N

GND

LA19_P

LA19_N

GND

LA21_P

LA21_N

GND

LA24_P

LA24_N

GND

LA28_P

LA28_N

GND

LA30_P

LA30_N

GND

LA32_P

LA32_N

GND

VADJ

R37 0

R30

100

R52

opt

R34 0

J9D

SEAM-10X40PIN

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

D31

D32

D33

D34

D35

D36

D37

D38

D39

D40

PG_C2M

GND

GBTCLK0_M2C_P

GBTCLK0_M2C_N

GND

LA01_P_CC

LA01_N_CC

GND

LA05_P

LA05_N

GND

LA09_P

LA09_N

GND

LA13_P

LA13_N

GND

LA17_P_CC

LA17_N_CC

GND

LA23_P

LA23_N

GND

LA26_P

LA26_N

GND

TCK

TDI

TDO

3P3VAUX

TMS

TRST_N

GA1

3P3V

GND

3P3V

GND

3P3V

C38

0.01uF

dc1732f

DEMO MANUAL DC1732

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ●FAX: (408) 434-0507 ●www.linear.com

 LINEAR TECHNOLOGY CORPORATION 2011

LT 1111 • PRINTED IN USA

DEMONSTRATION BOARD IMPORTANT NOTICE

Linear Technology Corporation (LTC) provides the enclosed product(s) under the following AS IS conditions:

This demonstration board (DEMO BOARD) kit being sold or provided by Linear Technology is intended for use for ENGINEERING DEVELOPMENT

OR EVALUATION PURPOSES ONLY and is not provided by LTC for commercial use. As such, the DEMO BOARD herein may not be complete

in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety

measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union

directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations.

If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 30 days from the date

of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU

OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS

FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR

ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.

The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user releases LTC from all claims

arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all

appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or

agency certified (FCC, UL, CE, etc.).

No License is granted under any patent right or other intellectual property whatsoever. LTC assumes no liability for applications assistance,

customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.

LTC currently services a variety of customers for products around the world, and therefore this transaction is not exclusive.

Please read the DEMO BOARD manual prior to handling the product. Persons handling this product must have electronics training and

observe good laboratory practice standards. Common sense is encouraged.

This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a LTC applica-

tion engineer.

Mailing Address:

Linear Technology

1630 McCarthy Blvd.

Milpitas, CA 95035

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