Intersil ISL282x6EVAL1Z User manual
1
®
AN1420.0
ISL282x6EVAL1Z Evaluation Board User’s Guide
Introduction
The ISL282x6EVAL1Z evaluation board is a design platform
containing all the circuitry needed to characterize critical
performance parameters of the ISL282x6 operational
amplifiers in both MSOP-8 and SOIC-8 packages, using a
variety of user defined test circuits.
The ISL28236 and ISL28246 high-speed operational
amplifiers feature low power consumption, while ISL28256
and ISL28266 operational amplifiers feature ultra-low power
consumption. All op amps have rail-to-rail output drive
capability and are designed to operate with a single lithium
cell or two Ni_Cd batteries.
Reference Documents
• ISL28236 Data Sheet
• ISL28246 Data Sheet
• ISL28256 Data Sheet
• ISL28266 Data Sheet
Evaluation Board Key Features
The ISL282x6EVAL1Z is designed to enable the IC to
operate from a single supply, +2.4VDC to +5.5VDC or from
split supplies, ±1.2VDC to ±2.75V. The board is configured
for a dual op amp connected for differential input with a
closed loop gain of 10. A single external reference voltage
(VREF) pin and provisions for a user-selectable voltage
divider - filter are included.
Power Supplies (Figure 1)
External power connections are made through the +V, -V,
VREF and Ground connections on the evaluation board.
User selectable SMA edge connectors are also provided for
+V and -V. For single supply operation, the -V and Ground
pins are tied together to the power supply negative terminal.
For split supplies, +V and -V terminals connect to their
respective power supply terminals. De-coupling capacitors
C2and C4connect to their respective supplies through R16
and R31 0Ωresistors. These resistors are 0Ωbut can be
changed by the user to provide additional power supply
filtering, or to reduce the voltage rate-of-rise to less than
±1V/µs. Two additional capacitors, C3and C5are connected
close to the part to filter out high frequency noise.
Anti-reverse diode D1protects the circuit in the case of
accidental polarity reversal.
Amplifier Configuration (Figure 2)
The schematic of 1/2 of the op amp with the components
supplied is shown in Figure 2. The circuit implements a
differential input amp with a closed loop gain of 10. The
circuit can operate from a single supply or from dual
supplies. The VREF pin must be connected to ground to
J11
C5
R31
R16
D1
C2 C4
C3
J14
J12 J13
J6
J8
0.01µF0.01µF
4.7µF4.7µF
0
0
VREF
V+V-
FIGURE 1. POWER SUPPLY CIRCUIT
IN-
IN+
RF
VREF
IN -
IN +
GND
100k
Ω
R
REF
+
VOUT
ISL282x6 (1/2)
VP
V-
0
Ω
VM
VCM
IN-
IN+
VREF
V+
R
IN
-
10k
Ω
R
IN
+
10k
Ω
-
+
100k
Ω
RL
10k
Ω
FIGURE 2. BASIC AMPLIFIER CONFIGURATION
Application Note August 28, 2008
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2AN1420.0
August 28, 2008
establish a ground referenced input for dual supply
operation, or can be externally set to any reference level for
single supply operation. VREF should not be left floating.
User-selectable Options (Figures 3 and 4)
Component pads are included to enable a variety of
user-selectable circuits to be added to the amplifier VREF,
inputs, outputs, and the amplifier feedback loops. The inputs
(Figure 3) have additional resistor and capacitor, and jumper
placements for loading and/or measurement of frequency
sensitive parameters.
The outputs (see Figure 4) have a 10kΩload resistor to
ground and have additional resistor and capacitor
placements for loading.
Note: Operational amplifiers are sensitive to output
capacitance and may oscillate. In the event of oscillation,
reduce output capacitance by using shorter cables or add a
resistor in series with the output.
FIGURE 3. INPUT STAGE (1/2) FIGURE 4. OUTPUT STAGE (1/2)
IN- OUTNODEIN+
C1
R5
R4
J2
J1 R1
R6
R17
R2 R14
R3
R18R15
R12R10
R13R11
DNP DNP
DNP
DNP
DNP
DNP
DNP
OPEN
DNP
DNP
10k 100k
100k
10k
0
VREF
TO OUTPUT
TO IN+
TO IN-
R26
C6
C8
R28
10k
OPEN
OPEN
0
FROM OUTPUT
Application Note 1420
3AN1420.0
August 28, 2008
ISL282x6EVAL1Z Components Parts List
DEVICE # DESCRIPTION COMMENTS
C2, C4 CAP-TANTALUM, SMD, D, 4.7µF, 50V, 10%, LOW ESR, ROHS Power supply decoupling
C3, C5 CAP, SMD, 0603, 0.1µF, 25V, 10%, X7R, ROHS Power supply decoupling
C1, C6 thru C10 CAP, SMD, 0603, DNP-PLACE HOLDER, ROHS User-selectable capacitors - not
populated
D1 DIODE-SCHOTTKY BARRIER, SMD, SOT-23, 3P, 40V, ROHS Reverse power protection
U1 (ISL28236FUZ) IC-5 MHz RRIO OP AMP, 8P, MSOP, ROHS
U1 (ISL28236FBZ) IC-5 MHz RRIO OP AMP, 8P, SOIC, ROHS
U1 (ISL28246FUZ) IC-5 MHz RRIO OP AMP, 8P, MSOP, ROHS
U1 (ISL28246FBZ) IC-5 MHz RRIO OP AMP, 8P, SOIC, ROHS
U1 (ISL28256FUZ) IC-39µA RRIO OP AMP, 8P, MSOP, ROHS
U1 (ISL28256FBZ) IC-39µA RRIO OP AMP, 8P, SOIC, ROHS
U1 (ISL28266FUZ) IC-39µA RRIO OP AMP, 8P, MSOP, ROHS
U1 (ISL28266FBZ) IC-39µA RRIO OP AMP, 8P, SOIC, ROHS
R30, R32, R34 thru R36 RESISTOR, SMD, 0603, 0.1%, MF, DNP-PLACE HOLDER User selectable resistors - not
populated
R4, R16, R25 thru R27, R31 RES, SMD, 0603, 0Ω, 1/10W,TF, ROHS 0Ω user selectable resistors
R11, R14, R21, R24, R28, R29 RES, SMD, 0603, 10k, 1/10W, 1%, TF, ROHS Gain and other user selectable
resistors
R13, R18, R19, R23 RES, SMD, 0603, 100k, 1/10W, 1%, TF, ROHS Gain resistors
Application Note 1420
4AN1420.0
August 28, 2008
Application Note 1420
FIGURE 5. ISL282x6EVAL1Z TOP VIEW (SOIC SHOWN)
5
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to
verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
AN1420.0
August 28, 2008
Application Note 1420
ISL282x6EVAL1Z Schematic Diagram
NODEBIN-A IN+BOUTANODEA IN-BOUTBIN+A
J11
C5
R31
R16
R36
R32 R34
R35
R30
32
1
D1
R20
C10
R8
R7
R5
R4 R24
C2 C4
C3
J15
J16
J2
J1
J3
J4
J14
J12
J13
J6
J8
R26
R27
C7
C6
C8C9
R1
R29
R25
R23
R6
R17
R2
R28
R3
R13R11
8
7
6
54
3
2
1U1
0.01µF0.01µF
4.7µF4.7µF
0
SOIC8
0
DNP
0
10k
OPEN
10k
OPEN
OPEN
OPEN
0
DNP
DNP
DNP
DNP
OPEN
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
OPEN
DNP
DNP
10k 10K100K 100k
100k 100k
10K 10k
0
0 DNP
VREF
VREF
V+V-
5
6
7
8
3
4
1
2
MSOP8
R15 R18 R19 R22
R21
R14
C1
R10 R12
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