Innovative Integration PC44 User manual
Innovative Integration
PC44 Hardware Manual
The PC44 Hardware Manual was prepared by the technical staff of Innovative Integration, Aug. ‘95.
Third Edition prepared June ‘96 (applies to Rev. E and later cards)
For further assistance contact
Innovative Integration
31352 W. Via Colinas #101
Westlake Village, California 91362
PH: (818) 865-6150
FAX: (818) 879-1770
email: techsprt@innovative-dsp.com
WWW: www.innovative-dsp.com
This document is copyright 1994, 1995, 1996 by Innovative Integration. All rights are reserved.
IBM PC, AT and PS/2 are registered trademarks of
International Business Machines
Windows is a registered trademark of Microsoft Corporation
file: \\p60\c\winword\manuals\pc44\hardware\pc44hdw3.doc
#51022 rev – 3.00
Table of Contents
1. PC44 Hardware Functions.................................................................. 1
1.1 PC44 Bus Interface...................................................................................................................... 1
1.2 PC44 Memory.............................................................................................................................. 3
1.2.1 PC44 Local Memory............................................................................................................. 3
1.2.2 Local Boot FLASH Memory................................................................................................ 3
1.2.3 Local SRAM Memory........................................................................................................... 4
1.2.4 PC44 Global Memory........................................................................................................... 4
1.2.4.1 Global Arbitration............................................................................................................ 4
1.2.4.2 Global Peripheral Region.................................................................................................4
1.2.5 Wait States............................................................................................................................. 6
1.2.6 Memory Options ................................................................................................................... 7
1.2.7 Dual Port Memory................................................................................................................ 8
1.2.7.1 Dual Port Semaphores...................................................................................................... 9
1.2.8 PC44 Boot PROM............................................................................................................... 10
1.3 Processor Interrupts.................................................................................................................. 11
1.3.1 Interrupt Combinations...................................................................................................... 11
1.3.2 Interrupt Types................................................................................................................... 11
1.3.3 Interrupt Selection.............................................................................................................. 13
1.4 TIM40 Expansion Sites............................................................................................................. 15
1.4.1 TIM40 Comm Port Interconnections................................................................................ 15
1.4.2 TIM Site JTAG Considerations......................................................................................... 16
1.5 Peripherals ................................................................................................................................. 18
1.5.1 External Memory Mapped Peripherals ............................................................................ 18
1.5.2 Timer Source Selection....................................................................................................... 20
1.5.3 The Parallel I/O Ports......................................................................................................... 20
1.5.3.1 Digital Connections......................................................................................................... 21
1.5.4 The 82C54 Counter/Timers................................................................................................ 21
1.5.5 Analog I/O ........................................................................................................................... 22
1.5.6 Analog Input........................................................................................................................ 23
1.5.6.1 PC44 A/D Register Set....................................................................................................25
1.5.6.2 A/D Conversion Triggering............................................................................................ 26
1.5.6.3 A/D Channel Calibration................................................................................................ 27
1.5.6.4 Input Range Control....................................................................................................... 27
1.5.6.5 Single-Ended/Differential Inputs................................................................................... 28
1.5.6.6 Analog Multiplexer......................................................................................................... 29
1.5.6.7 MUX Software Cautions................................................................................................ 31
1.5.6.8 Programmable Gain Amplifiers..................................................................................... 32
1.5.6.9 Anti-alias Filtering ..........................................................................................................32
1.5.7 Analog Output.....................................................................................................................35
1.5.7.1 D/A Converter Output Ranges.......................................................................................35
1.5.7.2 D/A Output Trimming....................................................................................................36
1.5.7.3 D/A Output Amplification and Filtering.......................................................................36
1.5.7.4 D/A Converter Control Registers (Software Conversion Triggering)........................36
1.5.7.5 D/A Hardware Conversion Triggering..........................................................................37
1.5.8 Analog Output Bits (ABITS)..............................................................................................38
1.5.9 Analog Power Supplies.......................................................................................................38
2. Appendices...........................................................................................39
2.1 Factory Jumper Settings ...........................................................................................................39
2.2 Connector Pinouts......................................................................................................................40
2.3 Component Data Sheets.............................................................................................................44
List of Figures
Figure 1: PC44 Memory Map...................................................................................................................... 5
Figure 2: PC44 Communication Port Connections.................................................................................. 15
Figure 3: JTAG Connections and Shorting Jumper Functionality........................................................ 17
Figure 4: PC44 Multiboard Installation................................................................................................... 17
Figure 5: Block Diagram of Analog Inputs .............................................................................................. 24
Figure 6: MUX Channel Input Diagram .................................................................................................. 30
Figure 7: Anti-alias Filter Frequency Response....................................................................................... 33
Figure 8: Anti-aliasing Filter Schematic................................................................................................... 34
Figure 9: JP7 - Digital I/O, External Clocks, and External Interrupts.................................................. 41
Figure 10: P1 - External Analog I/O and Power Supplies....................................................................... 42
Figure 11: JP31-36 - Processor Communication Port Headers.............................................................. 43
List of Tables
Table 1: I/O Mapped PC Bus Registers...................................................................................................... 1
Table 2: Processor Interrupt Types and Reception Compatibility......................................................... 11
Table 3: Processor A Interrupt Selector................................................................................................... 13
Table 4: Processor B Interrupt Selector................................................................................................... 13
Table 5: Processor C Interrupt Selector................................................................................................... 14
Table 6: Comm Port Jumper Direction Settings...................................................................................... 16
Table 7: PC44 External Peripheral Memory Map ................................................................................. 18
Table 8: Timer Source 0 Selection Jumpers............................................................................................. 20
Table 9: Timer Source 1 Selection Jumpers............................................................................................. 20
Table 10: JP5 Digital I/O Port Direction Jumper Settings...................................................................... 21
Table 11: JP4 Digital I/O Port Readback Clock Jumper Settings.......................................................... 21
Table 12: 82C54 Register Locations.......................................................................................................... 22
Table 13: 82C54 Clock Sources................................................................................................................. 22
Table 14: A/D Control Registers ............................................................................................................... 25
Table 15: A/D Conversion Trigger Selection Jumper.............................................................................. 26
Table 16:A/D Input Range Jumper Settings ............................................................................................ 27
Table 17: ADC Multiplexer Options......................................................................................................... 28
Table 18: JP17 Settings (A/D Channel A)................................................................................................. 28
Table 19: JP16 Settings (A/D Channel B)................................................................................................. 28
Table 20: MUX Channel A Selector Values ............................................................................................. 31
Table 21: MUX Channel B Selector Values ............................................................................................. 31
Table 22: Channel A Gain Selection ......................................................................................................... 32
Table 23: Channel B Gain Selection.......................................................................................................... 32
Table 24: DAC0 Output Range Selection................................................................................................. 35
Table 25: DAC1 Output Range Selection................................................................................................. 35
Table 26: DAC2 Output Range Selection................................................................................................. 35
Table 27: DAC3 Output Range Selection................................................................................................. 35
Table 28: DAC Output Range Adjustment Amplifier Resistors and Filtering Capacitors, with
Factory Defaults ................................................................................................................................ 36
Table 29: D/A Software Update Registers................................................................................................ 37
Table 30: D/A Update Trigger Selection................................................................................................... 37
Table 31: Analog Power Supply Current Limits ..................................................................................... 38
Table 32: JP7 - Pin Description................................................................................................................. 41
Table 33: P1 - Pin Description................................................................................................................... 42
Table 34: JP31-36 Pin Description............................................................................................................ 43
PC44 Hardware Manual - 1
1. PC44 Hardware Functions
The PC44 single board computer is built around the Texas Instruments TMS320C44 digital signal
processor capable of up to 200 MOPS (50 MHz clock) sustained performance. The major subsections of
the board are the bus interface, memory, I/O ports and analog I/O.
1.1 PC44 Bus Interface
The PC44 is mapped into the I/O and memory space of the IBM AT. The PC44 supports 16-bit and 32-bit
accesses only - no eight bit accesses are supported. The 32-bit operations on the PC bus allow easy use
with newer 32-bit protected mode PC software.
The PC44 is mapped into the I/O space of the IBM-AT and consumes 32 contiguous bytes of conventional
I/O space located on an even 32-bit boundary within the I/O map. Within this I/O region lie three 16-bit
registers which are manipulated to control the PC44, as well as eight 32-bit semaphore registers available to
development and user software. The I/O register map is described in the following table. References to
BASE below refer to the I/O address into which you mapped the PC44 in your system during installation
(default 0x280).
Table 1: I/O Mapped PC Bus Registers
I/O Address Bit Direction Function
Control Register
Base + 0x800 0 Write only Reset to PC44
1=reset 0=run
1 Write only Enable dual port accesses
1=enable 0=disable
2 Read Only Config readback
1=all processors booted
0=at least one processor still
booting
Interrupt 0
Base + 0x802 - Read/Write Cause PC Int0 to PC44
(access to cause interrupt pulse)
Interrupt 1
Base + 0x804 - Read/Write Cause PC Int1 to PC44
(access to cause interrupt pulse)
Interrupt 2
Base + 0x806 - Read/Write Cause PC Int2 to PC44
(access to cause interrupt pulse)
Dual Port Semaphores
0 Base + 0x0 16-bit Read/ Write 0x0000 = resource captured
0xFFFF = resource busy
1 Base + 0x4 16-bit Read/ Write 0x0000 = resource captured
0xFFFF = resource busy
2 Base + 0x8 16-bit Read/ Write 0x0000 = resource captured
0xFFFF = resource busy
PC44 Hardware Manual - 2
3 Base + 0xC 16-bit Read/ Write 0x0000 = resource captured
0xFFFF = resource busy
4 Base + 0x10 16-bit Read/ Write 0x0000 = resource captured
0xFFFF = resource busy
5 Base + 0x14 16-bit Read/ Write 0x0000 = resource captured
0xFFFF = resource busy
6 Base + 0x18 16-bit Read/ Write 0x0000 = resource captured
0xFFFF = resource busy
7 Base + 0x1C 16-bit Read/ Write 0x0000 = resource captured
0xFFFF = resource busy
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