CDB5471
10 DS480DB1
The user should recall from CS5471 Data Sheet
that the serial interface on the CS5471 device is a
“master-mode” interface, which means that the de-
vice provides the clock. Once the CS5471 is pow-
ered on, the SCLK pin produces a clock signal, and
data is sent out on the SDO pin of the device. When
the evaluation software is instructed (by the user) to
acquire data through the parallel interface, a two-
step process is performed: First the software syn-
chronizes itself to the frame rate of the CS5471,
then the software acquires multiple frames of data
from the CS5471.
2.3.7.1. Synchronization
When the software is commanded to acquire data,
the software will first synchronize itself to the
frame rate of the CS5471 (see CS5471 Data Sheet).
This is done by measuring the amount of time be-
tween rising and falling edges of the “BUSY” sig-
nal. (BUSY will change state every time the
CS5471 issues eight SCLKs--See next section for a
more detailed description.) By measuring this time
period, the software can determine the idle period
of the frame, which allows it to be prepared to col-
lect a complete frame’s worth of data when the next
CS5471 frame is received. This acquisition se-
quence is described next.
2.3.7.2. Acquisition
Referring to Figure 3, the CS5471’s SCLK line is
used to clock the 8-bit serial-in/parallel-out shift-
register (U7) which accepts the serial data on SDO
and shifts it into the 8 output bits QA-QG. The
SCLK signal is also fed into the up/down counter
U6 and after every 8 SCLKs, the “QC” pin of U6
will latch the QA-QG output bits of U6 into the 8-
bit D-Flip-Flop (U3). While this is happening, the
software monitors the “BUSY” signal (from the
“QD” pin of U6). BUSY is the critical handshake
signal. A rising or falling transition on BUSY in-
dicates to the software that it is now time to collect
another byte of data from the latched output on U3.
After sixteen SCLKs, the PC software has acquired
two bytes (16 bits) which represents one data sam-
ple. The 4-bit up/down counter (U6) will roll over
after every 16 SCLKs. (Note that U6 is cleared by
the CS5471’s FSO signal at the beginning of each
frame, which insures that the counter begins the
frame in the correct state--cleared). This sequence,
which lasts for 16 SCLKs, is performed a total of
six times, although only the first two repetitions of
this sequence are relevant. In the first two sequenc-
es, the two 16-bit words from the CS5471 are ac-
quired by the PC. The data contained in the
remaining four sequence executions will be mean-
ingless, as the state of the CS5471’s SDO pin is be
undefined during the last 64 clocks of each data
frame.
After the sixth 16-bit word is acquired, the software
recognizes that the end of a data frame has been
reached, and it will continue to wait for the next
transition on the “BUSY” line. This will not occur
until the first 8 SCLKs of the next frame are sent
from the CS5471. Various other signals in Figure
3 (STRB, FEED, ACK, etc.) are not used during
data capture and are only used for testing (internal
use only).
2.3.8 Connecting the Eval Board to PC
The CDB5471 connects to the user’s IBM-compat-
ible PC with the included 25-pin parallel port cable.
The user should not connect this cable between
the CDB5471 and theparallel port on the PC until
all of the header options in Table 2 have been set
to appropriate settings and the user has applied
power to the CDB5471. The parallel cable at-
tached to the CDB5471 Evaluation Board at J17.
After connecting the parallel port cable between
the PC and CDB5471, the user should always actu-
ate (press down on) the “RESET” switch (S1) at
least one time before performing any other evalua-
tion activities.
