Atmel AVR ATtiny22 Instruction Manual

Features

•Utilizes the AVR®RISC Architecture

•AVR - High-performance and Low-power RISC Architecture

– 118 Powerful Instructions - Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Up to 8 MIPS Throughput at 8 MHz

•Data and Nonvolatile Program Memory

– 2K Bytes of In-System Programmable Flash

Endurance 1,000 Write/Erase Cycles

– 128 Bytes of internal SRAM

– 128 Bytes of In-System Programmable EEPROM

Endurance: 100,000 Write/Erase Cycles

– Programming Lock for Flash Program and EEPROM Data Security

•Peripheral Features

– One 8-bit Timer/Counter with Separate Prescaler

– Programmable Watchdog Timer with On-chip Oscillator

– SPI Serial Interface for In-System Programming

•Special Microcontroller Features

– Low-power Idle and Power Down Modes

– External and Internal Interrupt Sources

– Power-on Reset Circuit

– Selectable On-chip RC Oscillator

•Specifications

– Low-power, High-speed CMOS Process Technology

– Fully Static Operation

•Power Consumption at 4 MHz, 3V, 25°C

– Active: 2.4 mA

– Idle Mode: 0.5 mA

– Power Down Mode: <1 µA

•I/O and Packages

– 5 Programmable I/O Lines

– 8-pin PDIP and SOIC

•Operating Voltages

– 2.7 - 6.0V (ATtiny22L)

– 4.0 - 6.0V (ATtiny22)

•Speed Grades

– 0 - 4 MHz (ATtiny22L)

– 0 - 8 MHz (ATtiny22)

Description

The ATtiny22/L is a low-power CMOS 8-bit microcontrollers based on the AVR RISC

architecture. By executing powerful instructions in a single clock cycle, the ATtiny22/L

achieves throughputs approaching 1 MIPS per MHz allowing the system designer to

optimize power consumption versus processing speed.

Rev. 1273A–04/99

8-bit

Microcontroller

with 2K Bytes of

In-System

Programmable

Flash

ATtiny22

ATtiny22L

Preliminary

Pin Configuration PDIP/SOIC

RESET

(CLOCK) PB3

PB4

GND

VCC

PB2 (SCK/T0)

PB1 (MISO/INT0)

PB0 (MOSI)

2ATtiny22/22L

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly

connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction

executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times

faster than conventional CISC microcontrollers.

Block Diagram

Figure 1. The ATtiny22/L Block Diagram

PROGRAM

COUNTER

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

STACK

POINTER

PROGRAM

FLASH MCU CONTROL

SRAM

GENERAL

PURPOSE

REGISTERS

INSTRUCTION

COUNTER

INSTRUCTION

DECODER

DATA DIR.

REG. PORTB

DATA REGISTER

PORTB

PROGRAMMING

LOGIC

TIMING AND

CONTROL

INTERRUPT

UNIT

EEPROM

SPI

STATUS

ALU

PORTB DRIVERS

PB0 - PB4

RESET

VCC

GND

CONTROL

LINES

8-BIT DATA BUS

ATtiny22/22L

The ATtiny22/L provides the following features: 2K bytes of In-System Programmable Flash, 128 bytes EEPROM,

128 bytes SRAM, five general purpose I/O lines, 32 general purpose working registers, an 8-bit timer/counter, internal and

external interrupts, programmable Watchdog Timer with internal oscillator, an SPI serial port for Flash Memory download-

ing and two software selectable power saving modes. The Idle Mode stops the CPU while allowing the SRAM,

timer/counters, SPI port and interrupt system to continue functioning. The power down mode saves the register contents

but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset.

The device is manufactured using Atmel’s high density nonvolatile memory technology. The on-chip Flash allows the

program memory to be reprogrammed in-system through an SPI serial interface. By combining an 8-bit RISC CPU with ISP

Flash on a monolithic chip, the Atmel ATtiny22/L is a powerful microcontroller that provides a highly flexible and cost effec-

tive solution to many embedded control applications.

The ATtiny22/L AVR is supported with a full suite of program and system development tools including: C compilers, macro

assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.

Pin Descriptions ATtiny22/L

VCC

Supply voltage pin.

GND

Ground pin.

Port B (PB4..PB0)

Port B is a 5-bit bi-directional I/O port. Port pins can provide internal pull-up resistors (selected for each bit). When the

device is clocked from an external clock source, PB3 is used as the clock input. The port B pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

RESET

Reset input. An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate

a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.

CLOCK

Clock signal input in external clock mode.

Clock Options

External Clock

The ATtiny22/L can be clocked by an external clock signal, as shown in Figure 2, or by the on-chip RC oscillator. This RC

oscillator runs at a nominal frequency of 1 MHz (VCC = 5V). A fuse bit - RCEN - in the Flash memory selects the on-chip

RC oscillator as the clock source when programmed (“0”). The ATtiny22/L is shipped with this bit programmed.

4ATtiny22/22L

Figure 2. External Clock Drive Configuration

Architectural Overview

The fast-access register file concept contains 32 x 8-bit general purpose working registers with a single clock cycle access

time. This means that during one single clock cycle, one arithmetic logic unit (ALU) operation is executed. Two operands

are output from the register file, the operation is executed, and the result is stored back in the register file in one clock

cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing enabling

efficient address calculations. One of the three address pointers is also used as the address pointer for the constant table

look up function. These added function registers are the 16-bit X-register, Y-register and Z-register.

Figure 3. The ATtiny22/L AVR RISC Architecture

PB3

1K x 16

Program

Flash

Instruction

Decoder

Program

Counter

Control Lines

32 x 8

General

Purpose

Registers

ALU

Status

and Test Control

Registers

Interrupt

Unit

SPI

Unit

8-bit

Timer/Counter

Watchdog

Timer

I/O Lines

128 x 8

EEPROM

Data Bus 8-bit

AVR

ATtiny22/L Architecture

128 x 8

Data

SRAM

Direct Addressing

Indirect Addressing

ATtiny22/22L

The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register

operations are also executed in the ALU. Figure 3 shows the ATtiny22/L AVR RISC microcontroller architecture.

In addition to the register operation, the conventional memory addressing modes can be used on the register file as well.

This is enabled by the fact that the register file is assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing

them to be accessed as though they were ordinary memory locations.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, Timer/Counters,

A/D-converters, and other I/O functions. The I/O memory can be accessed directly, or as the Data Space locations follow-

ing those of the register file, $20 - $5F.

The AVR has Harvard architecture - with separate memories and buses for program and data. The program memory is

accessed with a two stage pipeline. While one instruction is being executed, the next instruction is pre-fetched from the

program memory. This concept enables instructions to be executed in every clock cycle. The program memory is in-system

downloadable Flash memory.

With the relative jump and call instructions, the whole 1K address space is directly accessed. Most AVR instructions have a

single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction.

During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is

effectively allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and

the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are

executed). The 8-bit stack pointer SP is read/write accessible in the I/O space.

The 128 bytes data SRAM + register file and I/O registers can be easily accessed through the five different addressing

modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

Figure 4. Memory Maps

EEPROM

(128 x 8)

$000

$07F

EEPROM Data Memory

6ATtiny22/22L

A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status

register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the

program memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the

interrupt vector address, the higher the priority.

General Purpose Register File

Figure 5 shows the structure of the 32 general purpose registers in the CPU.

Figure 5. AVR CPU General Purpose Working Registers

All the register operating instructions in the instruction set have direct and single cycle access to all registers. The only

exception is the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI, ORI between a constant and a

register and the LDI instruction for load immediate constant data. These instructions apply to the second half of the regis-

ters in the register file - R16..R31. The general SBC, SUB, CP, AND, OR and all other operations between two registers or

on a single register apply to the entire register file.

As shown in Figure 5, each register is also assigned a data memory address, mapping them directly into the first 32 loca-

tions of the user Data Space. Although the register file is not physically implemented as SRAM locations, this memory

organization provides great flexibility in access of the registers, as the X, Y and Z registers can be set to index any register

in the file.

7 0 Addr.

R0 $00

R1 $01

R2 $02

…

R13 $0D

General R14 $0E

Purpose R15 $0F

Working R16 $10

Registers R17 $11

…

R26 $1A X-register low byte

R27 $1B X-register high byte

R28 $1C Y-register low byte

R29 $1D Y-register high byte

R30 $1E Z-register low byte

R31 $1F Z-register high byte

ATtiny22/22L

X-Register, Y-Register, and Z-Register

The registers R26..R31 have some added functions to their general purpose usage. These registers are the address point-

ers for indirect addressing of the Data Space. The three indirect address registers X, Y and Z are defined as:

Figure 6. The X, Y, and Z Registers

In the different addressing modes these address registers have functions as fixed displacement, automatic increment and

decrement (see the descriptions for the different instructions).

ALU - Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a

single clock cycle, ALU operations between registers in the register file are executed. The ALU operations are divided into

three main categories - arithmetic, logic and bit-functions

In-System Programmable Flash Program Memory

The ATtiny22/L contains 2K bytes on-chip In-System Programmable Flash memory for program storage. Since all instruc-

tions are 16- or 32-bit words, the Flash is organized as 1K x 16. The Flash memory has an endurance of at least 1000

write/erase cycles.

The ATtiny22/L Program Counter PC is 10 bits wide, hence addressing the 1024 program memory addresses. See

page 38 for a detailed description on Flash data programming.

Constant tables must be allocated within the address 0-2K (see the LPM - Load Program Memory instruction description).

See page 9 for the different addressing modes.

EEPROM Data Memory

The ATtiny22/L contains 128 bytes of EEPROM data memory. It is organized as a separate data space, in which single

bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access

between the EEPROM and the CPU is described on page 30 specifying the EEPROM address register, the EEPROM data

For the SPI data downloading, see page 38 for a detailed description.

15 0

X - register 7 0 7 0

R27 ($1B) R26 ($1A)

15 0

Y - register 7 0 7 0

R29 ($1D) R28 ($1C)

15 0

Z - register 7 0 7 0

R31 ($1F) R30 ($1E)

8ATtiny22/22L

SRAM Data Memory

The following figure shows how the ATtiny22/L Data Memory is organized:

Figure 7. SRAM Organization

The 224 Data Memory locations address the Register file, I/O Memory and the data SRAM. The first 96 locations address

the Register File + I/O Memory, and the next 128 locations address the data SRAM.

The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with

Pre-Decrement and Indirect with Post-Increment. In the register file, registers R26 to R31 feature the indirect addressing

pointer registers.

The Direct addressing reaches the entire data address space.

The Indirect with Displacement mode features 63 address locations reach from the base address given by the Y and Z

When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X,

Y and Z are used and decremented and incremented.

The 32 general purpose working registers, 64 I/O registers and the 128 bytes of data SRAM in the ATtiny22/L are all

directly accessible through all these addressing modes.

R0 $00

R1 $01

R2 $02

……

R29 $1D

R30 $1E

R31 $1F

I/O Registers

$00 $20

$01 $21

$02 $22

……

$3D $5D

$3E $5E

$3F $5F

Internal SRAM

$60

$61

$62

…

$DD

$DE

$DF

ATtiny22/22L

Program and Data Addressing Modes

The ATtiny22/L AVR RISC Microcontroller supports powerful and efficient addressing modes for access to the program

memory (Flash) and data memory. This section describes the different addressing modes supported by the AVR architec-

ture. In the figures, OP means the operation code part of the instruction word. To simplify, not all figures show the exact

location of the addressing bits.

Figure 8. Direct Single Register Addressing

The operand is contained in register d (Rd).

Figure 9. Direct Register Addressing, Two Registers

Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd).

10 ATtiny22/22L

I/O Direct

Figure 10. I/O Direct Addressing

Operand address is contained in 6 bits of the instruction word. n is the destination or source register address.

Data Direct

Figure 11. Direct Data Addressing

A 16-bit Data Address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the destination or source

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