ARM Cortex-M3 DesignStart User manual
ARM® Cortex®-M3 DesignStart™ Eval
Revision: r0p0
FPGA User Guide
Copyright © 2017 ARM Limited or its affiliates. All rights reserved.
ARM 100896_0000_00_en
ARM® Cortex®-M3 DesignStart™ Eval
FPGA User Guide
Copyright © 2017 ARM Limited or its affiliates. All rights reserved.
Release Information
Document History
Issue Date Confidentiality Change
0000-00 14 June 2017 Non-Confidential First release for r0p0
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ARM® Cortex®-M3 DesignStart™ Eval
ARM 100896_0000_00_en Copyright © 2017 ARM Limited or its affiliates. All rights reserved. 2
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Contents
ARM® Cortex®-M3 DesignStart™ Eval FPGA User
Guide
Preface
About this book ...................................................... ...................................................... 7
Feedback .................................................................................................................... 10
Chapter 1 Introduction
1.1 About Cortex®-M3 DesignStart™ Eval ................................... ................................... 1-12
1.2 About the ARM Versatile Express Cortex-M Prototyping System (V2M-MPS2+) . . 1-14
1.3 Using the documentation ............................................ ............................................ 1-15
1.4 FPGA Evaluation Flow directory structure ............................... ............................... 1-17
1.5 Limitations ....................................................... ....................................................... 1-18
Chapter 2 Using the prebuilt FPGA image
2.1 Setting up the MPS2+ FPGA platform .................................. .................................. 2-20
2.2 Running the self-test program ........................................ ........................................ 2-21
2.3 Connecting to a debugger ........................................... ........................................... 2-23
Chapter 3 FPGA platform overview
3.1 System overview .................................................. .................................................. 3-25
3.2 Memory map ............................................................................................................ 3-26
3.3 Block RAM instances ............................................... ............................................... 3-27
3.4 External Zero Bus Turnaround SSRAM ................................. ................................. 3-28
3.5 External PSRAM ...................................................................................................... 3-29
ARM 100896_0000_00_en Copyright © 2017 ARM Limited or its affiliates. All rights reserved. 4
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3.6 Arduino adapter board .............................................. .............................................. 3-30
3.7 Embedded Trace Macrocell interface ...................................................................... 3-31
3.8 CMSDK APB subsystem ............................................ ............................................ 3-32
3.9 AHB GPIO ....................................................... ....................................................... 3-33
3.10 Serial Peripheral Interface ........................................... ........................................... 3-34
3.11 Color LCD parallel interface .......................................... .......................................... 3-35
3.12 Ethernet ......................................................... ......................................................... 3-36
3.13 VGA ............................................................ ............................................................ 3-37
3.14 Audio I2S ........................................................ ........................................................ 3-38
3.15 Audio configuration .................................................................................................. 3-40
3.16 FPGA system control and I/O .................................................................................. 3-41
Chapter 4 Clocks
4.1 Source clocks .......................................................................................................... 4-43
4.2 Derived clocks .................................................... .................................................... 4-44
Chapter 5 Serial Communication Controller
5.1 SCC interface overview ............................................. ............................................. 5-46
5.2 SCC memory map ................................................. ................................................. 5-47
Chapter 6 FPGA build
6.1 Build flow ........................................................ ........................................................ 6-50
6.2 Build requirements ................................................. ................................................. 6-52
Chapter 7 Integrating with mbed™ OS
7.1 Compatibility with mbed™ OS ......................................... ......................................... 7-54
Chapter 8 Performance and utilization
8.1 Performance and clocks .......................................................................................... 8-56
8.2 Utilization of default system .......................................... .......................................... 8-57
Appendix A Revisions
A.1 Revisions - Cortex®-M3 DesignStart™ Eval .................................................... Appx-A-59
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About this book
This book describes how to use the FPGA platform in the ARM Versatile™ Express Cortex®-M
Prototyping System to evaluate a design developed using Cortex-M3 DesignStart™ Eval.
Product revision status
The rmpn identifier indicates the revision status of the product described in this book, for example, r1p2,
where:
rmIdentifies the major revision of the product, for example, r1.
pnIdentifies the minor revision or modification status of the product, for example, p2.
Intended audience
This book is written for hardware engineers, software engineers, system integrators, and system
designers, who might not have previous experience of ARM products, but want to run a complete
example of a working system.
Using this book
This book is organized into the following chapters:
Chapter 1 Introduction
This chapter introduces Cortex-M3 DesignStart Eval and gives an overview of the FPGA
Evaluation Flow, its directory structure, and limitations.
Chapter 2 Using the prebuilt FPGA image
Cortex-M3 DesignStart Eval includes a prebuilt FPGA image file of the Cortex-M3 DesignStart
Eval example system. This chapter describes how to set up the MPS2+ platform to load the
prebuilt file and run a self-test program.
Chapter 3 FPGA platform overview
This section gives an overview of the FPGA components that are used in Cortex-M3 DesignStart
Eval.
Chapter 4 Clocks
This chapter describes the source and derived clocks for the FPGA design.
Chapter 5 Serial Communication Controller
This chapter describes the Serial Communication Controller (SCC) used in the Cortex-M3
DesignStart Eval FPGA image.
Chapter 6 FPGA build
This chapter describes the steps that are required to build an FPGA bit file from the supplied
source code.
Chapter 7 Integrating with mbed™ OS
This chapter describes the support available for integrating the FPGA system with mbed OS.
Chapter 8 Performance and utilization
This chapter describes the performance, resources, and utilization for the default system of the
FPGA design in Cortex-M3 DesignStart Eval.
Appendix A Revisions
This appendix describes the technical changes between released issues of this book.
Glossary
The ARM® Glossary is a list of terms used in ARM documentation, together with definitions for those
terms. The ARM Glossary does not contain terms that are industry standard unless the ARM meaning
differs from the generally accepted meaning.
Preface
About this book
ARM 100896_0000_00_en Copyright © 2017 ARM Limited or its affiliates. All rights reserved. 7
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See the ARM® Glossary for more information.
Typographic conventions
italic
Introduces special terminology, denotes cross-references, and citations.
bold
Highlights interface elements, such as menu names. Denotes signal names. Also used for terms
in descriptive lists, where appropriate.
monospace
Denotes text that you can enter at the keyboard, such as commands, file and program names,
and source code.
monospace
Denotes a permitted abbreviation for a command or option. You can enter the underlined text
instead of the full command or option name.
monospace italic
Denotes arguments to monospace text where the argument is to be replaced by a specific value.
monospace bold
Denotes language keywords when used outside example code.
<and>
Encloses replaceable terms for assembler syntax where they appear in code or code fragments.
For example:
MRC p15, 0, <Rd>, <CRn>, <CRm>, <Opcode_2>
SMALL CAPITALS
Used in body text for a few terms that have specific technical meanings, that are defined in the
ARM® Glossary. For example, IMPLEMENTATION DEFINED, IMPLEMENTATION SPECIFIC, UNKNOWN, and
UNPREDICTABLE.
Timing diagrams
The following figure explains the components used in timing diagrams. Variations, when they occur,
have clear labels. You must not assume any timing information that is not explicit in the diagrams.
Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the shaded
area at that time. The actual level is unimportant and does not affect normal operation.
Clock
HIGH to LOW
Transient
HIGH/LOW to HIGH
Bus stable
Bus to high impedance
Bus change
High impedance to stable bus
Figure 1 Key to timing diagram conventions
Signals
The signal conventions are:
Preface
About this book
ARM 100896_0000_00_en Copyright © 2017 ARM Limited or its affiliates. All rights reserved. 8
Non-Confidential
Signal level
The level of an asserted signal depends on whether the signal is active-HIGH or active-LOW.
Asserted means:
• HIGH for active-HIGH signals.
• LOW for active-LOW signals.
Lowercase n
At the start or end of a signal name denotes an active-LOW signal.
Additional reading
This book contains information that is specific to this product. See the following documents for other
relevant information.
ARM publications
• Cortex®-M3 DesignStart™ Eval publications:
— ARM® Cortex®-M3 DesignStart™ Eval RTL and Testbench User Guide (ARM 100894).
— ARM® Cortex®-M3 DesignStart™ Eval RTL and FPGA Quick Start Guide (ARM 100895).
— ARM® Cortex®-M3 DesignStart™ Eval Customization Guide (ARM 100897).
• Other ARM publications:
— ARM® Cortex®-M System Design Kit Technical Reference Manual (ARM DDI0479).
— ARM® TrustZone® TRNG True Random Number Generator Technical Reference Manual
(ARM 1009676).
— ARM® PrimeCell™ Real Time Clock (PL031) Technical Reference Manual (ARM DDI
0224).
— ARM® PrimeCell® Synchronous Serial Port (PL022) Technical Reference Manual (ARM
DDI 0194).
— ARM® Versatile™ Express Cortex®-M Prototyping System (V2M-MPS2 and V2M-MPS2+)
Technical Reference Manual (ARM 100112).
— Application Note AN531 uSDCARD SPI Adapter for the Cortex-M Prototyping System
(MPS2+) (ARM DAI 0531).
— Application Note AN502 Adapter for Arduino for the Cortex-M Prototyping System
(MPS2 and MPS2+) (ARM DAI 0502).
— ARM® AMBA® 3 AHB-Lite Protocol Specification (v1.0) (ARM IHI 0033).
— ARM® Architecture Reference Manual ARMv7, for ARMv7-M architecture profile (ARM
DDI0403).
— ARM® Cortex®-M3 Technical Reference Manual (ARM 100165).
— ARM® Cortex®-M3 Devices Generic User Guide (ARM DUI0552).
Other publications
None.
Preface
About this book
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Non-Confidential
Feedback
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ARM also welcomes general suggestions for additions and improvements.
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