Alinx AXU2CGA User manual

ZYNQ UltraScale+

FPGA Development Board

AXU2CGA/B

User Manual

ZYNQ Ultrascale + FPGA Board AXU2CGA/B User Manual

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Version Record

Version

Date

Release By

Description

Rev 1.0

2021-04-08

Rachel Zhou

First Release

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Table of Contents

Version Record.......................................................................................................2

Part 1: AXU2CGA/B Introduction........................................................................4

Part 2: ZYNQ Chip.................................................................................................5

Part 3: DDR4 DRAM............................................................................................. 7

Part 4: QSPI Flash...............................................................................................11

Part 5: eMMC Flash (Only for AXU2CGB)......................................................12

Part 6: EEPROM................................................................................................. 13

Part 7: DP Display Interface.............................................................................. 13

Part 8: USB 3.0 Interface................................................................................... 15

Part 9: Gigabit Ethernet Interface.....................................................................16

Part 10: USB to Serial Port................................................................................17

Part 11: SD Card Slot Interface........................................................................ 18

Part 12: PCIE Interface...................................................................................... 19

Part 13: 40-Pin Expansion Header...................................................................20

Part 14: MIPI Camera Interface........................................................................22

Part 15: JTAG Debug Port................................................................................. 24

Part 16: DIP Switch Configuration....................................................................25

Part 17: LEDs.......................................................................................................25

Part 18: System Clock........................................................................................26

Part 19: ALINX Customized Fan Interface......................................................27

Part 20: Power Input........................................................................................... 28

Part 21: Board Size Dimension.........................................................................29

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Part 1: AXU2CGA/B Introduction

The AXU2CGA/B Board is characterized by its small size and extensive

peripherals. The main chip is Xilinx's Zynq UltraScale+ MPSoCs CG family chip,

the model is XCZU2CG-1SFVC784E. The PS side of AXU2CGA is mounted

with 2 slices of DDR4 (total 1GB, 32bit) and 1 slice of 256Mb QSPI FLASH.

The PS side of AXU2CGB is equipped with 4 DDR4 (total 2GB, 64bit), one 8GB

eMMC FLASH memory chip and one 256Mb QSPI FLASH.

Peripheral interfaces include 1 MINI DP interface, 4 USB3.0 interfaces, 1

Gigabit Ethernet interface, 1 USB serial port, 1 PCIE interface, 1 TF card

interface, 2 40-pin expansion ports, 2 MIPI Interface, KEYs and LEDs.

The board schematic is as Figure 1-1:

Figure 1-1: Board Schematic

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Part 2: ZYNQ Chip

The PS system of the XCZU2CG-1SFVC784E chip integrates two ARM

Cortex™-A53 processors with a speed of up to 1.2Ghz and supports Level 2

Cache; it also contains two Cortex-R5 processors with a speed of up to

500Mhz. The XCZU2CG Chip supports 32-bit or 64-bit DDR4, LPDDR4, DDR3,

DDR3L, LPDDR3 memory chips, with rich high-speed interfaces on the PS

side such as PCIE Gen2, USB3.0, SATA 3.1, DisplayPort; it also supports

USB2.0, Gigabit Ethernet, SD/SDIO, I2C, CAN, UART, GPIO and other

interfaces. The PL end contains a wealth of programmable logic units, DSP and

internal RAM. The overall block diagram of the XCZU2CG chip is shown in the

figure 2-1:

Figure 2-1: Overall Block Diagram of ZU2CG Chip

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The main parameters of the PS system are as follows:

ARM dual-core Cortex™-A53 processor, speed up to 1.2GHz, each CPU

32KB level 1 instruction and data cache, 1MB level 2 cache, shared by 2

CPUs

ARM dual-core Cortex-R5 processor, speed up to 500MHz, each CPU

32KB level 1 instruction and data cache, and 128K tightly coupled memory

External storage interface, support 32/64bit DDR4/3/3L, LPDDR4/3

interface

Static storage interface, support NAND, 2xQuad-SPI FLASH

High-speed connection interface, support PCIe Gen2 x4, 2xUSB3.0, Sata

3.1, Display Port, 4 x Tri-mode Gigabit Ethernet

Common connection interface: 2xUSB2.0, 2x SD/SDIO, 2x UART, 2x CAN

2.0B, 2x I2C, 2x SPI, 4x 32b GPIO

Power management: support the division of Full/Low/PL/Battery four parts

of power

Encryption algorithm: support RSA, AES and SHA

System monitoring: 10-bit 1Mbps AD sampling for temperature and voltage

detection

The main parameters of the PL logic part are as follows:

Logic Cells: 103K

flip-flops : 94K

Lookup table (LUTs) : 47K；

Block RAM: 5.3Mb

Clock Management Unit (CMTs) : 3

Multiplier 18x25MACCs: 240

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Part 3: DDR4 DRAM

There are two Micron DDR4 chips on the PS side of the AXU2CGA board,

which form a 32-bit data bus bandwidth and a total capacity of 1GB. There are

4 Micron DDR4 chips on the PS side of the AXU2CGB board, which form a

64-bit data bus bandwidth and a total capacity of 2GB. The maximum operating

speed of DDR4 SDRAM on the PS side can reach 1200MHz (data rate

2400Mbps). The specific configuration of DDR4 SDRAM is shown below.

Among them, U71 and U72 are only AXU2CGB mounted.

Location

Capacity

Manufacturer

U3,U5,(U71,U72)

256M x 16bit

Micron

Table 3-1: DDR4 SDRAM Configuration

The hardware connection of DDR4 on the PS side is shown in Figure 3-1:

Figure 3-1: PS Side DDR4 DRAM Schematic

AXU2CGA PS side DDR4 SDRAM Pin Assignment:

Signal Name

Pin Name

Pin Number

PS_DDR4_DQS0_P

PS_DDR_DQS_P0_504

AF21

PS_DDR4_DQS0_N

PS_DDR_DQS_N0_504

AG21

PS_DDR4_DQS1_P

PS_DDR_DQS_P1_504

AF23

PS_DDR4_DQS1_N

PS_DDR_DQS_N1_504

AG23

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PS_DDR4_DQS2_P

PS_DDR_DQS_P2_504

AF25

PS_DDR4_DQS2_N

PS_DDR_DQS_N2_504

AF26

PS_DDR4_DQS3_P

PS_DDR_DQS_P3_504

AE27

PS_DDR4_DQS3_N

PS_DDR_DQS_N3_504

AF27

PS_DDR4_DQ0

PS_DDR_DQ0_504

AD21

PS_DDR4_DQ1

PS_DDR_DQ1_504

AE20

PS_DDR4_DQ2

PS_DDR_DQ2_504

AD20

PS_DDR4_DQ3

PS_DDR_DQ3_504

AF20

PS_DDR4_DQ4

PS_DDR_DQ4_504

AH21

PS_DDR4_DQ5

PS_DDR_DQ5_504

AH20

PS_DDR4_DQ6

PS_DDR_DQ6_504

AH19

PS_DDR4_DQ7

PS_DDR_DQ7_504

AG19

PS_DDR4_DQ8

PS_DDR_DQ8_504

AF22

PS_DDR4_DQ9

PS_DDR_DQ9_504

AH22

PS_DDR4_DQ10

PS_DDR_DQ10_504

AE22

PS_DDR4_DQ11

PS_DDR_DQ11_504

AD22

PS_DDR4_DQ12

PS_DDR_DQ12_504

AH23

PS_DDR4_DQ13

PS_DDR_DQ13_504

AH24

PS_DDR4_DQ14

PS_DDR_DQ14_504

AE24

PS_DDR4_DQ15

PS_DDR_DQ15_504

AG24

PS_DDR4_DQ16

PS_DDR_DQ16_504

AC26

PS_DDR4_DQ17

PS_DDR_DQ17_504

AD26

PS_DDR4_DQ18

PS_DDR_DQ18_504

AD25

PS_DDR4_DQ19

PS_DDR_DQ19_504

AD24

PS_DDR4_DQ20

PS_DDR_DQ20_504

AG26

PS_DDR4_DQ21

PS_DDR_DQ21_504

AH25

PS_DDR4_DQ22

PS_DDR_DQ22_504

AH26

PS_DDR4_DQ23

PS_DDR_DQ23_504

AG25

PS_DDR4_DQ24

PS_DDR_DQ24_504

AH27

PS_DDR4_DQ25

PS_DDR_DQ25_504

AH28

PS_DDR4_DQ26

PS_DDR_DQ26_504

AF28

PS_DDR4_DQ27

PS_DDR_DQ27_504

AG28

PS_DDR4_DQ28

PS_DDR_DQ28_504

AC27

PS_DDR4_DQ29

PS_DDR_DQ29_504

AD27

PS_DDR4_DQ30

PS_DDR_DQ30_504

AD28

PS_DDR4_DQ31

PS_DDR_DQ31_504

AC28

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PS_DDR4_DM0

PS_DDR_DM0_504

AG20

PS_DDR4_DM1

PS_DDR_DM1_504

AE23

PS_DDR4_DM2

PS_DDR_DM2_504

AE25

PS_DDR4_DM3

PS_DDR_DM3_504

AE28

PS_DDR4_A0

PS_DDR_A0_504

W28

PS_DDR4_A1

PS_DDR_A1_504

Y28

PS_DDR4_A2

PS_DDR_A2_504

AB28

PS_DDR4_A3

PS_DDR_A3_504

AA28

PS_DDR4_A4

PS_DDR_A4_504

Y27

PS_DDR4_A5

PS_DDR_A5_504

AA27

PS_DDR4_A6

PS_DDR_A6_504

Y22

PS_DDR4_A7

PS_DDR_A7_504

AA23

PS_DDR4_A8

PS_DDR_A8_504

AA22

PS_DDR4_A9

PS_DDR_A9_504

AB23

PS_DDR4_A10

PS_DDR_A10_504

AA25

PS_DDR4_A11

PS_DDR_A11_504

AA26

PS_DDR4_A12

PS_DDR_A12_504

AB25

PS_DDR4_A13

PS_DDR_A13_504

AB26

PS_DDR4_WE_B

PS_DDR_A14_504

AB24

PS_DDR4_CAS_B

PS_DDR_A15_504

AC24

PS_DDR4_RAS_B

PS_DDR_A16_504

AC23

PS_DDR4_ACT_B

PS_DDR_ACT_N_504

Y23

PS_DDR4_ALERT_B

PS_DDR_ALERT_N_504

U25

PS_DDR4_BA0

PS_DDR_BA0_504

V23

PS_DDR4_BA1

PS_DDR_BA1_504

W22

PS_DDR4_BG0

PS_DDR_BG0_504

W24

PS_DDR4_CS0_B

PS_DDR_CS_N0_504

W27

PS_DDR4_ODT0

PS_DDR_ODT0_504

U28

PS_DDR4_PARITY

PS_DDR_PARITY_504

V24

PS_DDR4_RESET_B

PS_DDR_RST_N_504

U23

PS_DDR4_CLK0_P

PS_DDR_CK0_P_504

W25

PS_DDR4_CLK0_N

PS_DDR_CK0_N_504

W26

PS_DDR4_CKE0

PS_DDR_CKE0_504

V28

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AXU2CGB PS side DDR4 SDRAM data pin assignment is the same as

AXU2CGA, additional data signal assignment is as follows:

Signal Name

Pin Name

Pin Number

PS_DDR4_DQS4_P

PS_DDR_DQS_P4_504

N23

PS_DDR4_DQS4_N

PS_DDR_DQS_N4_504

M23

PS_DDR4_DQS5_P

PS_DDR_DQS_P5_504

L23

PS_DDR4_DQS5_N

PS_DDR_DQS_N5_504

K23

PS_DDR4_DQS6_P

PS_DDR_DQS_P6_504

N26

PS_DDR4_DQS6_N

PS_DDR_DQS_N6_504

N27

PS_DDR4_DQS7_P

PS_DDR_DQS_P7_504

J26

PS_DDR4_DQS7_N

PS_DDR_DQS_N7_504

J27

PS_DDR4_DQ32

PS_DDR_DQ32_504

T22

PS_DDR4_DQ33

PS_DDR_DQ33_504

R22

PS_DDR4_DQ34

PS_DDR_DQ34_504

P22

PS_DDR4_DQ35

PS_DDR_DQ35_504

N22

PS_DDR4_DQ36

PS_DDR_DQ36_504

T23

PS_DDR4_DQ37

PS_DDR_DQ37_504

P24

PS_DDR4_DQ38

PS_DDR_DQ38_504

R24

PS_DDR4_DQ39

PS_DDR_DQ39_504

N24

PS_DDR4_DQ40

PS_DDR_DQ40_504

H24

PS_DDR4_DQ41

PS_DDR_DQ41_504

J24

PS_DDR4_DQ42

PS_DDR_DQ42_504

M24

PS_DDR4_DQ43

PS_DDR_DQ43_504

K24

PS_DDR4_DQ44

PS_DDR_DQ44_504

J22

PS_DDR4_DQ45

PS_DDR_DQ45_504

H22

PS_DDR4_DQ46

PS_DDR_DQ46_504

K22

PS_DDR4_DQ47

PS_DDR_DQ47_504

L22

PS_DDR4_DQ48

PS_DDR_DQ48_504

M25

PS_DDR4_DQ49

PS_DDR_DQ49_504

M26

PS_DDR4_DQ50

PS_DDR_DQ50_504

L25

PS_DDR4_DQ51

PS_DDR_DQ51_504

L26

PS_DDR4_DQ52

PS_DDR_DQ52_504

K28

PS_DDR4_DQ53

PS_DDR_DQ53_504

L28

PS_DDR4_DQ54

PS_DDR_DQ54_504

M28

PS_DDR4_DQ55

PS_DDR_DQ55_504

N28

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