Transcend TS64GSSD10-M User manual

-M

1.0” Solid State Disk

Transcend Information Inc.

V1.6

Description

The 1-inch Solid State Disk is small in size, has a

huge capacity and low power consumption making

it perfect for use as a mobile storage solution in

devices such as, Mobile Phones, PDA and GPS

systems. This guide is written to provide general

installation and handling information, please use it

in conjunction with the Owner’s Manual for your

device or system.

Placement

Features

•RoHS compliant

•Fully compatible with 1.0-inch hard drive form factor

and interface (35-Pin FPC ZIF connector)

•Non-volatile Flash Memory for outstanding data

retention

•Built-in ECC (Error Correction Code) functionality and

wear-leveling algorithm ensures highly reliable of data

transfer

•Mode Supports:

Ultra DMA Mode 0 to Mode 5

Multi-Word DMA Mode 0 to Mode 2

PIO Mode 0 to Mode 4

•Supports ATA Security Commands

•Support S.M.A.R.T function (self-definition)

•Lower Power Consumption

•Shock resistance

•Power Supply: 3.3V ±5%

Dimensions

Side Millimeters Inches

A 40.00 ±0.30 1.575 ±0.012

B 30.00 ±0.20 1.181 ±0.008

C 5.00 ±0.50 0.196 ±0.020

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1.0” Solid State Disk

Transcend Information Inc.

V1.6

Specifications

* Note: Reference to the IEC 60068-2-1 and IEC 60068-2-56 Testing procedures; 48-hours chamber test on ASUS

M2N-MX, 1GB RAM, Windows

XP Version 2002 SP2.

Physical Specification

Form Factor 1-inch HDD

Storage Capacities 64 GB

Length 30.0 0 ±0.20

Width 40.00 ±0.30

Dimensions (mm)

Height 5.00 ±0.50

Weight 8 g

Connector 0.3 mm pitch 35-Pin Zero Insertion Force (ZIF) connector (P-ATA)

Environmental Specifications

Operating Temperature 0

℃

to 70

℃

Storage Temperature 0

℃

to 70

℃

Humidity

Operating Humidity (Non condensation) 0% to 95%

Storage Humidity (Non condensation) 0% to 95%

Power Consumption

Input Voltage DC 3.3V ±5%

Mode Maximum (mA)

Write 143

Power Consumption

(DC 3.3V

℃

)

Standby 3.8

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1.0” Solid State Disk

Transcend Information Inc.

V1.6

* Note : 25 ℃, test on ASUS M3N7B, 3GB RAM, IDE interface support UDMA5, Windows

XP SP3, benchmark utility

FDBENCH (version 1.02), copied file 100MB

Actual Capacity

Model P/N User LBA Cylinder Head Sector

TS64GSSD10-M 125,059,072 16383 15 63

* Note: FAT32 format

Reliability

Data Reliability Random 8-bit BCH ECC in 512 bytes

Data Retention 10 years [7 years operating (block erase cycle < 4K cycle) + 3 years storage]

Connector Durability 10 times

MTBF 4,400,000 hours

Interface Specification

Drivers No Device Driver Required

ATA-7 V3 Specification

PIO Mode 0 - 4

Multi-Word DMA Mode 0 -2

ATA Compatibility

UDMA Mode 0 - 5

Performance

Model P/N Capacity Read Write Random Read Random Write

PCMark05

HDD Score

TS64GSSD10-M 64GB 64851 39233 56952 11297 6358

Regulations

Compliance CE, FCC and BSMI

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1.0” Solid State Disk

Transcend Information Inc.

V1.6

Mechanical Dimensions

Below figure illustrates the Transcend 1” Solid State Disk. All dimensions are in mm.

Top View

Lateral View

-M

1.0” Solid State Disk

Transcend Information Inc.

V1.6

Pin Assignments

Pin No. Pin Name Pin No. Pin Name

01 GND 02 DD10

03 DD9 04 DD2

05 DD8 06 DD1

07 -PDIAG 08 DD0

09 -DASP 10 DA0

11 -DMACK 12 DA1

13 DMARQ 14 DA2

15 DSTROBE 16 -RESET

17 -CSEL 18 VCC

19 VCC 20 INTRQ

21 -HIOW 22 -HIOR

23 -CS1 24 -CS0

25 DD15 26 DD7

27 DD14 28 DD6

29 DD13 30 DD5

31 DD12 32 DD4

33 DD11 34 DD3

35 GND

Pin Layout

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1.0” Solid State Disk

Transcend Information Inc.

V1.6

Block Diagram

DC Characteristics

Parameter Symbol

Min. Max. Unit Remark

Supply Voltage V

2.97 3.63 V

High level output voltage V

– 0.8 V

Low level output voltage V

0.8 V

2.4 V Non-schmitt trigger

High level input voltage

2.05 V Schmitt trigger

0.6 V Non-schmitt trigger

Low level input voltage

1.25 V Schmitt trigger

Pull up resistance

52.7 141 KOhm

Pull down resistance R

47.5 172 kOhm

Solid

State Disk

Controller

Flash Memory

D0 – D7

-CE0

-CE1

-WE…-RE

FPC

Connector

Flash Memory

D0 – D7

-CE0

-CE1

-WE…-RE

D00 ~ D07

0 ~ D

CE0,

CE2

…

CE1,

CE3

…

Data bus

Control

Signal

Power

Others

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1.0” Solid State Disk

Transcend Information Inc.

V1.6

DC Characteristics

Table: Series Termination for Ultra DMA

Signal Host Termination Device Termination

-IORD (-HDMARDY,HSTROBE) 22 ohm 88 ohm

-IOWR (STOP) 22 ohm 88 ohm

-CS0, -CS1 33 ohm 88 ohm

A00, A01, A02 33 ohm 88 ohm

-DMACK 22 ohm 88 ohm

D15 through D00 33 ohm 33 ohm

DMARQ 82 ohm 22 ohm

INTRQ 82 ohm 22 ohm

DSTROBE (-DDMARDY, DSTROBE) 82 ohm 22 ohm

-RESET 33 ohm 88 ohm

NOTE − Only those signals requiring termination are listed in this table. If a signal is not listed, series

termination is not required for operation in an Ultra DMA mode. Shows signals also requiring a pull-up or

pull-down resistor at the host. The actual termination values should be selected to compensate for transceiver

and trace impedance to match the characteristic cable impedance.

Electrical Characteristics

Parameter Value

Frequency Stability 30-80MHz

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1.0” Solid State Disk

Transcend Information Inc.

V1.6

True IDE PIO Mode Read/Write Timing Specification

Mode

Item

0 1 2 3 4

Note

t0 Cycle time (min) 600

383

240

180

120

t1 Address Valid to -HIOR/-HIOW setup (min)

70 50

t2 -HIOR/-HIOW (min) 165

125

100

t2 -HIOR/-HIOW (min) Register (8 bit) 290

290

t2i

-HIOR/-HIOW recovery time (min) - - - 70

t3 -HIOW data setup (min) 60 45

t4 -HIOW data hold (min) 30 20

t5 -HIOR data setup (min) 50 35

t6 -HIOR data hold (min) 5 5 5 5 5

t6Z

-HIOR data tristate (max) 30 30

t9 -HIOR/-HIOW to address valid hold 20 15

tRD

Read Data Valid to DSTROBE active (min),

if DSTROBE initially low after tA 0 0 0 0 0

tA DSTROBE Setup time 35 35

tB DSTROBE Pulse Width (max) 1250

1250

tC DSTROBE assertion to release (max) 5 5 5 5 5

Notes: All timings are in nanoseconds. All time intervals are recorded in nanoseconds. Although minimum time from DSTROBE high

to HIOR# high is 0 nsec, the minimum HIOR# width is still met.

1) Where t0 denotes the minimum total cycle time, t2 represents the minimum command active time, and t2i is the minimum

command recovery time or command inactive time. Actual cycle time equals the sum of the actual command active time and

the actual command inactive time. The three timing requirements of t0, t2, and t2i are met. The minimum total cycle time

requirement is greater than the sum of t2 and t2i, implying that a host implementation can extend either or both t2 or t2i to

ensure that t0 is equal to or greater than the value reported in the device’s identify device data. A PATA implementation

supports any legal host implementation.

2) This parameter specifies the time from the negation edge of HIOR# to the time that the PATA (tri-state) no longer drives the

data bus.

3) The delay from the activation of HIOR# or HIOW# activation until the state of DSTROBE is first sampled. If DSTROBE is

inactive, the host waits until DSTROBE is active before the PIO cycle is completed. When the PATA is not driving DSTROBE,

which is negated at the tA after HIOR# or HIOW# activation, then t5 is met and tRD is not applicable. When the PATA is

driving DSTROBE, which is negated at the time tA after HIOR# or HIOW#, then tRD is met and t5 is not applicable.

4) DSTROBE is not supported in this mode.

-M

1.0” Solid State Disk

Transcend Information Inc.

V1.6

NOTES:

1 Device address comprises CS1#, CS0#, and HA [2:0].

2 Data comprises HD [15:] (16-bit) or HD [7:0] (8 bit).

3 The negation of DSTROBE by the device is used to lengthen the PIO cycle. Whether the cycle is to be extended is

determined by the host after t

from the assertion of HIOR# or HIOW#. The assertion and negation of DSTROBE is

described in the following three cases:

(a) The device never negates DSTROBE: No wait is generated.

(b) Device drives DSTROBE low before t

: a wait is generated. The cycle is completed after DSTROBE is reasserted.

For cycles in which a wait is generated and HIOR# is asserted, the device places read data on D15-D00 for t

before DSTROBE is asserted.

-M

1.0” Solid State Disk

Transcend Information Inc.

V1.6



True IDE Multiword DMA Mode Read/Write Timing Specification

Item Mode 0

(ns)

Mode 1

(ns)

Mode 2

(ns) Note

Cycle time (min) 480 150 120 1

HIOR# / HIOW# asserted width (min) 215 80 70 1

HIOR# data access (max) 150 60 50

HIOR# data hold (min) 5 5 5

HIOR#/HIOW# data setup (min) 100 30 20

HIOW# data hold (min) 20 15 10

DMACK# to HIOR#/HIOW# setup (min)

0 0 0

HIOR# / HIOW# to DMACK# hold (min)

20 5 5

HIOR# negated width (min) 50 50 25 1

HIOW# negated width (min) 215 50 25 1

HIOR# to DMARQ delay (max) 120 40 35

HIOW# to DMARQ delay (max) 40 40 35

CSx valid to HIOR# / HIOW# 50 30 25

CSx hold 15 10 10

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