Texas Instruments TMS320DM644x User manual

TMS320DM644x DMSoCMultimedia Card (MMC)/Secure Digital (SD)Card Controller

User's Guide

Literature Number: SPRUE30BSeptember 2006

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Contents

Preface ............................................................................................................................... 71 Introduction ................................................................................................................ 91.1 Purpose of the Peripheral ....................................................................................... 91.2 Features ........................................................................................................... 91.3 Functional Block Diagram ....................................................................................... 91.4 Supported Use Case Statement .............................................................................. 101.5 Industry Standard(s) Compliance Statement ............................................................... 102 Peripheral Architecture .............................................................................................. 102.1 Clock Control .................................................................................................... 122.2 Signal Descriptions ............................................................................................. 132.3 Protocol Descriptions........................................................................................... 132.4 Data Flow in the Input/Output FIFO .......................................................................... 152.5 Data Flow in the Data Registers (MMCDRR and MMCDXR) ............................................. 172.6 FIFO Operation During Card Read Operation .............................................................. 192.7 FIFO Operation During Card Write Operation .............................................................. 212.8 Reset Considerations .......................................................................................... 232.9 Initialization ...................................................................................................... 232.10 Interrupt Support ................................................................................................ 272.11 DMA Event Support ............................................................................................ 282.12 Power Management ............................................................................................ 282.13 Emulation Considerations ..................................................................................... 283 Procedures for Common Operations ........................................................................... 293.1 Card Identification Operation .................................................................................. 293.2 MMC/SD Mode Single-Block Write Operation Using CPU ................................................ 323.3 MMC/SD Mode Single-Block Write Operation Using the EDMA ......................................... 343.4 MMC/SD Mode Single-Block Read Operation Using the CPU ........................................... 343.5 MMC/SD Mode Single-Block Read Operation Using EDMA .............................................. 353.6 MMC/SD Mode Multiple-Block Write Operation Using CPU .............................................. 363.7 MMC/SD Mode Multiple-Block Write Operation Using EDMA ............................................ 383.8 MMC/SD Mode Multiple-Block Read Operation Using CPU .............................................. 383.9 MMC/SD Mode Multiple-Block Read Operation Using EDMA ............................................ 394 Registers .................................................................................................................. 404.1 MMC Control Register (MMCCTL) ........................................................................... 414.2 MMC Memory Clock Control Register (MMCCLK) ......................................................... 424.3 MMC Status Register 0 (MMCST0) .......................................................................... 434.4 MMC Status Register 1 (MMCST1) .......................................................................... 454.5 MMC Interrupt Mask Register (MMCIM) ..................................................................... 464.6 MMC Response Time-Out Register (MMCTOR) ........................................................... 474.7 MMC Data Read Time-Out Register (MMCTOD) .......................................................... 484.8 MMC Block Length Register (MMCBLEN) .................................................................. 494.9 MMC Number of Blocks Register (MMCNBLK) ............................................................ 504.10 MMC Number of Blocks Counter Register (MMCNBLC) .................................................. 504.11 MMC Data Receive Register (MMCDRR) ................................................................... 514.12 MMC Data Transmit Register (MMCDXR) .................................................................. 51

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4.13 MMC Command Register (MMCCMD) ...................................................................... 524.14 MMC Argument Register (MMCARGHL) .................................................................... 544.15 MMC Response Registers (MMCRSP0-MMCRSP7) ...................................................... 554.16 MMC Data Response Register (MMCDRSP) ............................................................... 574.17 MMC Command Index Register (MMCCIDX) ............................................................... 574.18 MMC FIFO Control Register (MMCFIFOCTL) .............................................................. 58Appendix A Revision History ............................................................................................. 59

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List of Figures

1 MMC/SD Card Controller Block Diagram ............................................................................... 102 MMC/SD Controller Interface Diagram .................................................................................. 113 MMC Configuration and SD Configuration Diagram ................................................................... 114 MMC/SD Controller Clocking Diagram .................................................................................. 125 MMC/SD Mode Write Sequence Timing Diagram ..................................................................... 146 MMC/SD Mode Read Sequence Timing Diagram ..................................................................... 157 FIFO Operation Diagram .................................................................................................. 168 Little-Endian Access to MMCDXR/MMCDRR from the ARM CPU or the EDMA .................................. 179 Big-Endian Access to MMCDXR/MMCDRR from the ARM CPU or the EDMA .................................... 1810 FIFO Operation During Card Read Diagram ........................................................................... 2011 FIFO Operation During Card Write Diagram ........................................................................... 2212 MMC Card Identification Procedure ..................................................................................... 3013 SD Card Identification Procedure ........................................................................................ 3114 MMC/SD Mode Single-Block Write Operation .......................................................................... 3315 MMC/SD Mode Single-Block Read Operation .......................................................................... 3516 MMC/SD Multiple-Block Write Operation ............................................................................... 3717 MMC/SD Mode Multiple-Block Read Operation ........................................................................ 3918 MMC Control Register (MMCCTL) ....................................................................................... 4119 MMC Memory Clock Control Register (MMCCLK) ..................................................................... 4220 MMC Status Register 0 (MMCST0) ...................................................................................... 4321 MMC Status Register 1 (MMCST1) ...................................................................................... 4522 MMC Interrupt Mask Register (MMCIM) ................................................................................ 4623 MMC Response Time-Out Register (MMCTOR) ....................................................................... 4724 MMC Data Read Time-Out Register (MMCTOD) ...................................................................... 4825 MMC Block Length Register (MMCBLEN) .............................................................................. 4926 MMC Number of Blocks Register (MMCNBLK) ........................................................................ 5027 MMC Number of Blocks Counter Register (MMCNBLC) .............................................................. 5028 MMC Data Receive Register (MMCDRR)............................................................................... 5129 MMC Data Transmit Register (MMCDXR) .............................................................................. 5130 MMC Command Register (MMCCMD) .................................................................................. 5231 Command Format .......................................................................................................... 5332 MMC Argument Register (MMCARGHL) ................................................................................ 5433 MMC Response Register 0 and 1 (MMCRSP01) ...................................................................... 5534 MMC Response Register 2 and 3 (MMCRSP23) ...................................................................... 5535 MMC Response Register 4 and 5 (MMCRSP45) ...................................................................... 5536 MMC Response Register 6 and 7 (MMCRSP67) ...................................................................... 5537 MMC Data Response Register (MMCDRSP) .......................................................................... 5738 MMC Command Index Register (MMCCIDX) .......................................................................... 5739 MMC FIFO Control Register (MMCFIFOCTL) .......................................................................... 58

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List of Tables

1 MMC/SD Controller Pins Used in Each Mode .......................................................................... 132 MMC/SD Mode Write Sequence ......................................................................................... 143 MMC/SD Mode Read Sequence ......................................................................................... 154 Description of MMC/SD Interrupt Requests ............................................................................ 275 Multimedia Card/Secure Digital (MMC/SD) Card Controller Registers .............................................. 406 MMC Control Register (MMCCTL) Field Descriptions................................................................. 417 MMC Memory Clock Control Register (MMCCLK) Field Descriptions .............................................. 428 MMC Status Register 0 (MMCST0) Field Descriptions ............................................................... 439 MMC Status Register 1 (MMCST1) Field Descriptions ............................................................... 4510 MMC Interrupt Mask Register (MMCIM) Field Descriptions .......................................................... 4611 MMC Response Time-Out Register (MMCTOR) Field Descriptions ................................................ 4712 MMC Data Read Time-Out Register (MMCTOD) Field Descriptions ................................................ 4813 MMC Block Length Register (MMCBLEN) Field Descriptions ........................................................ 4914 MMC Number of Blocks Register (MMCNBLK) Field Descriptions .................................................. 5015 MMC Number of Blocks Counter Register (MMCNBLC) Field Descriptions ....................................... 5016 MMC Data Receive Register (MMCDRR) Field Descriptions ........................................................ 5117 MMC Data Transmit Register (MMCDXR) Field Descriptions ........................................................ 5118 MMC Command Register (MMCCMD) Field Descriptions ............................................................ 5219 Command Format .......................................................................................................... 5320 MMC Argument Register (MMCARGHL) Field Descriptions ......................................................... 5421 R1, R3, R4, R5, or R6 Response (48 Bits) ............................................................................. 5622 R2 Response (136 Bits) ................................................................................................... 5623 MMC Data Response Register (MMCDRSP) Field Descriptions .................................................... 5724 MMC Command Index Register (MMCCIDX) Field Descriptions .................................................... 5725 MMC FIFO Control Register (MMCFIFOCTL) Field Descriptions ................................................... 58A-1 Document Revision History ............................................................................................... 59

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PrefaceSPRUE30B – September 2006

Read This First

About This Manual

This manual describes the multimedia card (MMC)/secure digital (SD) card controller in theTMS320DM644x Digital Media System-on-Chip (DMSoC). The MMC/SD card is used in a number ofapplications to provide removable data storage. The MMC/SD controller provides an interface to externalMMC and SD cards. The MMC/SD protocol performs the communication between the MMC/SD controllerand MMC/SD card(s).

Notational Conventions

This document uses the following conventions.•Hexadecimal numbers are shown with the suffix h. For example, the following number is 40hexadecimal (decimal 64): 40h.•Registers in this document are shown in figures and described in tables.– Each register figure shows a rectangle divided into fields that represent the fields of the register.Each field is labeled with its bit name, its beginning and ending bit numbers above, and itsread/write properties below. A legend explains the notation used for the properties.– Reserved bits in a register figure designate a bit that is used for future device expansion.

Related Documentation From Texas InstrumentsThe following documents describe the TMS320DM644x Digital Media System-on-Chip (DMSoC). Copiesof these documents are available on the Internet at www.ti.com .Tip: Enter the literature number in thesearch box provided at www.ti.com.

The current documentation that describes the DM644x DMSoC, related peripherals, and other technicalcollateral, is available in the C6000 DSP product folder at: www.ti.com/c6000 .

SPRUE14 —TMS320DM644x DMSoC ARM Subsystem Reference Guide. Describes the ARMsubsytem in the TMS320DM644x Digital Media System-on-Chip (DMSoC). The ARM subsystem isdesigned to give the ARM926EJ-S (ARM9) master control of the device. In general, the ARM isresponsible for configuration and control of the device; including the DSP subsystem, the videoprocessing subsystem, and a majority of the peripherals and external memories.

SPRUE15 —TMS320DM644x DMSoC DSP Subsystem Reference Guide. Describes the digital signalprocessor (DSP) subsystem in the TMS320DM644x Digital Media System-on-Chip (DMSoC).

SPRUE19 —TMS320DM644x DMSoC Peripherals Overview Reference Guide. Provides an overviewand briefly describes the peripherals available on the TMS320DM644x Digital MediaSystem-on-Chip (DMSoC).

SPRAA84 —TMS320C64x to TMS320C64x+ CPU Migration Guide. Describes migrating from theTexas Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. Theobjective of this document is to indicate differences between the two cores. Functionality in thedevices that is identical is not included.

SPRU732 —TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide. Describes the CPUarchitecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digitalsignal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generationcomprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancement ofthe C64x DSP with added functionality and an expanded instruction set.

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Related Documentation From Texas Instruments

SPRU871 —TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digitalsignal processor (DSP) megamodule. Included is a discussion on the internal direct memory access(IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidthmanagement, and the memory and cache.

SPRAAA6 —EDMA v3.0 (EDMA3) Migration Guide for TMS320DM644x DMSoC. Describes migratingfrom the Texas Instruments TMS320C64x digital signal processor (DSP) enhanced direct memoryaccess (EDMA2) to the TMS320DM644x Digital Media System-on-Chip (DMSoC) EDMA3. Thisdocument summarizes the key differences between the EDMA3 and the EDMA2 and providesguidance for migrating from EDMA2 to EDMA3.Trademarks

SD is a trademark of SanDisk.

8Read This First SPRUE30B – September 2006Submit Documentation Feedback

1 Introduction

1.1 Purpose of the Peripheral

1.2 Features

1.3 Functional Block Diagram

User's GuideSPRUE30B – September 2006

Multimedia Card (MMC)/Secure Digital (SD) CardController

This document describes the multimedia card (MMC)/secure digital (SD) card controller in theTMS320DM644x Digital Media System-on-Chip (DMSoC).

A number of applications use the multimedia card (MMC)/secure digital (SD) card to provide removabledata storage. The MMC/SD card controller provides an interface to external MMC and SD cards. Thecommunication between the MMC/SD card controller and MMC/SD card(s) is performed according to theMMC/SD protocol.

The MMC/SD card controller has the following features:•Supports interface to multimedia cards (MMC)•Supports interface to secure digital (SD) memory cards•Ability to use the MMC/SD protocol•Programmable frequency of the clock that controls the timing of transfers between the MMC/SDcontroller and memory card•256-bit read/write FIFO to lower system overhead•Signaling to support enhanced direct memory access (EDMA) transfers (slave)•20 MHz maximum clock to MMC (specification 3.31)•50 MHz maximum clock to SD (specification version 1.1)

The MMC/SD card controller transfers data between the ARM and the EDMA controller on one side andthe MMC/SD card on the other side, as shown in Figure 1 . This means you have a choice of performingdata transfers using the CPU or EDMA as a mechanism to move data between the device memory andthe FIFO. The ARM and the EDMA controller can read from or write to the data in the card by accessingthe registers in the MMC/SD controller.

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Status

and

registers

DMA requests

Interrupts

ARM CPU

FIFO

MMC/SD

interface

CLK

divider

MMC/SD

card

interface

1.4 Supported Use Case Statement

1.5 Industry Standard(s) Compliance Statement

2 Peripheral Architecture

Peripheral Architecture

Figure 1. MMC/SD Card Controller Block Diagram

The MMC/SD card controller supports the following user cases:•MMC/SD card identification•MMC/SD single-block read using CPU•MMC/SD single-block read using EDMA•MMC/SD single-block write using CPU•MMC/SD single-block write using EDMA•MMC/SD multiple-block read using CPU•MMC/SD multiple-block read using EDMA•MMC/SD multiple-block write using CPU•MMC/SD multiple-block write using EDMA

The MMC/SD card controller supports the following industry standards (with the exception noted below):•MMC (Multimedia Card) Specification V3.31•SD (Secure Digital) Physical Layer Specification V1.1

The information in this document assumes that you are familiar with these standards.

The MMC/SD controller does not support the SPI mode of operation.

The MMC/SD controller uses the MMC/SD protocol to communicate with the MMC/SD cards. You canconfigure the MMC/SD controller to work as an MMC or SD controller, based on the type of card thecontroller is communicating with. Figure 2 summarizes the MMC/SD mode interface. Figure 3 illustrateshow the controller interfaces to the cards in MMC/SD mode.

In the MMC/SD mode, the MMC controller supports one or more MMC/SD cards. Regardless of thenumber of cards connected, the MMC/SD controller selects one by using identification broadcast on thedata line. The following MMC/SD controller pins are used:•CMD: This pin is used for two-way communication between the connected card and the MMC/SDcontroller. The MMC/SD controller transmits commands to the card and the memory card drivesresponses to the commands on this pin.•DAT0 or DAT0-3: MMC cards only use one data line (DAT0) and SD cards use one or four data lines.The number of DAT pins (the data bus width) is set by the WIDTH bit in the MMC control register(MMCCTL), see Section 4.1 ).•CLK: This pin provides the clock to the memory card from the MMC/SD controller.

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Table of contents

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