Texas Instruments TMS320C6457 User manual

TMS320C6457 DSPPower/Sleep Controller (PSC)

User's Guide

Literature Number: SPRUGL4March 2009

2 SPRUGL4 – March 2009Submit Documentation Feedback

Contents
Preface ........................................................................................................................................ 51 Introduction/Feature Overview ............................................................................................... 61.1 Purpose of the Peripheral ................................................................................................ 61.2 Features .................................................................................................................... 61.3 Terms and Abbreviations ................................................................................................ 62 Power/Sleep Controller ......................................................................................................... 72.1 Power and Reset Domains .............................................................................................. 72.2 Power Domain and Module States Defined ........................................................................... 82.2.1 Power Domain States ........................................................................................ 82.2.2 Module States ................................................................................................. 92.2.3 Local Reset .................................................................................................... 92.3 Executing State Transitions .............................................................................................. 92.3.1 Power Domain State Transitions ........................................................................... 92.3.2 Module State Transitions................................................................................... 102.3.3 Concurrent Power Domain/Module State Transitions .................................................. 102.3.4 Recommendations for Power Domain/Module Sequencing ........................................... 112.4 Emulation Support in the PSC ......................................................................................... 113 PSC Registers .................................................................................................................... 123.1 Power and Sleep Controller (PSC) Register Map ................................................................... 123.2 Register Descriptions ................................................................................................... 133.2.1 Peripheral Identification Register (PID) ................................................................. 133.2.2 Power Domain Transition Command Register (PTCMD) .............................................. 143.2.3 Power Domain Transition Status Register (PTSTAT) .................................................. 153.2.4 Power Domain Status Register 0-4 (PDSTATx) ........................................................ 153.2.5 Power Domain Control Register 0-4 (PDCTLx) ......................................................... 163.2.6 Module Status Register 0-10 (MDSTATy) ............................................................... 173.2.7 Module Control Register 0-10 (MDCTLy) ................................................................ 18
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List of Figures

1 Power and Clock Domains ................................................................................................. 72 Peripheral Identification Register (PID) .................................................................................. 133 Power Domain Transition Command Register (PTCMD) ............................................................. 144 Power Domain Transition Status Register (PTSTAT) ................................................................. 155 Power Domain Status Register 0-4 (PDSTATx) ....................................................................... 156 Power Domain Control Register 0-4 (PDCTLx) ........................................................................ 167 Module Status Register 0-10 (MDSTATy) .............................................................................. 178 Module Control Register 0-10 (MDCTLy) ............................................................................... 18

List of Tables

1 C6457 Power Domains ..................................................................................................... 82 C6457 Clock Domains ...................................................................................................... 83 Module States ................................................................................................................ 94 PSC Register Memory Map ............................................................................................... 125 Peripheral Identification Register (PID) Field Descriptions ........................................................... 136 Power Domain Transition Command Register (PTCMD) Field Descriptions ....................................... 147 Power Domain Transition Status Register (PTSTAT) Field Descriptions ........................................... 158 Power Domain Status Register 0-4 (PDSTATx) Field Descriptions ................................................. 159 Power Domain Control Register 0-4 (PDCTLx) Field Descriptions .................................................. 1610 Module Status Register 0-10 (MDSTATy) Field Descriptions ........................................................ 1711 Module Control Register 0-10 (MDCTLy) Field Descriptions ......................................................... 18

List of Figures4 SPRUGL4 – March 2009Submit Documentation Feedback

PrefaceSPRUGL4 – March 2009

Read This First

About This Manual

Notational Conventions

This document uses the following conventions.•Hexadecimal numbers are shown with the suffix h. For example, the following number is 40hexadecimal (decimal 64): 40h.•Registers in this document are shown in figures and described in tables.– Each register figure shows a rectangle divided into fields that represent the fields of the register.Each field is labeled with its bit name, its beginning and ending bit numbers above, and itsread/write properties below. A legend explains the notation used for the properties.– Reserved bits in a register figure designate a bit that is used for future device expansion.

Related Documentation From Texas InstrumentsThe following documents describe the TMS320C6457 DSP. Copies of these documents are available onthe Internet at www.ti.com .Tip: Enter the literature number in the search box provided at www.ti.com.

SPRU189 —TMS320C6000 DSP CPU and Instruction Set Reference Guide. Describes the CPUarchitecture, pipeline, instruction set, and interrupts for the TMS320C6000 digital signal processors(DSPs).

SPRU198 —TMS320C6000 Programmer's Guide. Describes ways to optimize C and assembly code forthe TMS320C6000™ DSPs and includes application program examples.

SPRU301 —TMS320C6000 Code Composer Studio Tutorial. Introduces the Code Composer Studio™integrated development environment and software tools.

SPRU321 —Code Composer Studio Application Programming Interface Reference Guide.Describes the Code Composer Studio™ application programming interface (API), which allows youto program custom plug-ins for Code Composer.

SPRU871 —TMS320C64x+ Megamodule Reference Guide. Describes the TMS320C64x+ digital signalprocessor (DSP) megamodule. Included is a discussion on the internal direct memory access(IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidthmanagement, and the memory and cache.Trademarks

TMS320C6000, Code Composer Studio are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

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1 Introduction/Feature Overview

1.1 Purpose of the Peripheral

1.2 Features

1.3 Terms and Abbreviations

User's GuideSPRUGL4 – March 2009

TMS320C6457 DSP Power/Sleep Controller (PSC)

The TMS320C6457 device is single-core DSP platform architected primarily for the communicationsinfrastructure market. This document covers the usage of the Power/Sleep Controller (PSC) in theTMS320C6457 device. The intent is not to keep this document as a user's guide, but to actually add thisto the TMS320C6457 data manual, once it is available.

The purpose of the PSC is to reduce power when a module is not being utilized. In the TMS320C6457system, the PSC is responsible for managing transitions of clock on/off and memory sleep on/off. ThePSC provides the user with an interface to control several important power and clock operations. Theseoperations are the focus of this document.

The PSC includes the following features:•Provides software interface to:– Control module memory sleep on/off.– Control module clock on/off.– Control CPU local resets.•Supports emulation features: power, clock, and reset.

3GPP — Third-Generation Partnership Project

CPU — Central Processing Unit of the C64x+ Core

DSP — Digital Signal Processor

GPSC — Global Power/Sleep Controller; manages the LPSCs.

LPSC — Local Power/Sleep Controller; one per module.

PSC — Power/Sleep Controller, including one GPSC and multiple LPSCs

RAC — Receive Accelerator, including GCCP cores, FEI, and BEI

TCP — Turbo Coprocessor

VCP — Viterbi Coprocessor

WCDMA — Wideband Code Division Multiple Access

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2 Power/Sleep Controller

2.1 Power and Reset Domains

Clock Domain 1

C64x+

AlwaysOn

Power Domain 0

Clock Domain 6

(Never Gated)

Proxied

Power Domain 1

SRIO

Clock Domain 0

Reserved

DDR.PLLC

Main.PLLC

LPSC0

sysclk1_po

sysclk2_po

sysclk3_po

bpsysclk_po

Global PSC

sysclkn_pi

chip_0_early_rst_pi_n

por_pi_n

Chip

Configuration

Module

rail_gnt_A

iso_ctl_A

rail_gnt_B

iso_ctl_B

rail_gnt_C

iso_ctl_C

rail_gnt_D

iso_ctl_D Proxied

Power Domain 2

TCP2_0

Proxied

Power Domain 3

TCP2_1

Proxied

Power Domain 4

VCP2

sysclk1_po

sysclk2_po

sysclkn_po

chip_1_rst_po_n

chip_0_rst_po_n

chip_0_early_rst_po_n

chip_1_rst_po_n

chip_0_rst_po_n

chip_0_early_rst_po_n

sysclkn

LPSC1

LPSC2

LPSC3

LPSC4

LPSC5

(Shared LPSC)

LPSC6

LPSC7

LPSC8

LPSC9

LPSC10

DDR

EMIF EMAC

McBSP1

Timer1

I2C

McBSP0

Timer0

GPIO

SCRs, bridges and

other non-power

managed modules

Clock Domain 3

HPI

Clock Domain 2

EMIF64

Clock Domain 6

DEBUGSS

Clock Domain 4

UTOPIA

Clock Domain 8

TCP2_0

Clock Domain 7

SRIO

Clock Domain 10

VCP2

Clock Domain 9

TCP2_1

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Power/Sleep Controller

The C6457 device comprises several power domains to enable minimizing power dissipation for unusedlogic on the device. The GPSC is used to control sleep for memories within each power domain.

Additionally, clock gating to each of the logic blocks is managed by the LPSCs of each module. Formodules with a dedicated clock or multiple clocks, the LPSC communicates with the PLL controller toenable and disable that module's clock(s) at the source. For modules that share a clock with othermodules, the LPSC controls the clock gating.

Figure 1 shows the PSC components and the power and clock domains they control. Many modulesreside in the AlwaysOn domain, that always has power and clocks provided. These consist primarily of theinfrastructure components that are responsible for the clock and reset control (PLL Controller, PSC), theswitch fabric that connects all of the modules, and small modules that do not need dynamic enable/disablebecause they do not consume a significant amount of power.

Figure 1. Power and Clock Domains

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2.2 Power Domain and Module States Defined

2.2.1 Power Domain States

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Table 1 summarizes the C6457 power domains.

Table 1. C6457 Power Domains

Domain Block(s) Note Power Connection

AlwaysOn Core, L1/L2 RAMs L2 RAMs can sleep , contents Software power-down from the CPUmaintainedAlwaysOn Most peripheral logic Cannot be disabled Always onAlwaysOn I/O: All 1.8-/3.3-V LVCMOS I/O, Cannot be disabled Always onmost peripheralsA RapidIO RAMs can sleep , contents Software controlmaintainedB TCP2_0 RAMs can sleep , contents Software controlmaintainedC TCP2_1 RAMs can sleep , contents Software controlmaintainedD VCP2 RAMs can sleep , contents Software controlmaintained

Table 2 summarizes the C6457 clock domains. These may also be referred to later in the document asmodules.

Table 2. C6457 Clock Domains

LPSC Number Module(s) Notes

0 Reserved1 CPU Cannot be controlled; always on2 EMIF64 Software control3 HPI Software control4 UTOPIA Software control5 Shared LPSC for all modules other than those Cannot be controlled; always onlisted in this table.6 DEBUGSS Software control7 SRIO Software control8 TCP2_0 Software control9 TCP2_1 Software control10 VCP2 Software controlNo LPSC Bootcfg, PSC, Main PLLCTL, Efuse, and DFT. These modules do not use LPSC.

The PSC module organizes modules into different power domains and into different modules (clockdomains). Note that there is no relationship between a power domain and a module. These are completelyseparate entities and may be controlled separately.

A power domain can only be in one of two states: ON or OFF, defined as follows:•ON: Power to the power domain is on. Memories are awake.•OFF: Power to the power domain is off. Memories are asleep (low-leakage standby mode).

In the C6457 device, the AlwaysOn power domain is always in the ON state, when the chip is powered on.The other power domains, however, can be in either the ON or OFF state; i.e., the memory for a specificmodule can remain powered down if it is not used.

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2.2.2 Module States

2.2.3 Local Reset

2.3 Executing State Transitions

2.3.1 Power Domain State Transitions

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Power/Sleep Controller

A module can be in one of two states: Enable or SwRstDisable. As shown in Table 3 , these two statescorrespond to combinations of module reset asserted or de-asserted and module clock on or off. Note thatmodule reset is defined to completely reset a given module, such that all hardware is put back into itsdefault state. For more information on module reset, see Curie Chip Architecture (XXXX-SYS-FS-001)Revision XXXX.

Table 3. Module States

Module State Module Reset Module Clock

Enable De-asserted ONSwRstDisable Asserted OFF

The module states are defined as follows:•Enable: A module in the Enable state has its module reset de-asserted and its clock on. This is thenormal run-time state for a given module.•SwRstDisable: A module in the SwResetDisable state has its module reset asserted and its clockOFF. This state is not expected to be initiated by software.

In addition to module reset described in the previous section, the C64x+ CPU can be reset using a speciallocal reset. When local reset is asserted, the internal memories (L1P, L1D, and L2) for the core are stillaccessible. The local reset only resets the corresponding C64x+ core, not the rest of the chip. Local resetis intended to be used by the watchdog timers to reset the C64x+ core in the event of an error. Theprocedures for asserting and de-asserting local reset are as follows (Y denotes the module domainnumber):

•Set MDCTL[Y].LRSTZ to 0x0 to assert local reset.•Set MDCTL[Y].LRSTZ to 0x1 to de-assert local reset. The 64x+ core immediately executes programinstructions after reset is de-asserted. Note that the boot sequence does not re-occur unless there is achip-level reset. Execution of code previously in L2 begins execution.

This section describes how to execute state transitions for power domains and modules. Examples showhow to enable only power domains, only modules, or a combination. Although you have complete controlof the sequencing, for TI recommendations, see Section 2.3.4 .

This section describes the basic procedure for transitioning the state of a power domain which, in the caseof the C6457 device is limited to the memories located in a particular domain. The majority of the moduleson the chip are always in the ON state. The PSC handles all required internal operations to wakememories for the controlled power domains.

Note: As mentioned previously, in the C6457 device there are multiple power domains. TheAlwaysOn power domain is always in the ON state when the chip is powered-on, andtherefore it is not possible to transition this domain to the OFF state. Conversely, the otherdomains are in the OFF states when the chip is powered-on. Transitions from ON to OFF arenever allowed.

The procedure for power domain state transitions follows (X denotes the power domain number, Ydenotes the module domain number):•Wait for PTSTAT.GOSTAT[X] to clear to 0x0. Wait for any previously initiated transitions to finishbefore initiating a new transition.

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2.3.2 Module State Transitions

2.3.3 Concurrent Power Domain/Module State Transitions

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•Set PDCTL[X].NEXT for an ON (0x1) transition. Note: When PTCMD.GO[X] is set to 0x1 in the nextstep, the PDCTL[X].NEXT field of this power domain and the MDCTL[Y].NEXT field of the module inthis power domain are evaluated. Therefore, you may set the MDCTL[Y].NEXT field for multiplemodules before executing this step. Note that, if enabling other modules, ensure that if they are not inthe AlwaysOn domain, the memories for that module are not asleep.•Set PTCMD.GO[X] to 0x1 to initiate the state transition(s). The PSC awakens the memory for thatparticular domain.•Wait for PTSTAT.GOSTAT[X] to clear to 0x0. The domain is safely in the new state only afterPTSTAT.GOSTAT[X] is cleared to 0x0.

This section describes the procedure for transitioning the module state.

Note: In the C6457 device, the following procedure is directly applicable for all LPSC-controlledmodules, except the C64x+ core domains. To transition the module state, you must be awareof several system considerations. Transitions from Enable to any other state are not allowed.Also, before transitioning a module to Enable, if the memories are not in the AlwaysOnpower domain, they must be turned on before or in parallel with the transition. SeeSection 2.3.1 .

The procedure for module state transitions follows (X denotes the power domain number, Y denotes themodule domain number):•Wait for PTSTAT.GOSTAT[X] to clear to 0x0. Wait for any previously initiated transitions to finishbefore initiating a new transition.•Set MDCTL[Y].NEXT to Enable (0x3). Note that you may set transitions in multiple MDCTL[Y].NEXTfields in this step as long as the corresponding power domain is on.•Set PTCMD.GO[X] to 0x1 to initiate the transition(s).•Wait for PTSTAT.GOSTAT[X] to clear to 0x0. The module is safely in the new state only afterPTSTAT.GOSTAT[X] clears to 0x0.

This section describes the basic procedure for transitioning the state of a power domain and moduledomain for modules which are not in the AlwaysOn domain. You may do these separately as described inthe sections above, if desired.

The procedure for concurrent power domain/module state transitions follows (X denotes the power domainnumber, Y denotes the module domain number):•Wait for PTSTAT.GOSTAT[X] to clear to 0x0. Wait for any previously initiated transitions to finishbefore initiating a new transition.•Set PDCTL[X].NEXT for an ON (0x1) transition.•Set MDCTL[Y].NEXT to Enable (0x3). Note that you may set transitions in multiple MDCTL.NEXTfields in this step as long as the corresponding power domain is on.•Set PTCMD.GO[X] 0x1 to initiate the state transition(s). The PSC awakens the memory for thatparticular domain, starts the module clock, then de-asserts the module reset.•Wait for PTSTAT.GOSTAT[X] to clear to 0x0. The domain is safely in the new state only afterPTSTAT.GOSTAT[X] is cleared to 0x0.

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