Texas Instruments TPS70351EVM User manual

TPS70351EVM

Lo ĆDropout, DualĆOutput Linear Regulator EVM

For Using the TPS70351

October 2000 POWER MANAGEMENT PRODUCTS

User’s Guide

SLVU036

IMPORTANT NOTICE

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any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TIdeemsnecessarytosupport thiswarranty. Specifictestingofallparameters ofeachdevice isnotnecessarily

performed, except those mandated by government requirements.

Customers are responsible for their applications using TI components.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TIassumes noliabilityforapplicationsassistance orcustomer productdesign. TIdoes notwarrantorrepresent

thatanylicense,eitherexpressorimplied,isgrantedunderanypatentright,copyright,maskworkright,orother

intellectual property right of TI covering or relating to any combination, machine, or process in which such

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party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

iii

Read This First

Preface

About This Manual

This user’s guide describes the TPS70351EVM low-dropout, dual-output

evaluation module (SLVP165). The SLVP165 provides a convenient method

for evaluating the performance of a dual-output linear regulator.

How to Use This Manual

Chapter 1 Introduction

Chapter 2 EVM Adjustments and Test Points

Chapter 3 Circuit Design

Chapter 4 Test Results

Information About Cautions and Warnings

This book may contain cautions and warnings.

This is an example of a caution statement.

A caution statement describes a situation that could potentially

damage your software or equipment.

This is an example of a warning statement.

A warning statement describes a situation that could potentially

cause harm to you.

The information in a caution or a warning is provided for your protection.

Please read each caution and warning carefully.

Related Documentation From Texas Instruments

TPS70351 data sheets (literature number SLVS285)

Trademarks

PowerPAD is a trademark of Texas Instruments.

Running Title—Attribute Reference

Chapter Title—Attribute Reference

Contents

1 Introduction 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 Low Dropout Voltage Linear Regulator Circuit Operation 1-2. . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Design Strategy 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Schematic 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Bill of Materials 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5 Board Layout 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 EVM Adjustments and Test Points 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 Adjustment by Switch and Jumpers 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Adjustment Through Component Changes 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Test Setup 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Circuit Design 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 ESR and Transient Response 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Test Results 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1 Test Results 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Running Title—Attribute Reference

Figures

1–1 Typical LDO Application 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–2 SLVP165B EVM Universal LDO Tester Schematic Diagram 1-4. . . . . . . . . . . . . . . . . . . . . . . . .

1–3 Top Layer 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–4 Bottom Layer (top view) 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–5 Assembly Drawing (top assembly) 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–1 Test Setup 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–1 ESR and ESL 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–2 LDO Output Stage With Parasitic Resistances ESR 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–3 Correlation of Different ESRs and Their Influence to the Regulation of VOat a

Load Step From Low-to-High Output Current 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–1 VOUT1 Load Transient 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–2 VOUT2 Load Transient 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–3 Timing When SEQUENCE Is High 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–4 Timing When SEQUENCE Is Low 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–5 Timing Including RESET 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–6 Timing When SEQUENCE Is Low, With a Fault on VOUT1 4-4. . . . . . . . . . . . . . . . . . . . . . . . . .

4–7 Timing When SEQUENCE Is High, With a Fault on VOUT1 4-5. . . . . . . . . . . . . . . . . . . . . . . . .

4–8 Timing When SEQUENCE Is Low, With a Fault on VOUT2 4-5. . . . . . . . . . . . . . . . . . . . . . . . . .

4–9 Timing When SEQUENCE Is High, With a Fault on VOUT2 4-6. . . . . . . . . . . . . . . . . . . . . . . . .

4–10 Timing When MR Is Toggled 4-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Tables

1–1 Summary of the TPS703xx LDO Family Features 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–2 SLVP165B EVM Bill of Materials 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–1 Jumper Functions 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–2 Commonly Changed Components 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–3 Timing Equations 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–4 Regulator Loading Options 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1

Introduction

This user’s guide describes the TPS70351EVM165 low-dropout, dual-output

evaluationmodule(SLVP165B).LDOsprovideidealpowersuppliesforrapidly

transitioning DSP loads. The TPS703xx family of devices is designed to

provide a complete power management solution for DSP, processor power,

ASIC,FPGA,anddigitalapplicationswheredualoutputvoltageregulatorsare

required. Easy programmability of the sequencing function makes this family

ideal for any DSP applications with a power sequencing requirement.

Differentiated features, such as SVS supervisory circuit, manual reset inputs,

and enable function, provide a complete system solution. Moreover, with its

low-quiescent current, low-dropout voltage, low-output noise, high PSRR,

fast-transient response, and high accuracy compared to standard LDOs, the

TPS703xxprovidesan ideal solutionwhere standard linearregulators are too

inefficient or too slow and where a switch converter solution or the source

power supply is too noisy.

Topic Page

1.1 Low Dropout Voltage Linear Regulator Circuit Operation 1–2. . . . . . . . .

1.2 Design Strategy 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Schematic 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Bill of Materials 1–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5 Board Layout 1–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 1

Low Dropout Voltage Linear Regulator Circuit Operation

1-2

Introduction

1.1 Low Dropout Voltage Linear Regulator Circuit Operation

InTI’slowdropoutvoltagelinearregulatortopology,aPMOStransistorisused

for the pass element. Because the PMOS device behaves as a low-value

resistor,thedropoutvoltageisverylowandisdirectlyproportionaltotheoutput

current.Additionally,sincethePMOSpasselementisavoltage-drivendevice,

the quiescent current is very low and independent of output loading.

The basic LDO regulator circuit includes the LDO and an output capacitor for

stabilization. Figure 1–1 shows the circuit of a typical LDO application.

Figure 1–1.Typical LDO Application

Control

Vref

LDO

Load

VCC

In the LDO application shown in Figure 1–1, the LDO regulates the output

voltage VO.

If VOfalls below the regulation level, the controller increases the VSG

differential and the PMOS transistor conducts more current, resulting in an

increaseinVO.IfVOexceedstheregulationlevel,thecontrollerdecreasesthe

VSG differential and the PMOS transistor conducts less current, resulting in a

decreaseinVO.ThePMOSpasselementactslikeanadjustableresistor.The

morenegative the gatebecomes versus thesource, the lessthe source-drain

resistance becomes, resulting in higher current flow through the PMOS.

Design Strategy

1-3

Introduction

1.2 Design Strategy

The TI SLVP165B EVM provides a convenient method for evaluating the

performance of TPS703xx dual-output linear regulators. The EVM provides

proven, demonstrated reference designs and test modes to aid in evaluation.

Theboardcontainsapowersupplyalongwithanonboardtransientgenerator.

The transient slew rate can be modified by changing two resistors. Jumpers

allow settings of minimum/maximum load as well as device-enabling and

power sequencing. There is enough room on the EVM to evaluate different

typesofoutputcapacitorsincludingESRbehaviors.Manytestpointsallowthe

measuring of input, output, and dropout voltage.

The EVM contains a TPS70351. Regulator 1 provides an output voltage of

3.3 V and a maximum output current of 1 A. Regulator 2 provides an output

voltage of 1.8 V and a maximum output current of 2 A.

Table 1–1 summarizes the TPS703xx family’s features. See the TPS703xx

datasheet,TIliteraturenumberSLVS285

forafurtherexplanationoffeatures.

Table 1–1.Summary of the TPS703xx LDO Family Features

Description TPS703xx Feature

Maximum input voltage [V] 6

Maximum output current [A] 1/2

Typical quiescent current [µA] 185

Typical dropout voltage [mV] 160

Typical output noise [µVrms]

(30 Hz ≤f ≤50 kHz, Co= 33 µF) 79/77

Accuracy over line, load, and temperature 2%

PSRR (at 1 kHz, Co= 10 µF, TJ= 25°C) 65/60 dB

Package 24 pin TSSOP with PowerPAD

Minimum output capacitor > 47 µF (ceramic)

Available voltage option [V] 3.3/1.5, 3.3/1.2, 3.3/1.8, 3.3/2.5, and adj/adj

Performance advantage Dual output LDO, power-up sequencing, DSP application,

PG and RESET

PowerPAD is a trademark of Texas Instruments.

Schematic

1-4

Introduction

1.3 Schematic

Figure1–2 shows the SLVP165 EVM schematic diagram.

Figure 1–2.SLVP165B EVM Universal LDO Tester Schematic Diagram

Off

7DISCH

6THRES

2TRIG

1GND

4RESET 3

OUT

CTL

DL4148

+C3

JP7

C10

1000 pF

TP9

12 GND/HS

5MR2

6MR1

7ENABLE

GND/HS

1GND/HS

8SEQUENCE

9GND

4NC

RESET

PGD

PwrPad 14

OUT2 13

GND/HS

TPS70351PWP

R15

R5 10

R7 10

3GND

21IN

42IN

REG

2OUT

1OUT Q1

Si4410

C11

1000 pF

DL4148

R6 510

R8 510

+C2

TP6

TP4

TP3

TP5

TP8

TP7

JP1

Green

TP11

TP12

TP13

TP10

R12

TP17

C14

C12

R11

RED

TP14

TP16

R10

R24

R23

R21

R20

JP6 JP5

JP13

JP14

JP9

JP12

JP8

JP11

R19

R18

R17

R16

JP10

C13

R13

R14

C15

TP15

JP15

JP16

GND

J1 1

100 µF0.1 µF

TP1

VIN1

Sense

PGDGND

10 kΩ

100 µF0.1 µF

TP2

Sense

JP2

JP3

GND VIN

JP4

GND

0.1 µF

4.3 kΩ

10 kΩ

1µF

ENABLE

5.1 kΩ

TLC555D C7

0.1 µF

TP18

TPS2812

10 µF

0.1 µF

IMBD4148

2 kΩ2 kΩ

33µF0.1 µF

33 kΩ

Sense

1.8 kΩ

47µF0.1 µF

GND

Load 1

R22

VOUT2

OUT1

VOUT1

IN1

VIN1

IN2

VIN2

SENSE1

SENSE2

OUT2

OUT1

OUT2

IN2

IN1

IN2

VCC

Table of contents

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