ST STM8L Installation and operating instructions

July 2013 DocID16139 Rev 5 1/42

AN3029

Application note

Getting started with STM8L and STM8AL

Introduction

This application note complements the information in the STM8L and STM8AL datasheets

by describing the minimum hardware and software environment required to build an

application around an STM8L or STM8AL 8-bit microcontroller device.

A brief description of the principal hardware components is given. The power supply,

analog-to-digital converter (ADC), clock management, and reset control are described in

some detail. In addition, some hardware recommendations are given. This application note

also contains detailed reference design schematics with descriptions of the main

components. The STM8 development tools and software toolchain are common to STM8L,

STM8S, STM8AL, and STM8AF and are presented in Section 8, and Section 9. Section 10

describes how to set up the STM8 development environment. Finally, Section 11 provides a

list of relevant documentation and online support resources.

Table 1. Applicable products

Product family Part numbers

Microcontrollers

– STM8L051/52

– STM8L101

– STM8L151C2/K2/G2/F2 and STM8L151C3/K3/G3/F3

– STM8L151x4, STM8L151x6, STM8L152x4, STM8L152x6

– STM8L151x8, STM8L152x8, STM8L151R6, STM8L152R6, STM8L162R8,

STM8L162M8

– STM8AL313x, STM8AL314x, STM8AL316x, STM8AL3L4x, STM8AL3L6x

www.st.com

Contents AN3029

2/42 DocID16139 Rev 5

Contents

1 Hardware requirements summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1 Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2 Main operating voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.3 Power-on/power-down reset (POR/PDR) . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.1 Analog power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.2 Analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4.1 Clock management overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4.2 Internal clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4.3 External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4.3.1 HSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4.3.2 LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5 Reset control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.1 Reset management overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.1.1 Output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.1.2 Input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.2 Hardware reset implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.1 Printed circuit board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.2 Component position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.3 Ground and power supply (VSS, VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.4 Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.5 Other signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.6 Unused I/Os and features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.7 User options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.8 Bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

DocID16139 Rev 5 3/42

AN3029 Contents

7 Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.1 Component references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.2 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

8 STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

8.1 Single wire interface module (SWIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

8.1.1 SWIM overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

8.1.2 SWIM connector pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8.1.3 Hardware connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8.2 STice emulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.2.1 STice overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.2.2 STice in emulation configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

8.2.3 In-circuit programming and debugging . . . . . . . . . . . . . . . . . . . . . . . . . 25

8.3 RLink and STLink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

9 STM8 software toolchain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

9.1 Integrated development environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

9.2 Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

9.3 Firmware library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

10 Setting up the STM8 development environment . . . . . . . . . . . . . . . . . 28

10.1 Installing the tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

10.2 Using the tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

10.2.1 Project editing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

10.2.2 Online help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

10.3 Running the demonstration software . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

10.3.1 Compiling the project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

10.3.2 Selecting the correct debug instrument . . . . . . . . . . . . . . . . . . . . . . . . . 33

10.3.3 Connecting the hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

10.3.4 Starting the debug session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

10.3.5 Running the software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

10.3.6 Follow up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

11 Documentation and online support . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

List of tables AN3029

4/42 DocID16139 Rev 5

List of tables

Table 1. Applicable products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Component list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 3. SWIM connector pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 4. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

DocID16139 Rev 5 5/42

AN3029 List of figures

List of figures

Figure 1. Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 2. Typical layout of VDD/VSS pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3. Analog input interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 4. HSE clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 5. External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 6. Crystal/ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 7. Reset management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 8. Output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 9. Input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 10. Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 11. Debug system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 12. Hardware connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 13. Connection description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 14. STice in emulation configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 15. In-circuit programming and debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 16. STM8 software toolchain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 17. STVD open example workspace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 18. STVD MCU edit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 19. STM8 firmware library online help manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 20. STVD: Building the project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 21. STVD: Selecting the debug instrument. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 22. Connecting the debug instrument to the STM8L101-EVAL evaluation board . . . . . . . . . . 34

Figure 23. Connecting the debug instrument to the STM8L152x-EVAL evaluation board . . . . . . . . . 35

Figure 24. STVD: Starting the debug session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 25. STVD: Run the software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 26. STM8 evaluation board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Hardware requirements summary AN3029

6/42 DocID16139 Rev 5

1 Hardware requirements summary

To build an application around an STM8L or STM8AL device, the application board should

provide the following features:

•Power supply (mandatory)

•Clock management (optional)

•Reset management (optional)

•Debugging tool support: Single wire interface module (SWIM) connector (optional)

2 Power supply

2.1 Power supply overview

The STM8L or STM8AL can be supplied through a 1.65 V to 3.6 V external source (1.8 V to

3.6 V for STM8L05xxx). For medium density STM8L15xxx, medium density

STM8AL31xx/STM8AL3Lxx, and high density STM8L15xxx/STM8L162xx with BOR, the

power supply must be above 1.8 V at power-on and can go down to 1.65 V at power-down.

An on-chip power management system provides the constant digital supply to the core logic,

both in normal and low power modes. This guarantees that the logic consumes a constant

current over the voltage range. It is also capable of detecting voltage drops and generate

reset to avoid heratic behavior.

The STM8L and STM8AL devices provide:

•Depending on packages, one pair of pads (VDD/VSS), or several pairs of pads

(VDDx/VSSx) from 1.65 V or 1.8 V to 3.6 V.

All VDDx and VSSx must be at the same potential respectively. The VDDx pins must be

connected to VDD with external decoupling capacitors: one 100 nF Ceramic capacitor

for each VDDx pin and one single 1 µF Tantalum or Ceramic capacitor.

The STM8L15xxx, STM8AL31xx, and STM8L162xx devices also provide in some

packages:

•One pair of pads, VDDA/VSSA, dedicated to analog functions. VDDA and VSSA must be

at the same potential respectively as VDD and VSS. Refer to Section 3: Analog-to-digital

converter (ADC) for more details. The VDDA pin must be connected to two external

decoupling capacitors (one 100 nF Ceramic capacitor and one single 1 µF Tantalum or

Ceramic capacitor). Additional precautions can be taken to filter analog noise: VDDA

can be connected to VDD through a ferrite bead.

STM8L152xx, STM8AL3Lxx and STM8L162xx devices manage the supply voltage needed

by the LCD in three different ways (see Figure 1):

1. If the LCD feature is not used, connect the VLCD pin to VDD.

2. Apply to VLCD the voltage to be applied to the LCD.

3. Leave the STM8L152xx/STM8L162xx/STM8AL3Lxx to provide the correct voltage, via

its programmable LCD booster, by connecting the VLCD pin to a 1µF capacitor.

DocID16139 Rev 5 7/42

AN3029 Power supply

Figure 1. Power supply

1. Optional: if a separate, external reference voltage is connected on VREF+, the two capacitors (100 nF and 1

µF) must be connected. VREF+ is either connected to VDDA or VREF.

2. N is the number of VDD and VSS inputs.

Note: The capacitors must be connected as close as possible to the device supplies.

Placing a crystal/resonator on OSCIN/OSCOUT is optional. The resonator must be

connected as close as possible to the OSCIN and OSCOUT pins. The loading capacitance

ground must be connected as close as possible to VSS.

2.2 Main operating voltages

STM8L and STM8AL devices are processed in 0.13 µm technology. The STM8L and

STM8AL core and I/O peripherals need different power supplies. In fact, STM8L and

STM8AL devices have an internal regulator with a nominal target output of 1.8 V.

MS30982V1

VLCD

STM8L/STM8AL

N × 100 nF

VDD

+ 1 × 10 μF

100 nF + 1 μF

(note 1)

VLCD VREF+

VDDA

VSSA

VDD 1/2/... /N

VSS 1/2/... /N

VREF

VDD

1 μF

(optional)

(note 2)

Power supply AN3029

8/42 DocID16139 Rev 5

2.3 Power-on/power-down reset (POR/PDR)

The input supply to the main and low power regulators is monitored by a power-on/power-

down reset circuit. The monitoring voltage begins at 0.7 V.

During power-on, the POR/PDR keeps the device under reset until the supply voltages (VDD

and VDDA) reach their specified working area. Maximum power on time tVDD[max] must be

respected, as the internal reset provided for supply stabilization is maintained for ~1 ms.

At power-on, a defined reset should be maintained below 0.7 V. The upper threshold for a

reset release is defined in the electrical characteristics section of the product datasheets.

A hysteresis is implemented (POR > PDR) to ensure clean detection of voltage rise and fall.

The POR/PDR also generates a reset when the supply voltage drops below the VPDR

threshold (isolated and repetitive events).

Correct device reset during power-on sequence is guaranteed when tVDD[max] is respected.

It is recommended to use an internal BOR or an external reset circuit (especially for

STM8L101xx devices) to ensure correct device reset during power-down when VPDR < VDD

< VDD[min].

For better power monitoring, the STM8L15xxx, STM8L162xx, STM8AL31xx, and

STM8AL3Lxx provide a brown out reset (BOR) and programmable power voltage detection

(PVD) for an earlier detection of voltage drop.

Recommendations

All pins need to be properly connected to the power supplies. These connections, including

pads, tracks and vias should have the lowest possible impedance. This is typically achieved

with thick track widths and preferably dedicated power supply planes in multi-layer printed

circuit boards (PCBs).

In addition, each power supply pair should be decoupled with filtering ceramic capacitors (C)

at 100 nF with one chemical C (1..2 µF) in parallel on the STM8L/STM8AL devices. The

ceramic capacitors should be placed as close as possible to the appropriate pins, or below

the appropriate pins, on the opposite side of the PCB. Typical values are 10 nF to 100 nF,

but exact values depend on the application needs. Figure 2 shows the typical layout of such

a VDD/VSS pair.

Figure 2. Typical layout of VDD/VSS pair

MS32523V1

Via to VSS

Via to VDD

Cap.

VDD VSS

STM8

DocID16139 Rev 5 9/42

AN3029 Analog-to-digital converter (ADC)

3 Analog-to-digital converter (ADC)

This section does not apply to STM8L101xx devices.

3.1 Analog power

For some packages, the ADC unit has an independent, analog supply voltage, isolated on

input pin VDDA, which allows the ADC to accept a very clean voltage source. This analog

voltage, VDDA, should be identical to the digital voltage supply on pin VDD. To filter some

noise, a ferrite bead can be added between VDD and VDDA. This ferrite bead should be

chosen according to the frequencies to be filtered.

Some packages also provide a separate external analog reference voltage input for the

ADC unit on the VREF+ pin. This gives better accuracy on low voltage input as follows:

•The VREF+ pin can be connected to the VDDA external power supply. If a separate,

external reference voltage is applied on VREF+, a 100 nF and a 1 µF capacitor must be

connected on this pin. To compensate for peak consumption on VREF

, the 1 µF

capacitor may be increased to 10 µF when the sampling speed is low. In all cases,

VREF+ must be kept between 2.4 V and VDDA. If VDDA is below 2.4, VREF+ must be

equal to VDDA. This input is internally bonded to VDDA in the devices that have no

internal VREF+ pin.

•VREF- (input, analog reference negative): The lower/negative reference voltage is

internally bonded to VSSA.

3.2 Analog input

The devices include up to 28 analog input channels (including four fast channels), each

multiplexed with an I/O, which are converted by the ADC one at a time.

The external input impedance (RAIN) max value is 50 kΩ. The four fast channels can convert

at maximum speed (1 MHz) if RAIN is less than 0.5 kΩ.

Please refer to Figure 3.

Figure 3. Analog input interface

Please refer to the applicable datasheets and reference manuals for more details.

MS32530V1

Sample and hold

ADC converter

12-bit

converter

RADC

CADC

0.6 V

VDD

AINx

RAIN

Cparasitic IL

VAIN

Clock management AN3029

10/42 DocID16139 Rev 5

4 Clock management

The STM8L101xx devices have no external clock, so no precautionary measures are

needed.

4.1 Clock management overview

STM8L05xxx, STM8L15xxx, STM8L162xx, STM8AL31xx and STM8AL3Lxx devices offer a

flexible way of selecting the core and peripheral clocks (ADC, memory, and digital

peripherals). The devices have internal and external clock source inputs, both of which have

a high speed and a low speed version. Any of those four clocks can be use for the CPU and

most of the peripherals through a programmable prescaler. An I/O can be programmed as

output clock (CCO) to reflect one of the four clocks (with or without prescaling).

The signal which leaves the I/O represents an output clock (CCO) divided by a division

factor.

4.2 Internal clocks

STM8L and STM8AL devices have two kinds of internal clock: A high speed internal clock

(HSI) running at 16 MHz and a low speed internal clock (LSI) running at 38 kHz.

After reset, the CPU starts with the internal RC (HSI clock signal) divided by 8, i.e. 2 MHz.

4.3 External clock

STM8L05xx, STM8L15xxx, STM8L162xx, STM8AL31xx, and STM8AL3Lxx devices have

two kinds of external clock: A high speed external clock (HSE) running at up to 16 MHz and

a low speed external clock (LSE) running at 32.768 kHz.

4.3.1 HSE clock

STM8L05xx, STM8L15xxx, STM8L162xx, STM8AL31xx, and STM8AL3Lxx devices can

connect to an external crystal or an external oscillator.

Note: When no external clock is used, OSCIN and OSCOUT can be used as general purpose

I/Os.

Figure 4 describes the external clock connections.

External clock

•Frequency: 0 kHz … 16 MHz

•Input hysteresis: 100 mV

Caution: Without prescaler, a duty cycle of 45/55 % maximum must be respected at high speed

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