ST STM32L0 Series Installation and operating instructions

April 2014 DocID026156 Rev 1 1/34

AN4467

Application note

Getting started with STM32L0xx hardware development

Introduction

This application note is intended for system designers who require a hardware

implementation overview of the development board features such as the power supply, the

clock management, the reset control, the boot mode settings and the debug management. It

shows how to use STM32L0xx product families and describes the minimum hardware

resources required to develop an STM32L0xx application.

Detailed reference design schematics are also contained in this document with descriptions

of the main components, interfaces and modes.

Table 1. Applicable products

Type Product categories

Microcontrollers STM32L0 Series

www.st.com

Contents AN4467

2/34 DocID026156 Rev 1

Contents

1 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1.1 Independent A/D converter supply and reference voltage . . . . . . . . . . . . 8

1.1.2 Independent LCD supply (STM32L0x3 only) . . . . . . . . . . . . . . . . . . . . . . 9

1.1.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.2 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

1.3 Reset and power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.3.1 Power-on reset (POR) / Power-down reset (PDR),

Brownout reset (BOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1.3.2 Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . . 14

1.3.3 Brownout reset (BOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.3.4 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.1 MSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.2 HSE OSC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.2.1 External source (HSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.2.2 External crystal/ceramic resonator (HSE crystal) . . . . . . . . . . . . . . . . . 18

2.3 LSE OSC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.3.1 External crystal/ceramic resonator (LSE crystal) . . . . . . . . . . . . . . . . . . 20

2.3.2 External source (LSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.4 Clock security system on HSE (CSSHSE) . . . . . . . . . . . . . . . . . . . . . . . . 21

2.5 HSI16 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.6 LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.1 Boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.2 Embedded boot loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.3 BOOT0 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4 Debug management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.2 SWD debug port (serial wire) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

DocID026156 Rev 1 3/34

AN4467 Contents

4.3 Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.4 Serial wire debug (SWD) pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.4.1 SWD pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.4.2 Internal pull-up and pull-down on SWD pins . . . . . . . . . . . . . . . . . . . . . 25

4.4.3 SWD port connection with standard SWD connector . . . . . . . . . . . . . . 25

5 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.1 Printed circuit board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.2 Component position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.3 Ground and power supply (VSS, VDD,VSSA, VDDA) . . . . . . . . . . . . . . . . . 27

5.4 Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.5 Other signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.6 Unused I/Os and features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6 Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.1.1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.1.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.1.3 Boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.1.4 SWD interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.1.5 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.2 Component references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

List of tables AN4467

4/34 DocID026156 Rev 1

List of tables

Table 1. Applicable products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. VLCD rails connections to GPIO pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 3. Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 4. SWD port pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 5. Mandatory components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 6. Optional components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 7. Reference connection for all packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 8. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

DocID026156 Rev 1 5/34

AN4467 List of figures

List of figures

Figure 1. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 2. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 3. Optional LCD power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 4. Power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 5. Power on reset/power down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 6. PVD thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 7. Simplified diagram of the reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 8. External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 9. Crystal/ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 10. External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 11. Crystal/ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 12. Host-to-board connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 13. SWD port connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 14. Typical layout for VDD/VSS pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 15. Reference design (based on STM32L053RBT6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Power supplies AN4467

6/34 DocID026156 Rev 1

1 Power supplies

1.1 Introduction

The chip requires power supply on different power pins:

•VDD= 1.65 to 3.6 V: external power supply for I/Os and the internal regulator. Provided

externally through VDD pins. For VDD below 1.8 V see Section 1.3.3: Brownout reset

(BOR)

•VDDA = VDD: external analog power supply for ADC/DAC, Comparators, Reset

blocks, RCs and PLL. The minimum voltage to be applied to VDDA is 1.8 V when the

ADC and DAC are used.The VDDA voltage level must always be equal to the VDD

voltage level, A maximum difference of 300 mV between VDD and VDDA can be

tolerated during power-up and normal operation.

•VLCD= 2.5V to 3.6V when the LCD controller is powered externally. When the LCD is

powered internally from the voltage generated by the embedded step-up converter,

VLCD pin must be connected to a capacitor. If the LCD is not used at all, this pin should

be connected to VDDA.

•VDD_USB= 3.0 to 3.6 V, VDD_USB is a dedicated independent USB power supply for

USB transceivers. The minimum value of 3.0 V guarantees the USB’s signal voltage

level. When USB is not used the application must supply VDD_USB=1.65V to 3.6V.

Digital power voltage (VCORE) is provided with an embedded linear voltage regulator with

three different programmable ranges from 1.2 to 1.8 V.

To be fully functional at full speed, the device requires a 1.71 to 3.6 V operating voltage

supply (VDD), making possible to reach the digital power voltage VCORE close to 1.8 V

(product voltage range 1).

Product voltage range 2 (VCORE = 1.5 V) and 3 (VCORE = 1.2 V) can be selected when the

VDD operates from 1.65 to 3.6 V. Therefore, frequency is limited to 16 MHz and 4.2 MHz

respectively.

When the ADC, DAC and brownout reset (BOR) are not used, the device can operate at

power voltages below 1.8 V, down to 1.65 V.

DocID026156 Rev 1 7/34

AN4467 Power supplies

Figure 1. Power supply overview

Note: VDDA and VSSA must be connected to VDD and VSS, respectively.

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Power supplies AN4467

8/34 DocID026156 Rev 1

1.1.1 Independent A/D converter supply and reference voltage

To improve conversion accuracy, the ADC and the DAC have an independent power supply

that can be filtered separately, and shielded from noise on the PCB.

•The ADC voltage supply input is available on a separate VDDA pin

•An isolated supply ground connection is provided on the VSSA pin

VDDA and VREF+ require a stable voltage. The consumption on VDDA can reach several mA

(see IDD(ADCx), IDD(DAC), IDD(COMPx), IVDDA, and IVREF in the product datasheets for

further information).

When available (depending on the package), VREF- must be tied to VSSA.

VSSA and VDDA must be tied to VSS directly, without any filtering device, this avoids some

ESD issues.

On some packages with the pin VREF+ to ensure a better accuracy on low-voltage inputs

and outputs, the user can connect to VREF+ a separate external reference voltage which is

lower than VDD. VREF+ is the highest voltage, represented by the full scale value, for an

analog input (ADC) or output (DAC) signal.

On packages without such a dedicated pin, VREF+ is internally connected to the ADC

voltage supply (VDDA).

DocID026156 Rev 1 9/34

AN4467 Power supplies

1.1.2 Independent LCD supply (STM32L0x3 only)

The VLCD pin is provided to control the contrast of the glass LCD. This pin can be used in

two ways:

•It can receive, from an external circuitry, the desired maximum voltage that is provided

on the segment and common lines to the glass LCD by the microcontroller.

•It can also be used to connect an external capacitor that is used by the microcontroller

for its voltage step-up converter. This step-up converter is controlled by software to

provide the desired voltage to the segment and common lines of the glass LCD. Refer

to the specific product datasheet for the capacitor value.

The voltage provided to the segment and common lines defines the contrast of the glass

LCD pixels. This contrast can be reduced when the dead time between frames is

configured.

In case of LCD with big pixel, the high capacitance of the pixel might degrade the LCD

signal shape. So the device offer the possibility to connect internal VLCD rails

(LCD_VLCD1, LCD_VLCD2, LCD_VLCD3) to optional capacitors. This improves the

Segment and Common line signals shape with limited use of high drive resistor network, so

it improves the signal shape without extra current consumption. The values of these

decoupling capacitors must be tuned accordingto the LCD glass and the PCB capacitances.

As a guideline the user can set the decoupling capacitor values to approximately 10 times

the LCD and PCB capacitance. The LCD rails to be connected depends on the Bias

configuration.

1.1.3 Voltage regulator

The internal voltage regulator is always enabled after reset. It can be configured to provide

the core with three different voltage ranges. Choosing a range with low Vcore reduces the

consumption but lowers the maximum acceptable core speed. Consumption ranges in

decreasing consumption order are as follows:

•Range 1, available only for VDD above 1.71 V, allows maximum speed

•Range 2 allows CPU frequency up to 16 MHz

•Range 3 allows CPU frequency up to 4 MHz

Note: In Range 1, when VDD is below 2.0V, the CPU frequency in run mode must be managed to

prevent any changes exceeding a ratio of 4 in one shot. A delay of 5µs must be respected

between 2 changes. There is no limitation when waking up from low-power mode.

Table 2. VLCD rails connections to GPIO pins

Bias Pin selected by

CAPA[2:0] bits

1/2 1/3 1/4

LCD_VLCD3 Not used Not used 3/4 VLCD PB0

LCD_VLCD2 1/2 VLCD 2/3 VLCD 1/2 VLCD PB2

LCD_VLCD1 Not used 1/3 VLCD 1/2 VLCD PB12

Power supplies AN4467

10/34 DocID026156 Rev 1

Voltage regulator works in three different modes depending on the application:

•In Run mode, the regulator supplies full power to the Vcore domain (core, memories

and digital peripherals).

•In Stop mode, low-power run and low-power wait modes, the regulator supplies low-

power to the Vcore domain, preserving the contents of the registers and SRAM.

•In Standby mode, the regulator is powered off. The contents of the registers and SRAM

are lost except for those powered with the Standby circuitry.

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