NXP Semiconductors MPC574 P Series User manual

MPC574xP Clock Calculator Guide

How to use MPC5744P tool to easily calculate device frequency domains

by: NXP Semiconductors

1 Introduction

NXP’s MPC574xP is a lockstep, dual-core 32-bit microcontroller intended for

safety and chassis applications. This application note will refer to any device

in the MPC574xP family, MPC5741P, MPC5742P, MPC5743P, and MPC5744P,

as simply “MPC5744P.”

The MPC5744P supports an 8-44 MHz external oscillator (XOSC), a 16 MHz

internal RC oscillator (IRCOSC), and two phase locked loops (PLL) for a

maximum operating frequency of 200 MHz. The IRCOSC is selected out of

reset so increasing the operating frequency from 16 MHz requires additional

configuration. The MPC574xP clock calculator is meant to complement the

reference manual. It seeks to simplify the clock configuration process by

providing a graphical, interactive tool to help the user find the correct register

settings in order to achieve the desired clock frequencies.

Accompanying this application note is the clock calculator. You can download

it from MPC574xP_Clock_Calculator.

The clock calculator makes use of macros to perform functions like resetting

the spreadsheet to initial values, configuring all clock frequencies to the

maximum allowable settings, and copying generated code. Macros must be

enabled in the user's MS Excel to access these features. If macros are turned

off however, the tool will still be able to calculate clock frequencies, but the

aforementioned features will be disabled. To turn on macros in MS Excel 2016,

go to the Developer tab on the top toolbar and click on Macro Security. A popup

window will appear. In it, select Enable all macros.

Figure 1. Enabling macros

Contents

1 Introduction..........................................1

2 Clock calculator design...................... 2

2.1 Tree......................................... 3

2.2 Oscillator control..................... 6

2.3 Peripheral domains................. 6

2.4 LFAST clocking....................... 7

2.5 PLLx........................................9

2.6 Reference Tables

(pll0_phi, pll0_phi1, and

pll1_phi)...................................9

2.7 Summary...............................10

2.8 Limits.....................................13

3 Clock tool example use case:

configure ADC to PLL0 at 80 MHz. 14

3.1 Configure ADC_CLK............. 15

3.1.1 Configure the

oscillator.................... 16

3.1.2 Configure PLL0.......18

3.1.3 Finish setting

ADC_CLK..................23

3.2 Configure ADC bus clock

to 40 MHz PLL.......................24

3.3 Observe the registers............25

3.4 Copy the code.......................26

4 Conclusion......................................... 27

5 Revision history.................................27

NXP Semiconductors Document Number: AN5393

Application Note Rev. 9, April 2018

2 Clock calculator design

The MPC574xP clock calculator takes the form of an interactive Microsoft Excel spreadsheet organized into multiple tabs as shown

in the following figure.

Figure 2. MPC574xP clock calculator setup

Clock sources (e.g. oscillators and PLLs) propagate to the various clock domains from which the MCU modules take their clocks.

Most cells representing clock domain frequencies are not to be modified manually. The user is meant to enter frequencies to the

few select clock sources and all clock domain frequencies derive from these sources. Several clock domain inputs are meant to

be modified manually as they represent external clocks that are driven into a pin. There are also input cells that set muxes and

clock dividers. All cells that take entries have blue borders instead of black, shown below.

Figure 3. Input cells vs. output cells

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There are limits to what frequencies can be entered to the input frequency cells. Values that are out of range will be rejected and

the user will receive an error message. Invalid clock domain frequencies that arise from valid input values and legal, but improper,

dividers will be shaded in red, as will be explained in greater depth later in this application note.

Frequency values are linked across tabs, so FRAY_CLK in the Tree tab will always be the same as FRAY_CLK in the Peripheral

Domains tab. Hyperlinks are provided to duplicate domain names to link back to their points of origin. For example, FRAY_CLK

originates in Tree. Therefore, clicking the FRAY_CLK textbox in Peripheral Domains will take the user to FRAY_CLK in Tree.

Textboxes that are links, when hovered over, will cause the mouse cursor to turn into a hand icon and a pop-up to appear showing

the address of the destination, as shown in the following figure.

Figure 4. Clicking on a link

The following subsections will explain in depth the purpose of each tab.

2.1 Tree

Tree is the centerpiece of the tool. This tab is the starting point for all clock frequency calculations. It is organized to resemble the

MPC5744P clock tree as presented in the following figure.

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Figure 5. MPC5744P Reference Manual clock tree

The following figure shows, in part, the diagram’s clock tool counterpart. The difference between the two is that the latter is

interactive.

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Figure 6. Clock calculator tree

The flow of the diagram generally goes from left to right. On the left are the MPC5744P clock sources and on the right are the

clock domains. MCU modules run on one or more of these clock domains.

Clock domain frequency values are displayed in the outlined cells next to their labels. Most cells are not meant to be written to;

their values are dependent on the frequencies generated by preceding steps in the clock tree. Take MOTC_CLK, for example: its

value is sourced from either the IRCOSC, XOSC, or PLL0_PHI. Now, look at the IRCOSC block. IRCOSC is at 16 MHz, but the

frequency that propagates depends on the next block, IRCOSC Source Controller. Therefore, the actual input frequency received

by blocks that take IRCOSC as a source is the IRCOSC frequency of 16 MHz, filtered by the IRCOSC Source Controller block.

The same goes for XOSC. PLL0_PHI is configured in the PLL0 tab. MOTC_CLK selects from these three clock sources by selecting

the value of the AUX Clock Selector 0 block. Then finally, the selected signal is divided by the MOTC_CLK prescaler value.

Each auxiliary clock and the system clock can feed into multiple domains that each have their own dividers. The number to the

left of the prescaler shows the number of the divider that is associated with that clock. In the case of MOTC_CLK, the number “0”

is shown next to the MOTC_CLK divider. This means that MOTC_CLK is configured by Divider 0 of Auxiliary Clock 0.

This tab also features two buttons, Reset and Max. They only have function when macros are enabled. Clicking on these buttons

with macros disabled will return an error. If macros are enabled, the Reset button will set all blocks to their reset value, as described

in the reference manual. The Max button sets all blocks in this tool to values that configure the system and auxiliary clock domains

to their respective maximum allowable frequencies. Below is a screenshot of the buttons.

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Figure 7. Buttons

2.2 Oscillator control

Oscillator Control controls the generation of the external oscillator (XOSC) frequency. MPC5744P supports two ways of XOSC

generation. The chip has two external oscillator pins, XTAL and EXTAL. An 8-44 MHz external oscillator can be connected to both

pins. This external oscillator is also referred to simply as the XTAL. If the XOSC Select block selects XTAL, XOSC will derive its

frequency from the 8-44 MHz external oscillator (XTAL) block. Alternatively, a waveform can be driven directly to the EXTAL pin.

This signal is also referred to simply as EXTAL. When the XOSC Select block selects EXTAL, XOSC will derive its frequency from

the EXTAL pin. Shown below is a screenshot.

Figure 8. Oscillator control

2.3 Peripheral domains

Peripheral Domains is an in-depth diagram of MPC5744P modules. Where Tree leaves off at the clock domain level, Peripheral

Domains picks up and progresses to the module level, shown below.

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Figure 9. Peripheral domains

The clock domains are color-coded. Black lines are reserved for clock domains that only a few modules use. For example, the

SAR ADC module takes both PBRIDGEx_CLK and ADC_CLK. ADC_CLK is black because only the ADC uses that clock. As a

rule of thumb, clock domains are represented with black lines if all modules using it can fit within a single window without having

to scroll. The frequencies on this tab are not meant to be modified and are dependent on frequency values in the Tree tab.

2.4 LFAST clocking

The LFAST is a versatile, but intricate module. It supports its own PLL which generates multiple phases and generates a signal

within specification only if its inputs are certain frequencies. These intricacies make it necessary to give LFAST is own dedicated

tab. Peripheral Domains still hosts an LFAST block that shows its input clocks and is hyper-linked to LFAST Clocking, as shown

in the following figure.

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Figure 10. LFAST in peripheral domains

LFAST Clocking presents a block diagram of the module with various clocks going into it. It also supports LFAST_PLL

configuration to increase the LFAST frequency up to 320 MHz. The LFAST also supports a low-speed mode as well as a high-

speed mode. This tool allows the user to select between the two modes. Below is a screenshot of the sheet.

Figure 11. LFAST block diagram

Since the LFAST signal must be generated from an input clock of 10, 13, 20, or 26 MHz, this tool blocks any input from the signal

RF_REF other than these four values. RF_REF can technically be set to any value, but any frequency that is not 10, 13, 20, or 26

MHz generates an invalid signal. Therefore, in this tool, RF_REF goes through the LFAST Input Filter block before becoming

lfast_sys_clk, which in turn is the signal that gets fed into the LFAST_PLL and phase generators, as shown in the following figure.

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Figure 12. LFAST clocking input filter

If RF_REF is 10, 13, 20, or 26 MHz, lfast_sys_clk is also 10/13/20/26 MHz; otherwise, lfast_sys_clk is 0. MPC5744P does not

actually filter RF_REF the way this tool does. The purpose of the LFAST Input Filter block is to simulate how the user can technically

set RF_REF to any value, but the resulting LFAST output would be unusable. Therefore, if a user were to enter an invalid input

frequency (i.e. not 10, 13, 20, or 26 MHz), all subsequent frequencies would be 0, and the user would know to change the input.

2.5 PLLx

PLL0 and PLL1 are visual abstractions of the PLL digital interface, as shown in the following figure.

Figure 13. PLL0 control

The input source of PLL0 and PLL1 is selected by the auxiliary clock selectors, AUX Clock Selector 3 and AUX Clock Selector

4in the Tree tab. Then, from the source, the dividers and multipliers located in the PLL0 and PLL1 tabs are set in order to achieve

the PLL output frequencies. The PLL output frequencies are in turn propagated to the PLLx_PHIn clock domains in the Tree tab.

2.6 Reference Tables (pll0_phi, pll0_phi1, and pll1_phi)

The three tabs pll0_phi, pll0_phi1, and pll1_phi are reference tables for the user to find the appropriate PLL dividers and multipliers

to achieve the desired PLL frequency. There is a tab for each PLL output because input frequencies and the range of acceptable

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NXP Semiconductors 9

divider/multiplier values differ between each other. However, they all follow the same setup. Note that Columns A, B, and C of

these tabs are frozen so if the table looks cut off, just scroll left or right.

PLL frequencies are calculated from a reference frequency, a reference divider (RFD), a multiplier (MFD), and in PLL0, a prescaler

(PREDIV). The PLL reference is not manually configurable because there are a finite number of input values the PLL can take.

For example, PLL0 can only reference either the 16 MHz IRCOSC or the 8-44 MHz XOSC. PLL reference therefore comes from

the Tree tab. Configure AUX Clock Selector 3 and AUX Clock Selector 4 in Tree for PLL0 and PLL1, respectively. Once the PLL

reference frequency is configured, enter the desired PLL output frequency. Also, enter the PREDIV value when using PLL0_PHI

or PLL0_PHI1. The reference table then calculates the output frequency for each MFD and RFD setting. Like in the other sections,

frequencies are color-coded to define which values are valid and which are not. Shading will change automatically once the output

PLL frequencies are calculated. MFD and RFD settings that achieve the exact desired frequency is marked in green; values that

exceed the desired frequency, but are within MPC5744P hardware specifications are marked in yellow; and frequencies that

exceed the MPC5744P hardware specification are colored red. Below is a screenshot of the reference table for PLL0_PHI.

Figure 14. PLL0_PHI reference table 2.6

2.7 Summary

Almost all blocks populating this clock calculator represent real register fields in silicon. The Summary tab collates all the

information from the rest of the clock calculator into a list of register values, a screenshot of which is shown in the following figure.

The values in the register summary are interactive, updating automatically when the associated block is changed. Registers listed

within Summary are only the ones whose values are affected by clock configuration, not every single register available in the SoC.

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MPC574xP Clock Calculator Guide, Rev. 9, April 2018

10 NXP Semiconductors

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