Digital Equipment PDF-10 User manual

PDF -10

System Reference Manual

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ORDER NO. DEC-10-HGAA-D FROM PROGRAM LIBRARY, MAYNARD, MASSACHUSETTS PRICE $5.00

DIRECT COMMENTS CONCERNING THIS MANUAL TO SOFTWARE QUALITY CONTROL, MAYNARD, MASSACHUSETTS

DIGITAL EQUIPMENT CORPORATION MAYNARD, MASSACHUSETTS

April 1968

Second printing, June 1968

Changes are indicated by a

triangle (A) in the outside margin.

Digital Equipment Corporation

Instruction times, operating speeds and the like are

included here for reference only; they are not to be

taken as specifications.

Written and designed for Digital Equipment Corporation by William English, Wayland, Massachusetts

Manufactured in the United States of America

Contents

1INTRODUCTION 1-1

1.1 Number System 1-4

Floating point arithmetic 1-5

1.2 Instruction Format 1-6

Effective address calculation 1-7

1.3 Memory 1-8

Memory allocation 1-9

1.4 Programming Conventions 1-10

2CENTRAL PROCESSOR 2-1

2. 1Half Word Data Transmission 2-2

2.2 Full Word Data Transmission 2-9

Move instructions 2-10

Pushdown list 2-12

2.3 Byte Manipulation 2-15

2.4 Logic 2-17

Shift and rotate 2-24

2.5 Fixed Point Arithmetic 2-26

Arithmetic shifting 2-3 1

2.6 Floating Point Arithmetic 2-32

Scaling 2-33

Operations with rounding 2-34

Operations without rounding 2-37

2.7 Arithmetic Testing 2-41

2.8 Logical Testing and Modification 2-47

2.9 Program Control 2-54

2.10 Unimplemented Operations 2-64

2. 11Programming Examples 2-65

Double precision floating point 2-67

2.12 Input-Output 2-68

Readin mode 2-72

Console data transfers 2-73

2.13 Priority Interrupt 2-73

2.14 Processor Conditions 2-78

3BASIC IN-OUT EQUIPMENT 3-1

3.1 Paper Tape Reader 3-1

Readin mode 3-4

3.2 Paper Tape Punch 3-5

3.3 Teletype 3-7

APPENDICES

AInstruction and Device Mnemonics A1

Numeric listing A3

Alphabetic listing A6

Device mnemonics A10

BIn-out Codes Bl

Teletype code B2

Card codes B6

CMiscellany Cl

Introduction

The PDF- 10 is ageneral purpose, stored program computer that includes a

central processor, amemory, and avariety of peripheral equipment such as

paper tape reader and punch, teletype, card reader, line printer, DECtape,

magnetic tape, disk file and display. The central processor is the control unit

for the entire system: it governs all peripheral in-out equipment, sequences

the program, and performs all arithmetic, logical and data handling opera-

tions. The processor is connected to one or more memory units by amem-

ory bus and to the peripheral equipment by an in-out bus. The fastest

devices, such as the disc file, although controlled by the processor over the

in-out bus, have direct access to memory over asecond memory bus.

The processor handles words of thirty-six bits, which are stored in amem-

ory with amaximum capacity of 262,144 words. Storage in memory is

usually in the form of 37-bit words, the extra bit producingoddparit^ for

the word. The bits of aword are numbered 0-35, left to right, as are the

bits in the registers that handle the words. The processor can also handle

half words, wherein the left half comprises bits 0-17, the right half, bits

18-35. Optional hardware is available for byte manipulation abyte is any

contiguous set of bits within aword. Registers that hold addresses have

eighteen bits, numbered 18-35 according to the position of the address in a

word. Words are used either as computer instructions in the program, as

addresses, or as operands (data for the program).

Of the internal registers shown in the illustration on the next page, only

PC, the 18 bit program counter, is directly relevant to the programmer. The

processor performs aprogram by executing instructions retrieved from the

locations addressed by PC. At the beginning of each instruction PC is incre-

mented by one so that it normally contains an address one greater than the

location of the current instruction. Sequential program flow is altered by

changing the contents of PC, either by incrementing it an extra time in a

skip instruction or by replacing its contents with the value specified by a

jump instruction. Also of importance to the programmer is the 36-bit data

switch register DS on the processor console: through this register the pro-

gram can read data supplied by the operator. The processor also contains

flags that detect various types of errors, including several types of overflow

in arithmetic and pushdown operations, and provide other information of

interest to the programmer.

The processor has other registers but the programmer is not usually con-

cerned with them except when manually stepping through aprogram to

debug it. By means of the address switch register AS, the operator can

1-1

1-2 INTRODUCTION

CORE MEMORY

8192 OR 16384

37-BIT WORDS

CORE MEMORY CORE MEMORY

MEMORY BUS

FAST

MEMORY

16 X36

MA 18

AS 18 PC 18

ARITHMETIC

LOGIC

(AR, BR, MQ)

IN-OUT BUS

CENTRAL

PROCESSOR

Ml 36

DS 36

PRIORITY

INTERRUPT PAPER TAPE

READER PAPER TAPE

PUNCH TELETYPE

PDP-10 SIMPLIFIED

examine the contents of, or deposit information into, any memory location;

stop or interrupt the program whenever aparticular location is referenced;

and through AS the operator can supply astarting address for the program.

Through the memory indicators MI the program can display data for the

operator. The instruction register IR contains the left half of the current

instruction word, ie all but the address part. The memory address register

MA supplies the address for every memory access. The heart of the proc-

essor is the arithmetic logic, principally the 36-bit arithmetic register AR.

1-3

This register takes part in all arithmetic, logical and data handling operations;

all data transfers to and from memory, peripheral equipment and console are

made via AR. Associated with AR are an extremely fast full adder, abuffer

instructions, amultiplier-quotient register MQ that serves primarily as an

extension of AR for handling double length operands, and smaller registers

that handle floating point exponents and control shift operations and byte

manipulation.

From the point of view of the programmer however the arithmetic logic

can be regarded as ablack box. It performs almost all of the operations

necessary for the execution of aprogram, but it never retains any informa-

tion from one instruction to the next. Computations performed in the black

box either affect control elements such as PC and the flags, or produce

results that are always sent to memory and must be retrieved by the proc-

essor if they are to be used as operands in other instructions.

An instruction word has only one 18-bit address field for addressing any

location throughout all of memory. But most instructions have two 4-bit

fields for addressing the first sixteen memory locations. Any instruction

that requires asecond operand has an accumulator address field, which can

address one of these sixteen locations as an accumulator; in other words as

though it were aresult held over in the processor from some previous

instruction (the programmer usually has achoice of whether the result of the

instruction will go to the location addressed as an accumulator or to that

addressed by the 18-bit address field, or to both). Every instruction has a

4-bit index register address field, which can address fifteen of these locations

for use as index registers in modifying the 18-bit memory address (a zero

index register address specifies no indexing). Although all computations on

both operands and addresses are performed in the single arithmetic register

AR, the computer actually has sixteen accumulators, fifteen of which can

double as index registers. The factor that determines whether one of the

first sixteen locations in memory is an accumulator or an index register is

not the information it contains nor how its contents are used, but rather

how the location is addressed. There need be no difference physically be-

tween these locations and other memory locations, but an optional, fast flip-

flop memory contained in the processor can be substituted for the bottom

sixteen locations in core. This allows much quicker access to these locations

whether they are addressed as accumulators, index registers or ordinary

memory locations. They can even be addressed from the program counter,

gaining faster execution for ashort but oft-repeated subroutine.

Besides the registers that enter into the regular execution of the program

and its instructions, the processor has apriority interrupt system and can

contain optional equipment to facilitate time sharing. The interrupt system

facilitates processor control of the peripheral equipment by means of anum-

ber of priority-ordered channels over which external signals may interrupt

the normal program flow. The processor acknowledges an interrupt request

by executing the instruction contained in aparticular location assigned to

the channel. Assignment of channels to devices is entirely under program

control. One of the devices to which the program can assign achannel is the

processor itself, allowing internal conditions such as overflow or aparity

1-4 INTRODUCTION 1.1

error to signal the program.

The time share hardware provides memory protection and relocation.

Without time sharing, all instructions and all memory are available to the

program. Otherwise anumber of programs share processor time, with each

program relocated and restricted to aspecific area in core, and certain in-

structions are usually illegal. An attempt by any user to execute an illegal

instruction or address amemory location outside of his area results in a

transfer of control back to the time-sharing monitor.

1.1 NUMBER SYSTEM

The program can interpret adata word as a36-digit, unsigned binary num-

ber, or the left and right halves of aword can be taken as separate 18-bit

numbers. The PDF- 1repertoire includes instructions that effectively add

or subtract one from both halves of aword, so the right half can be used for

address modification when the word is addressed as an index register, while

the left half is used to keep acontrol count.

The standard arithmetic instructions in the PDF- 10 use twos comple-

ment, fixed point conventions to do binary arithmetic. In aword used as a

number, bit (the leftmost bit) represents the sign, for positive, 1for

negative. In apositive number the remaining 35 bits are the magnitude in

ordinary binary notation. The negative of anumber is obtained by taking its

twos complement. If xis an -digit binary number, its twos complement is

2"-x, and its ones complement is(2"-l)-jc, or equivalently (2"-x) -1.

Subtracting anumber from 2"- 1(ie, from all Is) is equivalent to perform-

ing the logical complement, ie changing all Os to Is and all Is to Os. There-

fore, to form the twos complement one takes the logical complement

(usually referred to merely as the complement) of the entire word including

the sign, and adds 1to the result. In anegative number the sign bit is 1, and

the remaining bits are the twos complement of the magnitude.

+153, -+231 8-000000000000000000000000000010011001

-153,0 =-231 8=1111 111 111 111 111 111 111 111 111 101 100111

Zero is represented by aword containing all Os. Complementing this num-

ber produces all Is, and adding 1to that produces all Os again. Hence there

is only one zero representation and its sign is positive. Since the numbers are

symmetrical in magnitude about asingle zero representation, all even num-

bers both positive and negative end in 0, all odd numbers in 1(a number all

Is represents -1). But since there are the same number of positive and nega-

tive numbers and zero is positive, there is one more negative number than

there are nonzero positive numbers. This is the most negative number and it

cannot be produced by negating any positive number (its octal representa-

1.1 NUMBER SYSTEM 1-5

tion is 400000 0000008and its magnitude is one greater than the largest

positive number).

If ones complements were used for negatives one could read anegative

number by attaching significance to the Os instead of the Is. In twos com-

plement notation each negative number is one greater than the complement

of the positive number of the same magnitude, so one can read anegative

number by attaching significance to the rightmost 1and attaching signifi-

cance to the Os at the left of it (the negative number of largest magnitude has

a1in only the sign position). In anegative integer, Is may be discarded at

the left, just as leading Os may be dropped in a positive integer. In anegative

fraction, Os may be discarded at the right. So long as only Os are discarded,

the number remains in twos complement form because it still has a1that

possesses significance; but if aportion including the rightmost 1is discarded,

the remaining part of the fraction is now aones complement.

The computer does not keep track of abinary point the programmer

must adopt apoint convention and shift the magnitude of the result to con-

form to the convention used. Two common conventions are to regard a

number as an integer (binary point at the right) or as aproper fraction

(binary point at the left); in these two cases the range of numbers repre-

sented by asingle word is 235 to 235 -1or -1to 12~35 .Since multiplica-

tion and division make use of double length numbers, there are special

instructions for performing these operations with integral operands.

Floating Point Arithmetic. Optional PDF- 1hardware is available for

processing floating point numbers. Afloating point instruction interprets

bit of aword as the sign, but interprets the rest of the word as an 8-bit

exponent and a27-bit fraction. For apositive number the sign is 0, as

before. But the contents of bits 9-35 are now interpreted only as abinary

fraction, and the contents of bits 1-8 are interpreted as an integral exponent

in excess 128 (2008)code. Exponents from -128 to +127 are therefore

represented by the binary equivalents of to 255 (0-3778). Floatingpoint

zero and negatives are represented in exactly the same way as in fixed point:

zero by aword containing all Os, anegative by the twos complement. A

negative number has a1for its sign and the twos complement of the frac-

tion, but since every fraction must ordinarily contain a1unless the entire

number is zero (see below), it has the ones complement of the exponent

code in bits 1-8. Since the exponent is in excess 128 code, an actual

exponent xis represented in apositive number by x+128, in anegative

number by 127 -x. The programmer, however, need not be concerned with

these representations as the hardware compensates automatically. Eg, for

+153 10 =+231 8=+.4628X28-

1-6 INTRODUCTION 1.2

the instruction that scales the exponent, the hardware interprets the integral

scale factor in standard twos complement form but produces the correct

ones complement result for the exponent.

Except in special cases the floating point instructions assume that all non-

zero operands are normalized, and they normalize anonzero result. A

floating point number is considered normalized if the magnitude of the frac-

tion is greater than or equal to l

/2 and less than 1.These numbers thus have a

fractional range in magnitude of 1

A. to 1-2"27 and an exponent range of

-128 to +127. The hardware may not give the correct result if the program

supplies an operand that is not normalized or that has azero fraction with a

nonzero exponent.

The precaution about truncation given for fixed point multiplication

applies to all floating point operations as they all produce extra length

results; but here the programmer may request rounding, which automatically

restores the high order part to twos complement form if it is negative. In

division the two words of the result are quotient and remainder, but in the

other operations they form adouble length number which is stored in two

accumulators if the instruction is executed in "long" mode. This number

contains a54-bit fraction, half of which is in bits 9-35 of each word. The

sign and exponent are in bits and 1-8 respectively of the word containing

the more significant half, and the standard twos complement is used to form

In the remaining part of the less

8contain anumber 27 less than the

exponent, but this is expressed in positive form even though bits 9-35 may

be part of anegative fraction. Eg the number 218 +2~18 has this two-word

representation:

010

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