Atmel AVR ATmega103 User manual

Features

•Utilizes the AVR®RISC Architecture

•AVR – High-performance and Low-power RISC Architecture

– 121 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General-purpose Working Registers + Peripheral Control Registers

– Up to 6 MIPS Throughput at 6 MHz

•Data and Nonvolatile Program Memory

– 128K Bytes of In-System Programmable Flash

Endurance: 1,000 Write/Erase Cycles

– 4K Bytes Internal SRAM

– 4K Bytes of In-System Programmable EEPROM

Endurance: 100,000 Write/Erase Cycles

– Programming Lock for Flash Program and EEPROM Data Security

– SPI Interface for In-System Programming

•Peripheral Features

– On-chip Analog Comparator

– Programmable Watchdog Timer with On-chip Oscillator

– Programmable Serial UART

– Master/Slave SPI Serial Interface

– Real-time Counter (RTC) with Separate Oscillator

– Two 8-bit Timer/Counters with Separate Prescaler and PWM

– Expanded 16-bit Timer/Counter System with Separate Prescaler, Compare,

Capture Modes and Dual 8-, 9-, or 10-bit PWM

– Programmable Watchdog Timer with On-chip Oscillator

– 8-channel, 10-bit ADC

•Special Microcontroller Features

– Low-power Idle, Power-save and Power-down Modes

– Software Selectable Clock Frequency

– External and Internal Interrupt Sources

•Specifications

– Low-power, High-speed CMOS Process Technology

– Fully Static Operation

•Power Consumption at 4 MHz, 3V, 25°C

– Active: 5.5 mA

– Idle Mode: 1.6 mA

– Power-down Mode: < 1 µA

•I/O and Packages

– 32 Programmable I/O Lines, 8 Output Lines, 8 Input Lines

– 64-lead TQFP

•Operating Voltages

– 2.7 - 3.6V for ATmega103L

– 4.0 - 5.5V for ATmega103

•Speed Grades

– 0 - 4 MHz for ATmega103L

– 0 - 6 MHz for ATmega103

8-bit

Microcontroller

with 128K Bytes

In-System

Programmable

Flash

ATmega103(L)

Rev. 0945G–09/01

2ATmega103(L)

0945G–09/01

Pin Configuration TQFP

PC0 (A8)

VCC

GND

(ADC0) PF0

(ADC7) PF7

(ADC1) PF1

(ADC2) PF2

(ADC3) PF3

(ADC4) PF4

(ADC5) PF5

(ADC6) PF6

AREF

AGND

AVCC

6464

(PDI/RXD) PE0

(PDO/TXD) PE1

PEN

(AC+) PE2

(AC-) PE3

(INT4) PE4

(INT5) PE5

(INT6) PE6

(INT7) PE7

(SS) PB0

(SCK) PB1

(MOSI) PB2

(MISO) PB3

(OC0/PWM0) PB4

PB7 (OC2/PWM2)

TOSC2

(OC1B/PWM1B) PB6

TOSC1

(OC1A/PWM1A) PB5

PC1 (A9)

PD7 (T2)

PC2 (A10)

PC3 (A11)

PC4 (A12)

PC5 (A13)

PC6 (A14)

PC7 (A15)

PA7 (AD7)

ALE

PA6 (AD6)

PA5 (AD5)

PA4 (AD4)

PA3 (AD3)

(AD0) PA0

(AD1) PA1

(AD2) PA2

PD6 (T1)

PD5

PD4 (IC1)

PD3 (INT3)

PD2 (INT2)

PD1 (INT1)

PD0 (INT0)

XTAL1

XTAL2

RESET

GND

VCC

INDEX CORNER

ATmega103(L)

0945G–09/01

Description The ATmega103(L) is a low-power, CMOS, 8-bit microcontroller based on the AVR

RISC architecture. By executing powerful instructions in a single clock cycle, the

ATmega103(L) achieves throughputs approaching 1 MIPS per MHz, allowing the sys-

tem designer to optimize power consumption versus processing speed.

The AVR core is based on an enhanced RISC architecture that combines a rich instruc-

tion set with 32 general-purpose working registers. All the 32 registers are directly

connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be

accessed in one single instruction executed in one clock cycle. The resulting architec-

ture is more code efficient while achieving throughputs up to ten times faster than

conventional CISC microcontrollers.

The ATmega103(L) provides the following features: 128K bytes of In-System Program-

mable Flash, 4K bytes EEPROM, 4K bytes SRAM, 32 general-purpose I/O lines, 8 input

lines, 8 output lines, 32 general-purpose working registers, real-time counter (RTC), 4

flexible timer/counters with compare modes and PWM, UART, programmable watchdog

timer with internal oscillator, an SPI serial port and 3 software-selectable power saving

modes. The Idle mode stops the CPU while allowing the SRAM, timer/counters, SPI port

and interrupt system to continue functioning. The Power-down mode saves the register

contents but freezes the oscillator, disabling all other chip functions until the next inter-

rupt or hardware reset. In Power-save mode, the timer oscillator continues to run,

allowing the user to maintain a timer base while the rest of the device is sleeping.

The device is manufactured using Atmel’s high-density nonvolatile memory technology.

The On-chip ISP Flash allows the program memory to be reprogrammed in-system

through a serial interface or by a conventional nonvolatile memory programmer. By

combining an 8-bit RISC CPU with a large array of ISP Flash on a monolithic chip, the

Atmel ATmega103(L) is a powerful microcontroller that provides a highly flexible and

cost-effective solution to many embedded control applications.

The ATmega103(L) AVR is supported with a full suite of program and system develop-

ment tools including: C compilers, macro assemblers, program debugger/simulators, in-

circuit emulators and evaluation kits.

4ATmega103(L)

0945G–09/01

Block Diagram Figure 1. The ATmega103(L) Block Diagram

PROGRAM

COUNTER

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

STACK

POINTER

PROGRAM

FLASH

MCU CONTROL

SRAM

GENERAL

PURPOSE

REGISTERS

INSTRUCTION

TIMER/

COUNTERS

INSTRUCTION

DECODER

DATA DIR.

REG. PORTB

DATA DIR.

REG. PORTE

DATA DIR.

REG. PORTA

DATA DIR.

REG. PORTD

DATA REGISTER

PORTB

DATA REGISTER

PORTE

DATA REGISTER

PORTA

DATA REGISTER

PORTC

DATA REGISTER

PORTD

PROGRAMMING

LOGIC

TIMING AND

CONTROL

OSCILLATOR

INTERRUPT

UNIT

EEPROM

SPI UART

STATUS

ALU

PORTB DRIVER/BUFFERSPORTE DRIVER/BUFFERS

PORTA DRIVER/BUFFERS

PORTF BUFFERS

ANALOG MUX ADC

PORTD DRIVER/BUFFERS

PORTC DRIVERS

PB0 - PB7PE0 - PE7

PA0 - PA7PF0 - PF7

RESET

VCC

AGND

GND

AREF

TOSC2

TOSC1

XTAL1

CONTROL

LINES

ANALOG

COMPARATOR

PD0 - PD7

PC0 - PC7

PEN

ALE

8-BIT DATA BUS

AVCC

ATmega103(L)

0945G–09/01

Pin Descriptions

VCC Supply voltage.

GND Ground.

Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors

(selected for each bit). The Port A output buffers can sink 20 mA and can drive LED dis-

plays directly. When pins PA0 to PA7 are used as inputs and are externally pulled low,

they will source current if the internal pull-up resistors are activated.

Port A serves as Multiplexed Address/Data bus when using external SRAM.

The Port A pins are tri-stated when a reset condition becomes active, even if the clock is

not running.

Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port B output

buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low, will source

current if the pull-up resistors are activated.

Port B also serves the functions of various special features.

The Port B pins are tri-stated when a reset condition becomes active, even if the clock is

not running.

Port C (PC7..PC0) Port C is an 8-bit output port. The Port C output buffers can sink 20 mA.

Port C also serves as Address output when using external SRAM.

Since Port C is an output only port, the Port C pins are not tri-stated when a reset condi-

tion becomes active.

Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port D output

buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source

current if the pull-up resistors are activated.

Port D also serves the functions of various special features.

The Port D pins are tri-stated when a reset condition becomes active, even if the clock is

not running.

Port E (PE7..PE0) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port E output

buffers can sink 20 mA. As inputs, Port E pins that are externally pulled low will source

current if the pull-up resistors are activated.

Port E also serves the functions of various special features.

The Port E pins are tri-stated when a reset condition becomes active, even if the clock is

not running

Port F (PF7..PF0) Port F is an 8-bit input port. Port F also serves as the analog inputs for the ADC.

RESET Reset input. An external reset is generated by a low level on the RESET pin. Reset

pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter

pulses are not guaranteed to generate a reset.

XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2 Output from the inverting oscillator amplifier.

6ATmega103(L)

0945G–09/01

TOSC1 Input to the inverting Timer/Counter oscillator amplifier.

TOSC2 Output from the inverting Timer/Counter oscillator amplifier.

WR External SRAM write strobe

RD External SRAM read strobe

ALE ALE is the Address Latch Enable used when the External Memory is enabled. The ALE

strobe is used to latch the low-order address (8 bits) into an address latch during the first

access cycle, and the AD0-7 pins are used for data during the second access cycle.

AVCC Supply voltage for Port F, including ADC. The pin must be connected to VCC when not

used for the ADC. See “ADC Noise Canceling Techniques”on page 77 for details when

using the ADC.

AREF AREF is the analog reference input for the ADC converter. For ADC operations, a volt-

age in the range AGND to AVCC must be applied to this pin.

AGND If the board has a separate analog ground plane, this pin should be connected to this

ground plane. Otherwise, connect to GND.

PEN PEN is a programming enable pin for the serial programming mode. By holding this pin

low during a power-on reset, the device will enter the serial programming mode. PEN

has no function during normal operation.

Clock Options

Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier, which

can be configured for use as an on-chip oscillator, as shown in Figure 2. Either a quartz

crystal or a ceramic resonator may be used.

Figure 2. Oscillator Connections

Note: When using the MCU oscillator as a clock for an external device, an HC buffer should be

connected as indicated in the figure.

XTAL2

XTAL1

GND

MAX 1 HC BUFFER

ATmega103(L)

0945G–09/01

External Clock To drive the device from an external clock source, XTAL2 should be left unconnected

while XTAL1 is driven as shown in Figure 3.

Figure 3. External Clock Drive Configuration

Timer Oscillator For the Timer Oscillator pins, TOSC1 and TOSC2, the crystal is connected directly

between the pins. No external capacitors are needed. The oscillator is optimized for use

with a 32,768 Hz watch crystal. Applying an external clock source to TOSC1 is not

recommended.

XTAL2

XTAL1

GND

EXTERNAL

OSCILLATOR

SIGNAL

8ATmega103(L)

0945G–09/01

Architectural

Overview

Figure 4. The ATmega103(L) AVR RISC Architecture

The AVR uses a Harvard architecture concept –with separate memories and buses for

program and data. The program memory is accessed with a single-level pipeline. While

one instruction is being executed, the next instruction is pre-fetched from the program

memory. This concept enables instructions to be executed in every clock cycle. The pro-

gram memory is In-System Programmable Flash memory. With a few exceptions, AVR

instructions have a single 16-bit word format, meaning that every program memory

address contains a single 16-bit instruction.

During interrupts and subroutine calls, the return address program counter (PC) is

stored on the stack. The stack is effectively allocated in the general data SRAM and,

consequently, the stack size is only limited by the total SRAM size and the usage of the

SRAM. All user programs must initialize the SP in the reset routine (before subroutines

or interrupts are executed). The 16-bit stack pointer (SP) is read/write accessible in the

I/O space.

The 4000 bytes data SRAM can be easily accessed through the five different address-

ing modes supported in the AVR architecture.

A flexible interrupt module has its control registers in the I/O space with an additional

global interrupt enable bit in the status register. All the different interrupts have a sepa-

64K x 16

Program

Memory

Instruction

Decoder

Program

Counter

Control Lines

32 x 8

General

Purpose

Registers

ALU

Status

and Test

4K x 8

EEPROM

Peripherals

Data Bus 8-bit

AVR ATmega103(L) Architecture

4K x 8

Data

SRAM

Direct Addressing

Indirect Addressing

ATmega103(L)

0945G–09/01

rate interrupt vector in the interrupt vector table at the beginning of the

program memory. The different interrupts have priority in accordance with their interrupt

vector position. The lower the interrupt vector address, the higher the priority.

The memory spaces in the AVR architecture are all linear and regular memory maps.

General-purpose

Figure 5 shows the structure of the 32 general-purpose working registers in the CPU.

Figure 5. AVR CPU General-purpose Working Registers

All the register operating instructions in the instruction set have direct and single-cycle

access to all registers. The only exception are the five constant arithmetic and logic

instructions SBCI, SUBI, CPI, ANDI and ORI between a constant and a register and the

LDI instruction for load immediate constant data. These instructions apply to the second

half of the registers in the register file –R16..R31. The general SBC, SUB, CP, AND and

OR and all other operations between two registers or on a single register apply to the

entire register file.

As shown in Figure 5, each register is also assigned a data memory address, mapping

them directly into the first 32 locations of the user Data Space. Although not being phys-

ically implemented as SRAM locations, this memory organization provides great

flexibility in access of the registers, as the X-, Y-, and Z-registers can be set to index any

The 4K bytes of SRAM available for general data are implemented as addresses $0060

to $0FFF.

7 0 Addr.

R0 $00

R1 $01

R2 $02

.=.=.

R13 $0D

General R14 $0E

Purpose R15 $0F

Working R16 $10

Registers R17 $11

. . .

R26 $1A X-register low byte

R27 $1B X-register high byte

R28 $1C Y-register low byte

R29 $1D Y-register high byte

R30 $1E Z-register low byte

R31 $1F Z-register high byte

10 ATmega103(L)

0945G–09/01

X-register, Y-register and Z-

The registers R26..R31 have some added functions to their general-purpose usage.

These registers are address pointers for indirect addressing of the SRAM. The three

indirect address registers X, Y, and Z are defined as:

Figure 6. X-, Y-, and Z-registers

In the different addressing modes these address registers have functions as fixed dis-

placement, automatic increment and decrement (see the descriptions for the different

instructions).

ALU – Arithmetic Logic

Unit

The high-performance AVR ALU operates in direct connection with all the 32 general-

purpose working registers. Within a single clock cycle, ALU operations between regis-

ters in the register file are executed. The ALU operations are divided into three main

categories: arithmetic, logical and bit functions.

ISP Flash Program

Memory

The ATmega103(L) contains 128K bytes of On-chip In-System Programmable Flash

memory for program storage. Since all instructions are single or double 16-bit words, the

Flash is organized as 64K x 16. The Flash memory has an endurance of at least 1000

write/erase cycles.

Constant tables can be allocated in the entire program memory space (see the LPM –

Load Program Memory and ELPM –Extended Load Program Memory instruction

descriptions).

SRAM Data Memory The ATmega103(L) supports two different configurations for the SRAM data memory as

listed in Table 1.

Note: When using 64K of external SRAM, 60K will be available.

15 0

X-register 7 0 7 0

R27 ($1B) R26 ($1A)

15 0

Y-register 7 0 7 0

R29 ($1D) R28 ($1C)

15 0

Z-register 7 0 7 0

R31 ($1F) R30 ($1E)

Table 1. Memory Configurations

Configuration Internal SRAM Data Memory External SRAM Data Memory

A 4000 None

B 4000 up to 64K

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