Atmel AT90S8515-8PI User manual

Features

•Utilizes the AVR®RISC Architecture

•AVR - High-performance and Low-power RISC Architecture

– 118 Powerful Instructions - Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Up to 8 MIPS Throughput at 8 MHz

•Data and Nonvolatile Program Memory

– 4K/8K Bytes of In-System Programmable Flash

Endurance: 1,000 Write/Erase Cycles

– 256/512 Bytes of SRAM

– 256/512 Bytes of In-System Programmable EEPROM

Endurance: 100,000 Write/Erase Cycles

– Programming Lock for Flash Program and EEPROM Data Security

•Peripheral Features

– One 8-bit Timer/Counter with Separate Prescaler

– One 16-bit Timer/Counter with Separate Prescaler

Compare, Capture Modes and Dual 8-, 9- or 10-bit PWM

– On-chip Analog Comparator

– Programmable Watchdog Timer with On-chip Oscillator

– Programmable Serial UART

– Master/Slave SPI Serial Interface

•Special Microcontroller Features

– Low-power Idle and Power Down Modes

– External and Internal Interrupt Sources

•Specifications

– Low-power, High-speed CMOS Process Technology

– Fully Static Operation

•Power Consumption at 4 MHz, 3V, 25°C

– Active: 3.0 mA

– Idle Mode: 1.0 mA

– Power Down Mode: <1 µA

•I/O and Packages

– 32 Programmable I/O Lines

– 40-pin PDIP, 44-pin PLCC and TQFP

•Operating Voltages

– 2.7 - 6.0V (AT90S4414-4 and AT90S8515-4)

– 4.0 - 6.0V (AT90S4414-8 and AT90S8515-8)

•Speed Grades

– 0 - 4 MHz (AT90S4414-4 and AT90S8515-4)

– 0 - 8 MHz (AT90S4414-8 and AT90S8515-8)

Rev. 0841E–04/99

8-bit

Microcontroller

with 4K/8K

bytes In-System

Programmable

Flash

AT90S4414

AT90S8515

Pin Configurations

AT90S4414/8515

Description

The AT90S4414/AT90S8515 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By execut-

ing powerful instructions in a single clock cycle, the AT90S4414/8515 achieves throughputs approaching 1 MIPS per MHz

allowing the system designer to optimize power consumption versus processing speed.

Block Diagram

Figure 1. The AT90S4414/8515 Block Diagram

AT90S4414/8515

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly

connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction

executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times

faster than conventional CISC microcontrollers.

The AT90S4414/8515 provides the following features: 4K/8K bytes of In-System Programmable Flash, 256/512 bytes

EEPROM, 256/512 bytes SRAM, 32 general purpose I/O lines, 32 general purpose working registers, flexible

timer/counters with compare modes, internal and external interrupts, a programmable serial UART, programmable Watch-

dog Timer with internal oscillator, an SPI serial port and two software selectable power saving modes. The Idle Mode stops

the CPU while allowing the SRAM, timer/counters, SPI port and interrupt system to continue functioning. The power down

mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next external interrupt

or hardware reset.

The device is manufactured using Atmel’s high density nonvolatile memory technology. The on-chip in-system programma-

ble Flash allows the program memory to be reprogrammed in-system through an SPI serial interface or by a conventional

nonvolatile memory programmer. By combining an enhanced RISC 8-bit CPU with In-System Programmable Flash on a

monolithic chip, the Atmel AT90S4414/8515 is a powerful microcontroller that provides a highly flexible and cost effective

solution to many embedded control applications.

The AT90S4414/8515 AVR is supported with a full suite of program and system development tools including: C compilers,

macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.

Comparison Between AT90S4414 and AT90S8515

The AT90S4414 has 4K bytes of In-System Programmable Flash, 256 bytes of EEPROM and 256 bytes of internal SRAM.

The AT90S8515 has 8K bytes of In-System Programmable Flash, 512 bytes of EEPROM and 512 bytes of internal SRAM.

Table 1 summarizes the different memory sizes for the two devices.

Pin Descriptions

VCC

Supply voltage

GND

Ground

Port A (PA7..PA0)

Port A is an 8-bit bidirectional I/O port. Port pins can provide internal pull-up resistors (selected for each bit). The Port A

output buffers can sink 20mA and can drive LED displays directly. When pins PA0 to PA7 are used as inputs and are

externally pulled low, they will source current if the internal pull-up resistors are activated. The Port A pins are tri-stated

when a reset condition becomes active, even if the clock is not active.

Port A serves as Multiplexed Address/Data input/output when using external SRAM.

Table 1. Memory Size Summary

Part Flash EEPROM SRAM

AT90S4414 4K bytes 256 bytes 256 bytes

AT90S8515 8K bytes 512 bytes 512 bytes

AT90S4414/8515

Port B (PB7..PB0)

Port B is an 8-bit bidirectional I/O port with internal pull-up resistors. The Port B output buffers can sink 20 mA. As inputs,

Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are

tri-stated when a reset condition becomes active, even if the clock is not active.

Port B also serves the functions of various special features of the AT90S4414/8515 as listed on page 58.

Port C (PC7..PC0)

Port C is an 8-bit bidirectional I/O port with internal pull-up resistors. The Port C output buffers can sink 20 mA. As inputs,

Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are

tri-stated when a reset condition becomes active, even if the clock is not active.

Port C also serves as Address output when using external SRAM.

Port D (PD7..PD0)

Port D is an 8-bit bidirectional I/O port with internal pull-up resistors. The Port D output buffers can sink 20 mA. As inputs,

Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are

tri-stated when a reset condition becomes active, even if the clock is not active.

Port D also serves the functions of various special features of the AT90S4414/8515 as listed on page 64.

RESET

Reset input. A low level on this pin for more than 50 ns will generate a reset, even if the clock is not running. Shorter pulses

are not guaranteed to generate a reset.

XTAL1

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier

ICP

ICP is the input pin for the Timer/Counter1 Input Capture function.

OC1B

OC1B is the output pin for the Timer/Counter1 Output CompareB function

ALE

ALE is the Address Latch Enable used when the External Memory is enabled. The ALE strobe is used to latch the

low-order address (8 bits) into an address latch during the first access cycle, and the AD0-7 pins are used for data during

the second access cycle.

Crystal Oscillator

XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an

on-chip oscillator, as shown in Figure 2. Either a quartz crystal or a ceramic resonator may be used. To drive the device

from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 3.

AT90S4414/8515

Figure 2. Oscillator Connections

Note: When using the MCU Oscillator as a clock for an external device, an HC buffer should be connected as indicated in the figure.

Figure 3. External Clock Drive Configuration

Architectural Overview

The fast-access register file concept contains 32 x 8-bit general purpose working registers with a single clock cycle access

time. This means that during one single clock cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands

are output from the register file, the operation is executed, and the result is stored back in the register file - in one clock

cycle.

Six of the 32 registers can be used as three 16-bits indirect address register pointers for Data Space addressing - enabling

efficient address calculations. One of the three address pointers is also used as the address pointer for the constant table

look up function. These added function registers are the 16-bits X-register, Y-register and Z-register.

The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register

operations are also executed in the ALU. Figure 4 shows the AT90S4414/8515 AVR RISC microcontroller architecture.

In addition to the register operation, the conventional memory addressing modes can be used on the register file as well.

This is enabled by the fact that the register file is assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing

them to be accessed as though they were ordinary memory locations.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, Timer/Counters,

A/D-converters, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations

following those of the register file, $20 - $5F.

XTAL2

XTAL1

GND

MAX 1 HC BUFFER

AT90S4414/8515

The AVR uses a Harvard architecture concept - with separate memories and buses for program and data. The program

memory is executed with a two stage pipeline. While one instruction is being executed, the next instruction is pre-fetched

from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is

in-system programmable Flash memory.

With the relative jump and call instructions, the whole 2K/4K address space is directly accessed. Most AVR instructions

have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction.

During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is

effectively allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and

the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are

executed). The 16-bit stack pointer SP is read/write accessible in the I/O space.

The 256/512 bytes data SRAM can be easily accessed through the five different addressing modes supported in the AVR

architecture.

The memory spaces in the AVR

architecture are all linear and regular memory maps.

Figure 4. The AT90S4414/8515 AVR RISC Architecture

Data Bus 8-bit

2K/4K X 16

Program

Memory

Instruction

Decoder

Control Lines

Program

Counter Status

and Test

32 x 8

General

Purpose

Registers

ALU

256/512 x 8

Data

SRAM

Direct Addressing

Indirect Addressing

Control

Registers

Interrupt

Unit

SPI

Unit

Serial

Uart

8-bit

Timer/Counter

16-bit

Timer/Counter

with PWM

Watchdog

Timer

Analog

Comparator

I/O Lines

256/512 x 8

EEPROM

AT90S4414/8515

A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status

register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the pro-

gram memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the

interrupt vector address the higher the priority.

Figure 5. Memory Maps

$0000

Data Memory

Program Memory

32 Gen. Purpose

Working Registers $001F

$0020

$005F

$015F/$025F

$0060

$0160/$0260

$FFFF

64 I/O Registers

Internal SRAM

(256/512 x 8)

External SRAM

(0-64K X 8)

Program FLASH

(2K/4K x 16)

$000

$7FF/$FFF

AT90S4414/8515

General Purpose Register File

Figure 6 shows the structure of the 32 general purpose working registers in the CPU.

Figure 6. AVR CPU General Purpose Working Registers

All the register operating instructions in the instruction set have direct and single cycle access to all registers. The only

exception is the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI and ORI between a constant and a

registers in the register file - R16..R31. The general SBC, SUB, CP, AND and OR and all other operations between two

registers or on a single register apply to the entire register file.

As shown in Figure 6, each register is also assigned a data memory address, mapping them directly into the first 32 loca-

tions of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization

provides great flexibility in access of the registers, as the X,Y and Z registers can be set to index any register in the file.

X-Register, Y-Register And Z-Register

The registers R26..R31 have some added functions to their general purpose usage. These registers are address pointers

for indirect addressing of the Data Space. The three indirect address registers X, Y and Z are defined as:

Figure 7. X, Y and Z Registers

In the different addressing modes these address registers have functions as fixed displacement, automatic increment and

decrement (see the descriptions for the different instructions).

70Addr.

R0 $00

R1 $01

R2 $02

…

R13 $0D

General R14 $0E

Purpose R15 $0F

Working R16 $10

Registers R17 $11

…

R26 $1A X-register low byte

R27 $1B X-register high byte

R28 $1C Y-register low byte

R29 $1D Y-register high byte

R30 $1E Z-register low byte

R31 $1F Z-register high byte

15 0

X - register 7 0 7 0

R27 ($1B) R26 ($1A)

15 0

Y - register 7 0 7 0

R29 ($1D) R28 ($1C)

15 0

Z - register 7 0 7 0

R31 ($1F) R30 ($1E)

AT90S4414/8515

ALU - Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a

single clock cycle, ALU operations between registers in the register file are executed. The ALU operations are divided into

three main categories - arithmetic, logical and bit-functions.

In-System Programmable Flash Program Memory

The AT90S4414/8515 contains 4K/8K bytes on-chip In-System Programmable Flash memory for program storage. Since

all instructions are 16-or 32-bit words, the Flash is organized as 2K x 16/4K x 16. The Flash memory has an endurance of

at least 1000 write/erase cycles. The AT90S4414/8515 Program Counter (PC) is 11/12 bits wide, thus addressing the

2048/4096 program memory addresses.

See page 77 for a detailed description on Flash data downloading.

See page 10 for the different program memory addressing modes.

SRAM Data Memory - Internal and External

The following figure shows how the AT90S4414/8515 SRAM Memory is organized:

Figure 8. SRAM Organization

R0 $0000

R1 $0001

R2 $0002

……

R29 $001D

R30 $001E

R31 $001F

I/O Registers

$00 $0020

$01 $0021

$02 $0022

……

$3D $005D

$3E $005E

$3F $005F

Internal SRAM

$0060

$0061

…

$015E/$025E

$015F/$025F

External SRAM

$0160/$0260

$0161/$0261

…

$FFFE

$FFFF

AT90S4414/8515

The lower 352/608 Data Memory locations address the Register file, the I/O Memory and the internal data SRAM. The first

96 locations address the Register File + I/O Memory, and the next 256/512 locations address the internal data SRAM. An

optional external data SRAM can be placed in the same SRAM memory space. This SRAM will occupy the location follow-

ing the internal SRAM and up to as much as 64K - 1, depending on SRAM size.

When the addresses accessing the data memory space exceeds the internal data SRAM locations, the external data

SRAM is accessed using the same instructions as for the internal data SRAM access. When the internal data space is

accessed, the read and write strobe pins (RD and WR) are inactive during the whole access cycle. External SRAM opera-

tion is enabled by setting the SRE bit in the MCUCR register. See page 27 for details.

Accessing external SRAM takes one additional clock cycle per byte compared to access of the internal SRAM. This means

that the commands LD, ST, LDS, STS, PUSH and POP take one additional clock cycle. If the stack is placed in external

SRAM, interrupts, subroutine calls and returns take two clock cycles extra because the two-byte program counter is

pushed and popped. When external SRAM interface is used with wait state, two additional clock cycles is used per byte.

This has the following effect: Data transfer instructions take two extra clock cycles, whereas interrupt, subroutine calls and

returns will need four clock cycles more than specified in the instruction set manual.

The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with

Pre-Decrement and Indirect with Post-Increment. In the register file, registers R26 to R31 feature the indirect addressing

pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode features a 63 address locations reach from the base address given by the Y or

Z-register.

When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X,

Y and Z are decremented and incremented.

The 32 general purpose working registers, 64 I/O registers, the 256/512 bytes of internal data SRAM, and the 64K bytes of

optional external data SRAM in the AT90S4414/8515 are all accessible through all these addressing modes.

See the next section for a detailed description of the different addressing modes.

Program and Data Addressing Modes

The AT90S4414/8515 AVR RISC microcontroller supports powerful and efficient addressing modes for access to the pro-

gram memory (Flash) and data memory (SRAM, Register File and I/O Memory). This section describes the different

addressing modes supported by the

AVR

architecture. In the figures, OP means the operation code part of the instruction

word. To simplify, not all figures show the exact location of the addressing bits.

Figure 9. Direct Single Register Addressing

The operand is contained in register d (Rd).

This manual suits for next models

Table of contents

Other Atmel Microcontroller manuals

Atmel

Atmel ATmega128A-STK600 Installation and operating instructions

Atmel

Atmel AVR ATtiny10 Series User manual

Atmel

Atmel AVR 1908 User manual

Atmel

Atmel AVR128 Installation and operating instructions

Atmel

Atmel AVR4901 Installation and operating instructions

Atmel

Atmel ATmega161 User manual

Atmel

Atmel AT97SC3205T-SDK2 User manual

Atmel

Atmel STK512 User manual

Atmel

Atmel AVR1014 User manual

Atmel

Atmel ATBTLC1000 BluSDK User manual

Atmel

Atmel AT90USB162 User manual

Atmel

Atmel AVR XMEGA AU series User manual

Atmel

Atmel AT90S1200 User manual

Atmel

Atmel AT32UC3 Series Installation and operating instructions

Atmel

Atmel SAM4L Xplained Pro User manual

Atmel

Atmel SAM L21 Xplained Pro User manual

Atmel

Atmel ATmega48A User manual

Atmel

Atmel AT40K Installation and operating instructions

Atmel

Atmel AT89C52 User manual

Atmel

Atmel UC3-L0 Xplained Installation and operating instructions

Atmel

Atmel 8051 User manual

Atmel

Atmel AT32UC3L064 User manual

Atmel

Atmel AVR AVR350 Installation and operating instructions

Atmel

Atmel SAM D09 Installation and operating instructions

Popular Microcontroller manuals by other brands

AMS

AMS AS7261 Demo Kit user guide

Novatek

Novatek NT6861 manual

Espressif Systems

Espressif Systems ESP8266 SDK AT Instruction Set

Nuvoton

Nuvoton ISD61S00 ChipCorder Design guide

STMicrolectronics

STMicrolectronics ST7 Assembler Linker user manual

Texas Instruments

Texas Instruments Chipcon CC2420DK user manual

Lantronix

Lantronix Intrinsyc Open-Q 865XR SOM user guide

NEC

NEC 78GK0S/K 1+ Series Application note

Mikroe

Mikroe SEMITECH N-PLC Click Application note

Intel

Intel Agilex user guide

Cypress

Cypress CY4607 HX2VL quick start guide

DIGITAL-LOGIC

DIGITAL-LOGIC MICROSPACE manual

Texas Instruments

Texas Instruments TMS320F2837 D Series Workshop Guide and Lab Manual

CYPRES

CYPRES CY14NVSRAMKIT-001 user guide

Texas Instruments

Texas Instruments INA-DUAL-2AMP-EVM user guide

Espressif Systems

Espressif Systems ESP8266EX Programming guide

Abov

Abov AC33M8128L user manual

Laird

Laird BL654PA user guide