Western Digital TN-55 User manual

J U L Y 1 9 9 8

WRL

Technical Note TN-55

The Memory

Daughter-Card

Version 1.5

User’s Manual

Marc A. Viredaz

d i gi t a l

Western Research Laboratory 250 University Avenue Palo Alto, California 94301 USA

The Western Research Laboratory (WRL) is a computer systems research group that

was founded by Digital Equipment Corporation in 1982. Our focus is computer science

research relevant to the design and application of high performance scientific computers.

We test our ideas by designing, building, and using real systems. The systems we build

are research prototypes; they are not intended to become products.

There are two other research laboratories located in Palo Alto, the Network Systems

Lab (NSL) and the Systems Research Center (SRC). Another Digital research group is

located in Cambridge, Massachusetts (CRL).

Our research is directed towards mainstream high-performance computer systems. Our

prototypes are intended to foreshadow the future computing environments used by many

Digital customers. The long-term goal of WRL is to aid and accelerate the development

of high-performance uni- and multi-processors. The research projects within WRL will

address various aspects of high-performance computing.

We believe that significant advances in computer systems do not come from any single

technological advance. Technologies, both hardware and software, do not all advance at

the same pace. System design is the art of composing systems which use each level of

technology in an appropriate balance. A major advance in overall system performance

will require reexamination of all aspects of the system.

We do work in the design, fabrication and packaging of hardware; language processing

and scaling issues in system software design; and the exploration of new applications

areas that are opening up with the advent of higher performance systems. Researchers at

WRL cooperate closely and move freely among the various levels of system design. This

allows us to explore a wide range of tradeoffs to meet system goals.

We publish the results of our work in a variety of journals, conferences, research

reports, and technical notes. This document is a technical note. We use this form for

rapid distribution of technical material. Usually this represents research in progress.

Research reports are normally accounts of completed research and may include material

from earlier technical notes.

Research reports and technical notes may be ordered from us. You may mail your

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DEC Western Research Laboratory, WRL-2

250 University Avenue

Palo Alto, California 94301 USA

Reports and technical notes may also be ordered by electronic mail. Use one of the fol-

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To obtain more details on ordering by electronic mail, send a message to one of these

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Reports and technical notes may also be accessed via the World Wide Web:

http://www.research.digital.com/wrl/home.html.

The Memory Daughter-Card Version 1.5

User's Manual

Marc A. Viredaz

July 1998

Abstract

The

memory daughter-card

is memory extension b oard for the

Itsy pocket computer

develop ed at

Compaq Computer Corp oration's

Western Research Laboratory (WRL)

. It provides an additional

bank of ash memory and up to three additional banks of DRAM. It is possible to b o ot from this

daughter-card. This document describes the architecture and the low-level programming mo del of

the memory daughter-card.

Revision 1.0

The Memory Daughter-Card Version 1.5 : User's Manual

Contents

Disclaimer 1

1 Intro duction 1

1.1 Purp ose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.3 Notations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2 Architecture 2

2.1 Memory system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.1.1 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.1.2 Dynamic RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3 Programmer's mo del 4

3.1 Memory daughter-card general-purp ose input/output signals . . . . . . . . . . . . . 4

3.2 Non-volatile memory identication structure . . . . . . . . . . . . . . . . . . . . . . . 5

References 5

List of Figures

1 Architecture of the memory daughter-card . . . . . . . . . . . . . . . . . . . . . . . . 2

List of Tables

1 Memory daughter-card general-purp ose input/output signals . . . . . . . . . . . . . 4

WRL, Compaq

iii

The Memory Daughter-Card Version 1.5 : User's Manual

Disclaimer

Compaq Computer Corp oration b elieves the information included in this pub-

lication is correct as of the date of publication. Such information is sub ject to

change without notice. Compaq is not resp onsible for inadvertent errors.

Compaq makes no representations that the use of its pro ducts in the man-

ner describ ed in this publication will not infringe on existing or future patent

rights, nor do the descriptions contained in this publication imply the granting

of licenses to make, use, or sell equipment or software in accordance with the

description.

1 Intro duction

This do cument describ es the architecture and the programmer's mo del of the

memory daughter-

card

for the

Itsy pocket computer

[Vir98]. It should b e considered as a guide for low-level software

develop ers.

A go o d understanding of the Itsy computer [Vir98] is assumed throughout this report.

1.1 Purp ose

The design of the memory daughter-card was aimed at achieving several goals :



Provide additional ash memory and DRAM (memory extension).



Be usable as a \safety daughter-card," i.e., it should b e p ossible to bo ot from the daughter-

card, in order to recover from a corrupted mother-b oard ash memory.



Be usable as a system test and debug platform, i.e., it should be p ossible to boot from the

daughter-card and use so ckets for the ash memory, so that it can b e programmed with an

external programmer.



Provide a prototyping platform to interface additional hardware to the Itsy computer.

1.2 History

The rst

printed-circuit board (PCB)

, referred to as

memory daughter-card version 1.0

, was com-

pleted in November 1997. This rst prototyp e had a few minor aws, all of which could b e corrected.

The logic design corresponding to a mo died (i.e., patched) version 1.0 b oard is known as

memory

daughter-card version 1.1

. This design corresponds only to a set of schematics, no physical PCB

having b een manufactured.

A second prototype, named

memory daughter-card version 1.5

was complete in July 1998.

It corresp onds to a version 1.1 system with a few additional features. From the programmer's

p oint-of-view, there are almost no dierences between the versions 1.1 and 1.5.

This do cument describ es the memory daughter-card version 1.5. All relevant dierences b etween

the versions 1.1 and 1.5 are outlined in foot-notes.

WRL, Compaq

The Memory Daughter-Card Version 1.5 : User's Manual

16 Mbyte

Flash

Memory

4 Mbyte

RS-232

IrDA

Power

Mother

Board Screen

Touch

200 x 320

15 Gray L.

LCD

Processor

StrongARM

SA-1100

Interface

Analog

DRAM

16 Mbyte

Memory

Card

DRAM

Daughter

Flash

Memory

4 Mbyte

Telecom.

Codec

Points

Access

Memory

Bus

A/D

GPIO

SSP

SDLC

UART

USB

Figure 1: Architecture of the memory daughter-card.

1.3 Notations

In this rep ort, electrical signals are represented as upp er-case names in a sans-serif font (e.g.,

PWR EN

). Active-low signals are denoted byover-lines (e.g.,

RESET OUT

), while buses and element

of buses are specied by subscripts (e.g.,

DCD

DCA

). In the schematics, the same signals are

represented using the syntax and conventions of the WindowSIL [Tha97 ] CAD to ols. For example,

the signal

DCCS

app ears as

~dccs[2]

2 Architecture

Figure 1 presents the architecture of the memory daughter-card (right part), shown in resp ect to

the Itsy computer (left part). The memory daughter-card versions 1.1 and 1.5 are b oth compatible

with both versions of the Itsy mother-b oard (i.e., versions 1.1 and 1.5).

2.1 Memory system

The memory daughter-card features a

ash memory

deco ded as static-memory bank 2 and the

three

dynamic random-access memory (DRAM)

banks 1, 2, and 3. Dep ending on the application's

WRL, Compaq

The Memory Daughter-Card Version 1.5 : User's Manual

needs, only some of these banks (or even none) might be present. Since this daughter-card is

b o otable, the ash memory is also deco ded as static-memory bank 0, from which the StrongARM

SA-1100 processor [DEC98] b o ots.

2.1.1 Flash memory

A pair of 16-bit ash-memory circuits implement the 32-bit ash memory. These circuits can be

either soldered on the b oard or put in

zero insertion force (ZIF) sockets

. Many dierent devices

can b e accommo dated :

AMD Am29LV160B

OssPT

[AMD97e]

AMD Am29LV800

ss P T

/Am29LV800B

OssPT

[AMD97c, AMD97d]

AMD Am29LV400

ss P T

[AMD97a ]

AMD Am29LV200

ss P T

[AMD97b]

Hitachi HN29V

800

/HN29W

800

[Hit97c, Hit97d]

Motorola M29F800A2

OPss

/M29F800A3

OPss

[Mot97]

Sharp LH28F800SG

-L

[Sha97]

where \

" sp ecies the internal sector organization, \

" sp ecies the sp eed, \

" sp ecies the

package, and \

" sp ecies the temp erature range. Any other compatible parts can also b e used.

Following the Itsy static-memory identication scheme [Vir98], a non-volatile memory identi-

cation structure describ es the characteristics of the sp ecic parts used on a given daughter-card

and hence allows the software to congure the memory interface correctly.

The

reset/power-down pin

of the ash-memory circuits is asserted (0) during a reset (i.e.,

hardware, software, or watch-dog reset) and during sleep mo de. When the ash memory do es not

need to b e accessed, this signal can also be asserted (0) by setting the signal

GPIO

(

DCFLFOFF

)

to 0 (see Section 3.1).

When the Itsy computer must boot from the daughter-card, this signal

should never b e set to 0 during sleep mode, since the pro cessor would be unable to read the b o ot

memory up on wake up. This can easily be achieved by setting bit 16 of the

power manager GPIO

sleep state register

PGSR

of the StrongARM SA-1100 pro cessor [DEC98] to 1.

The

ready/not-busy pins

of the ash-memory circuits can b e monitored using the signals

GPIO

(

DCFL0RY

), for the least signicant16data bits

, and

GPIO

(

DCFL1RY

), for the

most signicant 16 data bits

(see Section 3.1).

The hardware write-protection mechanism, featured by some of the supp orted parts, is never

used, and the corresp onding pin is always de-asserted (1). However, it is still possible to protect

the ash memory against write accesses, by using the jumper provided for this purpose. The ash

memory is protected when this jump er is open and is writable when this jump er is short-circuited.

2.1.2 Dynamic RAM

Three pairs of 64 Mbit (i.e., 2

rows



columns



16 bits) self-refresh DRAM circuits implement

the three 32-bit DRAM banks. Many dierent

fast-page mode

enhanced data out (EDO)

devices

can b e accommo dated :

On the memory daughter-card version 1.1, the reset/p ower-down pins are only asserted (0) during sleep mo de or

when the signal

GPIO

(

DCFLFOFF

) is set to 0.

WRL, Compaq

The Memory Daughter-Card Version 1.5 : User's Manual

Signal Name Function Dir. Def.

GPIO

DCFLFOFF

aughter-

ard



ash memory

orce

o

O 1

GPIO

DCFL0RY

aughter-

ard



ash memory

ead

GPIO

DCFL1RY

aughter-

ard



ash memory

ead

Table 1: Memory daughter-card general-purp ose input/output signals.

Hitachi HM5165160ALTT-

[Hit97a]

Hitachi HM5165165ALTT-

[Hit97b]

Samsung KM416V4100AS-L

/KM416V4100BS-L

[Sam97a, Sam98a]

Samsung KM416V4104AS-L

/KM416V4104BS-L

[Sam97b, Sam98b]

Toshiba TC5165165AFTS-

[Tos96 ]

where \

" sp ecies the sp eed. Any other compatible parts can also b e used.

Since all DRAM banks must b e accessed at the sp eed of the slowest one, it is b est to use the

same devices as on the Itsy mother-board, that is, 50 ns EDO DRAM circuits (KM416V4104AS-L5 ,

KM416V4104BS-L5 , or TC5165165AFTS-50 ).

3 Programmer's mo del

This section presents additional information on the mo del that the low-level software has of the

memory daughter-card hardware.

3.1 Memory daughter-card general-purp ose input/output signals

Table 1 shows the general-purpose input/output signals used on the memory daughter-card. Both

input signals can be used as interrupts. After a hardware reset (i.e., power-up or push-button

reset), all input/output signals are congured as input. Therefore, a pull-up resistor is used to

provide a default value to the signal

GPIO

(

DCFLFOFF

), as shown in the last column of Table 1.

The function of all signals are :

GPIO

DCFLFOFF

: D

aughter-

ard



ash memory

orce

o

This output signal is used to control the reset/p ower-down pin of the ash-memory circuits

(see Section 2.1.1). When this signal is set to 0, the reset/p ower-down pins are asserted (0).

When it is set to 1, the reset/p ower-down pins are only asserted (0) during a reset (i.e.,

hardware, software, or watch-dog reset) and during sleep mo de.

A pull-up resistor sets the

default value of this signal to 1 when the

GPIO

pin is congured as input (e.g., after a

hardware reset). When the Itsy computer must boot from the daughter-card, this signal

should never be set to 0 during sleep mo de, since the pro cessor would be unable to read

the b o ot memory up on wake up. This can b e easily achieved by setting bit 16 of the

power

manager GPIO sleep state register

PGSR

of the StrongARM SA-1100 pro cessor [DEC98] to 1.

On the memory daughter-card version 1.1, the reset/power-down pins are only asserted (0) when this signal is

set to 0 and during sleep mode.

WRL, Compaq

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