Texas Instruments XIO2001 User manual
XIO2001
Evaluation Module (EVM)
User's Guide
Literature Number: SCPU031A
February 2009–Revised December 2012
Contents
1 Read This First ................................................................................................................... 3
1.1 About This Manual ...................................................................................................... 3
1.2 How to Use This Manual ............................................................................................... 3
1.3 Information About Cautions and Warnings ........................................................................... 3
1.4 Related Documentation from Texas Instruments ................................................................... 3
2 Overview ............................................................................................................................ 4
3 EVM Features ..................................................................................................................... 4
3.1 PCI Express Connector ................................................................................................. 4
3.2 PCI Add-In Slots ......................................................................................................... 4
3.3 EEPROM Interface ...................................................................................................... 5
3.4 Test Header .............................................................................................................. 5
3.5 Clock Run (CLKRUN) ................................................................................................... 6
3.6 JTAG Header ............................................................................................................ 6
3.7 LEDs ...................................................................................................................... 6
4 FAQ/Troubleshooting .......................................................................................................... 7
4.1 BIOS Fails to Assign Memory Window to Bridge ................................................................... 7
4.2 ×16 Slots Only Support INTA .......................................................................................... 7
4.3 System Turns On When PCI Card Is Inserted Into EVM Or When EVM Is Plugged Into Slot ................ 7
4.4 What To Do If EVM Is Not Working ................................................................................... 8
5 Schematics ......................................................................................................................... 9
6 Bill of Materials ................................................................................................................. 13
2Table of Contents SCPU031A–February 2009–Revised December 2012
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User's Guide
SCPU031A–February 2009–Revised December 2012
XIO2001 Evaluation Module (EVM)
1 Read This First
1.1 About This Manual
This manual describes the operation of the XIO2001 evaluation module (EVM) from Texas Instruments.
1.2 How to Use This Manual
This document contains the following sections:
•Overview
•EVM Features
•FAQ/Troubleshooting
•Schematics
•Bill of Materials
1.3 Information About Cautions and Warnings
This manual may contain cautions and warnings.
CAUTION
This is an example of a caution statement.
A caution statement describes a situation that could potentially damage your
software or equipment.
WARNING
This is an example of a warning statement.
A warning statement describes a situation that could potentially
cause harm to you.
1.4 Related Documentation from Texas Instruments
Table 1 contains a list of data manuals that have detailed descriptions of the integrated circuits used in the
design of the TAS3208EVM-LC. The data manuals can be obtained at www.ti.com.
3
SCPU031A–February 2009–Revised December 2012 XIO2001 Evaluation Module (EVM)
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FAQ/Troubleshooting
www.ti.com
4.4 What To Do If EVM Is Not Working
4.4.1 Check EVM Power
Diodes LED1, LED2, LED4 and LED5 show the status of the 5-V, 3.3-V, 12-V, and –12-V rails,
respectively. 1.5 V may be probed on the top pad of C44 (directly next to U3), and –12 V may be probed
from C100. A ground reference is available at J1 pin 11 and JP1 pins
www.ti.com
Schematics
range will not be claimed by the bridge. The I/O window for the XIO2001 has a minimum size of 4
KBytes and is naturally 4K-aligned. Typically, most systems use only 16-bit addressing for I/O
transactions, so the upper base and limit registers remain 0.
• Memory base and memory limit registers – PCI offsets 0×20 and 0×22 : Similar to the I/O base and
limit registers, the bridge must be programmed with a memory address window containing the
nonprefetchable memory resources of all downstream PCI devices requiring nonprefetchable memory.
Memory windows have a minimum size of 1 MByte and are naturally 1M-aligned. The bridge does not
claim either a memory transaction initiated from upstream that does not fall within its memory window
nor memory transactions initiated downstream that do fall within its memory window.
• Prefetchable memory base, prefetchable memory limit, prefetchable base upper 32-bit, and
prefetchable limit upper 32-bit registers – PCI offsets 0x24, 0x26, 0x28, and 0×2C: Identical to the
memory base and limit registers but for prefetchable memory resources. The prefetchable base upper
32-bit, and prefetchable limit upper 32-bit registers are only used if 64-bit addressing is in use and in
most systems both of these registers will remain all zeroes. If 64-bit addressing is desired and the
memory window for devices behind the XIO2001 resides all or in part in 64-bit memory space then the
prefetchable base upper 32-bit register will combine with the prefetchable base register and the
prefetchable limit upper 32-bit register will combine with the prefetchable limit register to create 64-bit
base and limit registers. All memory addresses between the two addresses will be considered to be
located behind the bridge.
• For all base and limit registers any case in which the limit register contains a lower address than the
base register will be considered invalid. In this situation the bridge will react as if all resources of that
type resided upstream of the bridge. The bridge will respond to all downstream transactions of that
type with Unsupported Request and will claim and forward upstream any transactions of that type that
initiate on the PCI bus.
Depending on desired functionality, other PCI registers on the XIO2001 may have to be configured.
Consult the XIO2001 Data Manual for a description of the previous registers or for any other XIO2001
registers.
4.4.4 Check Devices Downstream From Bridge
Once the bridge is communicating and is properly configured, check if devices downstream from the
bridge have been configured as required. Check the Windows Device Manager to determine if the device
drivers have been loaded or if other problems exist with the device. Once you have performed these
checks, you can perform PCI transactions on the bus and examine them with any standard PCI analyzer.
5 Schematics
Schematics for the XIO2001 EVM are shown on the following pages.
9
SCPU031A–February 2009–Revised December 2012 XIO2001 Evaluation Module (EVM)
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Pull Ups/Pull DownsBridge Power
Filtering/Decoupling
Schematics
www.ti.com
10 XIO2001 Evaluation Module (EVM) SCPU031A–February 2009–Revised December 2012
Submit Documentation Feedback
Copyright © 2009–2012, Texas Instruments Incorporated
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