Texas Instruments 990 User manual

TEXAS

INSTRUMENTS

Improving Man's Effectiveness Through Electronics

Model

990

Computer

lnput/16

Output TTL Data Module

Depot Maintenance Manual.

MANUAL

NO. 945407-9701

ORIGINAL

ISSUE

1 AUGUST 1976

Digital Systems Division

Texas

Instruments Incorporated

1976

All

Rights

Reserved

The

infonnation and/or

drawings

set

forth

this

document

and

all

rights in

and

to inventions disclosed herein

and

patents

which

might

granted thereon disclos-

ing

employing

the materials,

methods,

techniques or apparatus described herein

are the exclusive property of

Texas

Instruments Incorporated.

INSERT

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EFFECTIVE

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portion of the text affected

the

changes

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in the outer

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Model 990 Computer 16 Input/16 Output TTL Data Module Depot Maintenance

Manual (945407-9701)

Original Issue 1 August 1976

Total

number

pages

this

publication

consisting

the

following:

PAGE

NO.

Cover

Eff. Pages .

iii -

1-1

-1-6

2-1

-2-2

3-1

-3-2

4-1

-4-10 .

5-1

-5-8

Alphabetical Index Div

Index-I -lndex-2

User's Resp

Bus. Reply

Cover Blank .

Cover

CHANGE

PAGE

NO.

CHANGE

NO. PAGE

NO.

CHANGE

NO.

Jdl.J\

______

945407-9701

PREFACE

This manual provides maintenance instructions for the Texas Instruments 16

Input/

Output

TTL Data Module. The manual also provides the theory

operation for the module. The

information in the manual

divided into the following sections:

I. General Description -This section briefly describes the module, including its operation

and characteristics.

II. Installation -This section provides instructions for unpacking, inspecting, and

installing the module into a Model

990

Computer mainframe or expansion chassis.

III. Operating Instructions -This section provides programming instructions for

the

module and a description

how the software controls the operation

the module.

IV.

Theory

Operation -This section contains detailed block diagrams

the data

module, describes the module's interfaces with the Model 990 Computer and a

peripheral device, and provides a discussion

the

module's operation.

Maintenance -This section provides troubleshooting and fault isolation procedures for

the module.

Alphabetical Index -The alphabetical index provides an alphabetical listing

key

words and concepts within the manual and locates them for easy reference.

Additional information related

the

Input/16

Output

TTL Data Module may be found in

the following documents:

Title

990 Computer Family Systems Handbook

Model 990/4 Computer System Hardware Reference

Manual

Model 990/10 Computer System Hardware Reference

Manual

Model 990 Computer Family Maintenance Drawings

iii/iv

Part

Number

945250-9701

945251-9701

945417-9701

945421-9701

and

945421-9702

Digital

Systems

Division

Jd75l

______

945407-9701

Paragraph

1.1

1.2

1.2.1

1.2.2

1.2.3

1.3

1.4

1.5

2.1

2.2

2.3

2.4

3.1

3.2

4.1

4.2

4.2.1

4.3

4.3.1

4.3.2

4.3.3

4.4

5.1

5.2

5.3

5.4

5.4.1

TABLE OF CONTENTS

Title

SECTION

GENERAL DESCRIPTION

General

.....

Equipment Overview

Transmit Mode

Receive Mode . _

Interrupt

Response

Physical Characteristics

Electrical Characteristics

Module Address . . .

SECTION II. INSTALLATION

General

Unpacking

Inspection

Installation

SECTION III. OPERATING INSTRUCTIONS

General . . .

Programming

SECTION IV. THEORY

OPERATION

General

.....

Data Module

Input

Logic .

Multiplexer . . . . . .

Data Module

Output

Logic

Output

Decoder . . . .

Output

Flip-Flops . . .

Output

Transistors . . .

Data Module

Interrupt

Logic

SECTION V. MAINTENANCE

General

Maintenance Philosophy

Special Test Equipment

Troubleshooting Procedures

Scoping Loops . . . . .

Page

1-2

1-3

1-5

2-1

2-2

3-1

4-1

4-8

5-1

5-4

Digital

Systems

Division

~~-~~~~~~~---

945407-9701

Figure

1-1

1-2

1-3

4-1

4-2

4-3

4-4

4-5

4-6

5-1

5-2

Table

1-1

1-2

1-3

2-1

4-1

4-2

5-1

5-2

5-3

LIST

ILLUSTRATIONS

Input/16

Output

TTL

Data Module

Simplified

Control

System Example

Title

Simplified 16

lnput/16

Output

Data Module Diagram

Data Module

Input

Circuit and Timing

Data Selector/Multiplexer . . . . . . . .

Data Module

Output

Flip-Flop and Timing

4-Line-to-16-Line Decoder/Multiplexer

Dual D-Type Positive-Edge-Triggered Flip-Flops with Preset and Clear

Edge Triggered

Interrupt

Generation Logic

and

Signals

Model

990/4

Computer

Hot

Mockup System

Model

990/10

Computer

Hot

Mockup System . . . .

LIST

TABLES

CRU

Interface Pin Assignments

External

Connector

Pin Assignment

Title

16 I/O

TTL

Data Module Electrical Characteristics

Jumper

Connections

Multiplexer

Input

Select for CRUBIT12-15

Decoder

Output

Select for

CRUBITl

2-15

Test Procedures . . . . . .

Output

Line Reference Chart

Input

Line Reference

Chart

Page

1-1

1-2

1-4

4-2

4-4

4-5

4-7

4-8

4-9

5-2

5-3

Page

1-5

1-6

2-1

4-3

4-6

5-5

5-6

Digital

Systems

Division

J2r75'

______

945407-9701

SECTION I

GENERAL

DESCRIPTION

1.1

GENERAL

The 16

Input/16

Output

TTL

Data Module (see figure 1-1) provwes a two-way

communication

path

between

a Texas

Instruments

990

Computer

and

attached

peripheral devices which are

operated

which genernte

TTL

level digital signals. l

module

may

be used in

any

Communications Register Unit (CRU)

port

within

the

CPU chassis,

may

used in a CRU

expansion chassis.

The

module

provides

input

and

output

lines. Each line

may

addressed

a single

independent

binary value

as a

member

group

from

lines"

Alternate

versions

the

module

provide 15

normal

inputs, 14

normal

outputs,

interrupt

line,

and

interrupt

mask. Data

module

inputs

and

outputs

are negative logic levels

that

switch

between

0 volts

and

positive voltage level. Each

output

is an

open

collector

transistor

capable

sinking

milliamperes at

volts. Pads are available

the

module

for installing pull-up resistors

resistor divider

networks

at each

output

the

module.

Each

input

connected

the

base

an emitter-follower

transistor

that

operates

TTL

levels. Pads

for

input

filter

capacitors

are also

available

the

module.

Use

the

data

module

in a simplified

control

system

shown

in figure 1-2. In this example,

the

computer

and

the

data

module

combine

sense

the

level

fluid in a storage

tank

and

control

the

operation

input

valve

reference levels. When

the

fluid reaches

one

the

prescribed references, an

interrupt

and an

FLOW

IN*

OPEN!CLOSE

OPEN/CLOSE

VALVE

lt..1011""1""

I~,

r U I

VALVE

161/0

DATA

MODULE

MODEL

TANK

FULL

990

COMPUTER

INTERRUPT

STORAGE

TANK

FULL

FLOW

TANK

LOW

OUT

*FLOW

IN >

FLOW

OUT

(A)129473

Figure 1-2. Simplified Control System Example

1-1

Digital

Systems Division

945407-9701

1-2

::I

Q..

::I

§"

-I

Digital

Systems Division

Jd15'

______

945407-9701

indication

which condition

(tank

low

tank

full) caused

the

interrupt are generated. The

seivice routine handling

the

storage

tank

system

then

uses

the

input

data

develop a control

signal

that

either opens

closes

the

input

valve

rectify

the

situation.

1.2

EQUIPMENT

OVERVIEW

Refer

figure

1-3

for a simplified diagram

the

data module. The module contains 16

flip-flops

that

are used

hold

the

data

supplied

the CPU and destined for some attached

device. In

the

send mode,

the

CPU supplies

output

data, a write clock signal, an address

that

specifies one

the

16 flip-flops, and a module enable signal. All

these controls act

set

clear the selected flip-flop

establish an interface with

the

attached

device. In

the

receive mode,

the CPU provides a select address and a module enable signal

read one

input

lines.

The

990

Computer

instruction repertoire includes single (SBO, SBZ, and TB) and multiple

(STCR and LDCR) bit instructions

that

exercise

the

data module in

both

the

send and receive

modes. The SBO and SBZ instructions set and clear, respectively,

the

addressed flip-flop;

the

instruction tests

the

addressed

input

line. The LDCR instruction uses address increment logic

load from 1

the

flip-flops with serial data from

the

CPU. The STCR instruction uses

the

address increment logic

store

data

from 1

the

input

lines in contiguous

memory

locations.

When the module

wired

report interrupts, 2

the

16 flip-flops are used

store

the

interrupt itself and an

interrupt

mask. When

the

attached

device generates an interrupt, it

recorded in

the

interrupt

flip-flop and

the

interrupt

mask, controlled by

the

CPU,

either

enables

disables

the

transfer

the

interrupt

the

CPU.

1.2.1 TRANSMIT MODE. In

the

transmit mode,

the

CPU supplies an address (CRUBITl2-15)

that

specifies 1

the

16 flip-flops,

the

module enable signal

(IMODSELA-

), a write clock signal

(STORECLK-),

and

the

data bit

(CRUBITOUT-).

When

IMODSELA-

and

STORECLK-

are

both

TRUE (logic 0),

the

address decoder uses

the

address

select one

the

16 flip-flops and

the data bit

gated

into

it, through an open-collector driver, and

out

the

selected line. See

figure

1-3

for

the

output

logic.

1.2.2 RECEIVE MODE. In

the

receive mode,

the

CPU supplies

the

line address (CRUBITI2-15)

and

the

module enable signal

(IMODSELA-

The line address

decoded

the

multiplexer

and, when

IMODSELA-

true (logic 0),

the

input

bit

gated

through

an emitter-follower

transistor on

the

selected line, inverted three times and

submitted

the

CPU

CRUBITIN--.

See figure

1-3

for

the

input

logic.

1.2.3 INTERRUPT RESPONSE.

Interrupt

handling

selected

wiring

the

jumper

options

shown in Section II. Both types

interrupts (low-to-high and high-to-low) provide 15 normal

input

lines, 14 normal

output

lines, an

interrupt

line, and an

interrupt

mask. When an

interrupt

occurs, it

input

line

INl

5-.

The signal

inverted

either

once

twice (depending

upon

the

type

interrupt

the

module is wired for), submitted

a differentiating network,

and

clears

the

interrupt flip-flop.

interrupts are enabled

the

CPU (determined

the

interrupt

mask),

the

interrupt

inverted three times and

submitted

the

CPU as a low signal. See figure

1-3

for

the

interrupt

logic.

1-3 Digital Systems Division

(CPUDATAOUT)

990

DATA

OUT

990

WRITE

CLOCK

(STORECLOCK)

MODULE

ADDRESS

BITS

(CRUBIT1

2-15)

DECODE

ENABLE

(CRUSELO)

L(CRUDATAIN)

990

DATA

'Ii\

ENABLE

DECODE

SELECT

FLIP-FLOPS

(OUTo_-)

..-~------------------(-IN_O_~_),._·--<

(A)

INPUT/16

(IN

15-)

OUTPUT

CONFIGURATION

INTERRUPT

MASK

INTERRUPT

·---0...

)

(CRUDATA_o_u_T_)

_________________

--11.,.D

)

990

INTEH-

M.A.SK

DATA

INTERRUPT

990

(A)

29474A

FF14 FF15

15DC

~--~---------------~---~-~---~CLK

Q Q

CLR

(CRU

INT-)

(IN

15-)

(B)

INTERRUPT

CONFIGURATION

Figure 1-3. Simplified 16 Input/16 Output Data Module Diagram

DATA

LINES

PERIPHERAL

DEVICE(S)

LINES

PERIPHERAL

DEVICE

DATA

JUMPER

OPTION

PERIPHERAL

INTERRUPT

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