ST STM32F103 series Installation and operating instructions

May 2008 Rev 1 1/26

AN2739

Application note

How to use the high-density STM32F103xx microcontroller

to play audio files with an external I²S audio codec

Introduction

This application note describes how to use the high-density STM32F103xx I2S feature to

play audio files using an external codec.

The I2S protocol is widely used to transfer audio data from a microcontroller/DSP to an

audio codec in order to play melodies (stored in a memory) or, to capture analog sound

(from a microphone).

The high-density STM32F103xx allows I2S audio communications using the SPI peripheral,

and implements specific functionalities for this communications mode.

The first, preliminary section of this application note may be skipped by advanced users.

Note: Throughout this document, and unless otherwise specified, the term of I2S will be used to

refer to the I2S feature of the SPI peripheral that is implemented in high-density

STM32F103xx microcontrollers.

www.st.com

Contents AN2739

2/26

Contents

2S general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1 I2S protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.2 STM32F103xx I2S feature presentation . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Implementation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 General overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 Hardware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2.1 Audio codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2.2 STM32F103xx and board configuration . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3 Firmware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3.1 I2S_CODEC driver firmware description . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3.2 Demo firmware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.3.3 Timing considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.4 General, allowed parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

AN2739 List of tables

3/26

List of tables

Table 1. Driver library description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 2. I2S_CODEC driver high-level functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 3. I2S_CODEC_Init function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 4. Configuration parameters list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 5. I2S_CODEC_ReplayConfig function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 6. I2S_CODEC_Play function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 7. I2S_CODEC_ControlVolume function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 8. I2S_CODEC medium-level driver functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 9. I2S_CODEC low-level driver functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 10. Joystick_Config function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 11. Description of the Joystick functionalities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 12. LCD_Update function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 13. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

List of figures AN2739

4/26

List of figures

Figure 1. I2S Phillips protocol waveforms 16/32-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. I2S protocol signal description and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. Typical implementation design description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4. Audio codec hardware implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 5. Driver’s functional flowchart 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 6. Driver’s functional flowchart 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 7. Demo’s functional flowchart 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 8. Demo’s functional flowchart 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

AN2739 I2S general description

5/26

1 I2S general description

1.1 I2S protocol

I2S (IC-to-IC sound) is an audio data transfer standard using a three-line bus for serial and

synchronous data transmission.

Data are transmitted on the SD line (Serial Data) in Little Endian format (MSB first). Data

length is not limited (usually 16/20/24/32/64 bits). Data are synchronized by the rising or

falling edge of SCK (Serial Clock) for the transmitter, and by the falling edge of SCK for the

receiver. Refer to Figure 1.

Data represent stereo digital sound, so each sample contains two words, the right-channel

sample and the left-channel sample. Instead of using two data channels, multiplexing is

performed by transmitting each word over half a sampling period, which doubles the

sampling rate, and makes it possible to transmit two words per period.

A control signal WS (Word Select) is then used to determine if the word being sent is the

right or left one. This signal also determines the beginning and the end of the data: there is

no need to fix the data length. Receiver and transmitter data lengths can therefore be

different, as well as the right and left data lengths.

WS is synchronized to either the rising or the falling edge of SCK and precedes the MSB by

one SCK period in order to have enough time to store and shift operations.

As in most communication protocols, there must be a master and a slave. The master

provides and controls the SCK clock and the WS signal, while the slave only sends or

receives data. The master can be the receiver, the transmitter or a third element (Controller).

Refer to Figure 2.

Figure 1. I2S Phillips protocol waveforms 16/32-bit

Transmission Reception

MSB MSBLSB

16-bit or 32-bit

Left channel Right channel

ai15112

I2S general description AN2739

6/26

Figure 2. I2S protocol signal description and configuration

1.2 STM32F103xx I2S feature presentation

The STM32F103xx implements the I2S feature as a mode included in the SPI peripheral.

The user has to choose either the SPI mode or the I2S mode (software configuration).

The STM32F103xx I2S is available in simplex mode only (receive-only or transmit-only), the

communication direction is configured by software.

The I2S peripheral supports four audio protocols (configurable by software):

●I2S Phillips protocol

●MSB protocol

●LSB protocol

●PCM protocol (including PCM Short and PCM Long)

It also supports most audio frequencies (8 kHz, 16 kHz, 22.05 kHz, 44.1 kHz, 48 kHz, etc.)

The data format is programmable to 16-, 24- or 32-bit data length (for each channel), MSB

first, and to 16- or 32-bit packet length (for each channel).

The WS signal assignment is managed by hardware and a relative flag (CHSIDE) is

available to monitor the channel side (for Phillips, MSB and LSB standards).

The I2S peripheral can be configured as the master or the slave in the audio communication.

The I2S generates its own clock (independent of the SPI clock used to interface registers to

the APB bus) using a 9-bit prescaler and designed to reach accurate audio frequencies

(8 kHz, 16 kHz, 22.05 kHz, 44.1 kHz, 48 kHz, etc.)(a). When configured in master mode, the

peripheral is able to output an additional master clock (MCLK) at a fixed rate: 256 × FS

(where FSis the audio frequency).

ai15113

Transmitter Receiver

Transmitter = Master

Transmitter Receiver

Receiver = Master

Transmitter Receiver

Controller = Master

Controller

a. The sampling frequency is the bit clock frequency (CK) and is equal to:

FS× number of bits per channel × number of channels, where FSis the WS frequency in the Phillips, MSB and

LSB standards and, the WS/2 frequency in PCM mode.

AN2739 I2S general description

7/26

To decide if MCLK should be generated or not, the following facts have to be taken into

consideration:

●The external I2S device requirements (codec/DAC).

In general these devices need a master clock (usually at the rate 256 × FS) to perform

internal and sampling operations.

●The audio frequency accuracy is, in some cases, compromised by enabling the MCLK

output (that is when a low-frequency clock is driving the STM32F103xx system

(SYSCLK less than 36 MHz)).

The audio communication can be controlled in one of the following ways:

– by polling on the TXE/RXNE flag (bits 1/0 in SPI_CR2 register): wait until

TXE/RXNE flag is set then write/read the channel wave data to/from the SPI_DR

– Interrupt on TXE/RXNE: configure and enable the transmit/receive interrupt. And

in the interrupt subroutine, write/read the channel wave data to/from the SPI_DR

– DMA transfer: configure the DMA to load/unload the data from/to the SPI_DR

Note: In I2S mode, the DMA is used in exactly the same way as the SPI mode (with respect to the

supported audio transmission protocols, the CRC feature is not available in I2S mode).

The choice of the SYSCLK frequency directly impacts the I2S transmission quality (in

master mode): the sampling clock (CK) and WS clock are derived directly from SYSCLK

divided by a 9-bit prescaler in order to obtain the most accurate FSfrequency. For maximum

accuracy, the prescaler allows odd division by two (using the ODD bit in the SPI_I2SPR

But when the SYSCLK frequency is too low (it is typically greater than 36 MHz), the division

results in a low accuracy factor leading to audio quality degradation.

Implementation example AN2739

8/26

2 Implementation example

2.1 General overview

The example presented in this application note aims at providing typical hardware and

software implementation basics for an audio application like portable audio players, sound

synthesis systems, speech recorders, cell phones or interactive control boards.

Typically, the system embeds:

– a microcontroller (STM32F103xx device)

– an audio codec

– a speaker

– a memory support (where the audio file is stored).

Figure 3. Typical implementation design description

1. The audio input functionality (microphone) is not discussed in this application note.

The audio file format supported by the application is PCM, 16-bit data length, stereo/mono

channels, 8 to 48 kHz audio frequency.

2.2 Hardware description

General requirements

The developed example is mainly based on the STM3210E-EVAL evaluation board but the

functional and structural description is similar for most applications and platforms.

The memory in which the audio file is stored is the NOR Flash memory implemented on the

board. A different memory/source may be configured as the audio file support (like the SPI

Flash memory).

ai15114

LCD FSMC Codec

Memory controller

I2C

I2S

Display

controls

Control flow

Data flow

STM32F103xx (1)

Data flow

& memory control

Memory

Audio file:

PCM

16 bits

Stereo

8.48 kHz

AN2739 Implementation example

9/26

Other board resources are used to interface the application:

●Audio codec: AK4343 implemented on the STM3210E-EVAL and connected to the

I2S2 interface (and to relative passive components).

●Stereo audio speaker and audio jack connected to the audio codec and implemented

on the STM3210E-EVAL.

●Joystick and key push-buttons: connected to the PG7, PD3, PG13, PG14, PG15 and

PG8 pins on the board. These push-buttons are used to control the audio stream.

●LCD screen: implemented on the STM3210E-EVAL evaluation board and controlled by

the FSMC interface.

2.2.1 Audio codec

The audio codec implemented on the STM3210E-EVAL is the AK4343 from AKM. This

codec allows digital (PCM raw data transmitted with I2S protocol) to analog conversion. The

audio parameterization and the codec configuration are performed through an I2C interface.

The codec has 36 configuration registers mainly used to:

●program the audio output (speaker or headphone) and input (analog input or digital I2S

data, etc.).

●enable or disable the master clock feature and, set the reference clock for internal and

sampling operations.

●set the digital volume level, the mute status and the digital filter coefficients.

The codec can operate in different modes. The modes allowed by the hardware board

implementation are listed below:

●PLL Slave mode: the internal codec clock is derived, with an internal PLL, from an

external clock. The external clock can be either the bit clock (SCK) or the channel clock

(WS) (this mode requires a high clock accuracy on SCK/WS clock).

●EXT slave mode: no PLL is used and the internal clock is derived from the MCLK input

clock (at 256 × FSfrequency rate).

Figure 4 illustrates the hardware implementation schematic and how the codec is connected

to the STM32F103xx and the board components.

Figure 4. Audio codec hardware implementation

I2S_WS

I2S_SD

I2S_SCK

JP1 8

MCKO

TP7

+3V3

1uF

C59

I2C_SCK

I2C_SDA

10uF

C65

100n F

C54

2. 2uF

C53

100n F

C34

+3V3

10uF

C73

100n F

C66

10uF

C79

100n F

C16

+3V3

R83

0. 22u F

C67

R73

0. 22u F

C76

R86

6. 8

R87

6. 8

R84

47uF

C80

47uF

C70

Jack Ou tput

CN15

KSS-1508

SPEAKER

CCLK/SCL

CDTI/SDA

SDTI

TEST2 12

LRCK

BICK

DVDD

DVSS

MUTET

ROUT /RCN 26

LO UT/ R CP 27

MIN/L I N3 28

RIN2/IN2- 29

LIN 2/I N 2+ 30

LIN 1/I N 1- 31

RIN1/IN1+ 32

TEST1 1

VCOM 2

AV SS 3

AV DD 4

VCOC/ RIN3 5

I2C

PDN

CSN/CAD0

MCKI

17 MCKO

SPN 19

SPP 20

HVDD

HVSS

HPR 23

HPL 24

AK 434 3

U10

Au di o_RI N

Au di o_L IN

1uF

C56

1uF

C57

0R67

0R68

RIN

TP9

LIN

TP6

HPL

TP1 0

HPR

TP8

SPP

TP1 2

SPN

TP1 3

I2S_MCK

Defaul t s ett ing: 1<->2

PC6

PB12

PB13

PB15

PB7

PB6

PA5

PA4

PG11 (PDN)

DA C Out pu t

I2S Interface

I2C Interface

ai15128

Implementation example AN2739

10/26

When the MCLK clock is enabled (by configuring the relative configuration register), MCKI

jumper (JP18) should be configured in the 2<>3 position in order to drive the MCLK signal

from the STM32F103xx I2S interface to the codec MCLKI pin.

The default codec configuration used in this application note is:

●I2S standard: I2S Phillips (can be changed to MSB or LSB standards)

●MCLK clock enabled at 256 × FSfrequency rate and PLL disabled. (Disabling the

MCLK clock might lead to a reduced audio quality due to the high accuracy needed on

the alternative clocks: WS or CK)

●The default output is the headphone but the configuration can be changed before or

during the application execution (using the up/down joystick push-buttons).

Codec configuration steps

●Power up the codec (supply voltage) and activate it (pull the PDN pin high). This

operation causes all the codec registers to reset.

●Select the audio protocol (Phillips, MSB or LSB) by writing to Mode Control 1 register at

address 0x04.

●Select the MCLK rate (256 × FS) if the MCLK mode is configured, by writing to the

Mode Control 2 register at address 0x05.

●Power up the internal modules of the codec by writing to the Power Management 1

●To set the PLL mode, write to the Power Management 2 register at address 0x01.

●Supply the main clock to the codec (either the MCLK or the SCK/WS clocks) by

sending dummy data (this clock must be supplied through all subsequent operations).

●Choose the audio output device:

– select headphone by writing to the Mode Control 4 register at address 0x0F

– select speaker by writing to the Signal Select register at address 0x02

●Configure the digital volume by writing to the Lch Digital Volume Control and Rch

Digital Volume Control registers at addresses 0x0A and 0x0D, respectively.

●Power up:

– the speaker by writing to the Power Management 1 register at address 0x00

– the headphone by writing to the Power Management 2 register at address 0x01

●Exit the Mute mode by writing to the Power Management 1 register at address 0x00.

●Send the audio data through the I2S interface and stop I2C communications.

In the I2S_CODEC driver file, a single function performs the codec configuration:

CODEC_Config(u16 OutputDevice, u16 I2S_Standard, u16 I2S_MCLKOutput, u8 Volume)

2.2.2 STM32F103xx and board configuration

The STM32F103xx peripherals used for this application are: I2S2 for audio communication,

I2C1 for codec configuration and the memory interface (could be FSMC for NOR Flash

memory or SPI1 for SPI_Flash memory, etc.).

●Since the MCLK feature is enabled, configure MCKI Jumper (JP18) in the 2<>3

position to connect the I2S2 MCLK signal to the MCLKI codec pin.

●If the audio file to be played has a big size, it should be previously loaded into the

memory source (NOR Flash memory or SPI Flash) using an independent application

(IAP, DFU, etc.). It may also be included as a table file.

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