ST STM32F10 Series Installation and operating instructions

July 2007 Rev 1 1/23

AN2586

Application note

STM32F10xxx hardware development:

getting started

Introduction

This application note is intended for system designers who require a hardware

implementation overview of the development board features such as the power supply, the

clock management, the reset control, the boot mode settings and the debug management. It

shows how to use the STM32F10xxx product family and describes the minimum hardware

resources required to develop an STM32F10xxx application.

Detailed reference design schematics are also contained in this document with descriptions

of the main components, interfaces and modes.

www.st.com

Contents AN2586 - Application note

2/23

Contents

1 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1.1 Independent A/D converter supply and reference voltage . . . . . . . . . . . . 6

1.1.2 Battery backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.2 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.3 Reset & power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.3.1 Power on reset (POR) / power down reset (PDR) . . . . . . . . . . . . . . . . . . 8

1.3.2 Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.3.3 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.1 HSE OSC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.1.1 External source (HSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.1.2 External crystal/ceramic resonator (HSE crystal) . . . . . . . . . . . . . . . . . 12

2.2 LSE OSC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.2.1 External source (LSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.2.2 External crystal/ceramic resonator (LSE crystal) . . . . . . . . . . . . . . . . . . 13

2.3 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.4 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1 Boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.2 Boot pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.3 Embedded Boot Loader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4 Debug management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.2 SWJ debug port (serial wire and JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.3 Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.3.1 SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.3.2 Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.3.3 Internal pull-up and pull-down on JTAG pins . . . . . . . . . . . . . . . . . . . . . 18

AN2586 - Application note Contents

3/23

4.3.4 SWJ debug port connection with Standard JTAG connector . . . . . . . . . 19

5 Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.1 Main . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.1.1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.1.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.1.3 Boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.2 SWJ interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.3 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

List of tables AN2586 - Application note

4/23

List of tables

Table 1. Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 2. Debug port pin assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 3. SWJ I/O pin availability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 4. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

AN2586 - Application note List of figures

5/23

List of figures

Figure 1. Power supply overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3. Power on reset/power down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4. PVD thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 5. Reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 6. Clock overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 7. External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 8. Crystal/ceramic resonators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 9. External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 10. Crystal/ceramic resonators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 11. Boot mode selection implementation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 12. Host-to-board connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 13. JTAG connector implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 14. STM32F10xxx microcontroller reference schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Power supplies AN2586 - Application note

6/23

1 Power supplies

1.1 Introduction

The device requires a 2.0 V to 3.6 V operating voltage supply (VDD). An embedded regulator

is used to supply the internal 1.8 V digital power.

The real-time clock (RTC) andbackup registers can be powered from the VBAT voltage when

the main VDD supply is powered off.

Figure 1. Power supply overview

1.1.1 Independent A/D converter supply and reference voltage

To improve conversion accuracy, the ADC has an independent power supply that can be

filtered separately, and shielded from noise on the PCB.

●the ADC voltage supply input is available on a separate VDDA pin

●an isolated supply ground connection is provided on the VSSA pin

When available (depending on package), VREF– must be tied to VSSA.

On 100-pin packages

To ensure a better accuracy on low-voltage inputs, the user can connect a separate external

reference voltage ADC input on VREF+. The voltage on VREF+ may range from 2.0 V to

VDDA.

A/D converter

VDDA

VDD

VSSA

VREF+

VBAT

VSS I/O Ring

BKP registers

Temp. sensor

Reset block

Standby circuitry

PLL

(Wakeup logic,

IWDG)

RTC

Voltage regulator

Core

memories'

digital

peripherals

Low voltage detector

VREF- VDDA domain

VDD domain 1.8 V domain

Backup domain

LSE crystal 32K osc

RCC BDCR register

ai14602b

AN2586 - Application note Power supplies

7/23

On packages with 64 pins or less

The VREF+ and VREF- pins are not available, they are internally connected to the ADC

voltage supply (VDDA) and ground (VSSA).

1.1.2 Battery backup

To retain the content of the Backup registers when VDD is turned off, the VBAT pin can be

connected to an optional standby voltage supplied by a battery or another source.

The VBAT pin also powers the RTC unit, allowing the RTC to operate even when the main

digital supply (VDD) is turned off. The switch to the VBAT supply is controlled by the power

down reset (PDR) circuitry embedded in the Reset block.

If no external battery is used in the application, VBAT must be connected externally to VDD.

1.1.3 Voltage regulator

The voltage regulator is always enabled after reset. It works in three different modes

depending on the application modes.

●in Run mode,the regulator supplies full power to the 1.8 V domain (core, memories and

digital peripherals)

●in Stop mode, the regulator supplies low power to the 1.8 V domain, preserving the

contents of the registers and SRAM

●in Standby mode, the regulator is powered off. The contents of the registers and SRAM

are lost except for those concerned with the Standby circuitry and the Backup domain.

1.2 Power supply schemes

The circuit is powered by a stabilized power supply, VDD.

●Caution:

– If the ADC is used, the VDD range is limited to 2.4 V to 3.6 V

– If the ADC is not used, the VDD range is 2 V to 3.6 V

●The VDD pins must be connected to VDD with external stabilization capacitors (five

100 nF ceramic capacitor + one Tantalum capacitor (min. 4.7 µF typ.10 µF).

●The VBAT pin must be connected to the external battery (1.8 V < VBAT < 3.6 V). if no

external battery is used, this pin must be connected to VDD with a 100 nF external

ceramic stabilization capacitor.

●The VDDA pin must be connected to two external stabilization capacitors (10 nF

ceramic + 1 µF Tantalum).

●The VREF+ pin can be connected to the VDDA external power supply. If a separate,

external reference voltage is applied on VREF+, two 10 nF and 1 µF capacitors must be

connected on this pin. In all cases, VREF+ must be kept between 2.0 V and VDDA.

Power supplies AN2586 - Application note

8/23

Figure 2. Power supply scheme

1. Optional. If a separate, external reference voltage is connected on VREF+, the two capacitors (10 nF and

1 µF) must be connected.

2. VREF+ is either connected to VDDA or to VREF.

1.3 Reset & power supply supervisor

1.3.1 Power on reset (POR) / power down reset (PDR)

The device has an integrated POR/PDR circuitry that allows proper operation starting from

2V.

The device remains in the Reset mode as long as VDD is below a specified threshold,

VPOR/PDR, without the need for an external reset circuit. For more details concerning the

power on/power down reset threshold, refer to the electrical characteristics in the

STM32F101xx and STM32F103xx datasheets.

Figure 3. Power on reset/power down reset waveform

VBAT

STM32F10xxx

5 × 100 nF

VDD

+ 1 × 10 µF

10 nF + 1 µF

(note 1)

Battery

VBAT VREF+

VDDA

VSSA

VREF–

VDD 1/2/3/4/5

VSS 1/2/3/4/5

VREF

VDD

ai14363

VDD

POR

PDR

40 mV

hysteresis

Temporization

tRSTTEMPO

RESET

ai14364

AN2586 - Application note Power supplies

9/23

1.3.2 Programmable voltage detector (PVD)

You can use the PVD to monitor the VDD power supply by comparing it to a threshold

selected by the PLS[2:0] bits in the Power control register (PWR_CR).

The PVD is enabled by setting the PVDE bit.

A PVDO flag is available, in the Power control/status register (PWR_CSR), to indicate

whether VDD is higher or lower than the PVD threshold. This event is internally connected to

EXTI Line16 and can generate an interrupt if enabled through the EXTI registers. The PVD

output interrupt can be generated when VDD drops below the PVD threshold and/or when

VDD rises above the PVD threshold depending on the EXTI Line16 rising/falling edge

configuration. As an example the service routine can perform emergency shutdown tasks.

Figure 4. PVD thresholds

1.3.3 System reset

A system reset sets all registers to their reset values except for the reset flags in the clock

controller CSR register and the registers in the Backup domain (see Figure 1).

A system reset is generated when one of the following events occurs:

1. A low level on the NRST pin (external reset)

2. window watchdog end-of-count condition (WWDG reset)

3. Independent watchdog end-of-count condition (IWDG reset)

4. A software reset (SW reset)

5. Low-power management reset

The reset source can be identified by checking the reset flags in the Control/Status register,

RCC_CSR.

100 mV

hysteresis

PVD threshold

PVD output

ai14365

Power supplies AN2586 - Application note

10/23

Figure 5. Reset circuit

RON

VDD

Filter

0.1 µF

External

reset circuit NRST System nreset

WWDG reset

IWDG reset

POR/PDR reset

Software reset

Low-power management reset

Pulse

generator

(min 20 µs)

ai14366

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