Silicon Laboratories EFM32G User manual

...the world's most energy friendly microcontrollers

2014-07-02 - Gecko Family - d0001_Rev1.30 1 www.silabs.com

EFM32G Reference Manual

Gecko Series

• 32-bit ARM Cortex-M3 processor running at up to 32 MHz

• Up to 128 kB Flash and 16 kB RAM memory

• Energy efficient and autonomous peripherals

• Ultra low power Energy Modes with sub-µA operation

• Fast wake-up time of only 2 µs

The EFM32G microcontroller series revolutionizes the 8- to 32-bit market with a

combination of unmatched performance and ultra low power consumption in both

active- and sleep modes. EFM32G devices consume as little as 180 µA/MHz in run

mode, and as little as 900 nA with a Real Time Counter running, Brown-out and full

RAM and register retention.

EFM32G's low energy consumption outperforms any other available 8-, 16-, and 32-

bit solution. The EFM32G includes autonomous and energy efficient peripherals,

high overall chip- and analog integration, and the performance of the industry

standard 32-bit ARM Cortex-M3 processor.

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1 Energy Friendly Microcontrollers

1.1 Typical Applications

The EFM32G Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

These devices are developed to minimize the energy consumption by lowering both the power and the

active time, over all phases of MCU operation. This unique combination of ultra low energy consumption

and the performance of the 32-bit ARM Cortex-M3 processor, help designers get more out of the

available energy in a variety of applications.

Ultra low energy EFM32G microcontrollers are perfect for:

• Gas metering

• Energy metering

• Water metering

• Smart metering

• Alarm and security systems

• Health and fitness applications

• Industrial and home automation

01 2 3 4

1.2 EFM32G Development

Because EFM32G use the Cortex-M3 CPU, embedded designers benefit from the largest development

ecosystem in the industry, the ARM ecosystem. The development suite spans the whole design

process and includes powerful debug tools, and some of the world’s top brand compilers. Libraries with

documentation and user examples shorten time from idea to market.

The range of EFM32G devices ensure easy migration and feature upgrade possibilities.

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2 About This Document

This document contains reference material for the EFM32G series of microcontrollers. All modules and

peripherals in the EFM32G series devices are described in general terms. Not all modules are present

in all devices, and the feature set for each device might vary. Such differences, including pin-out, are

covered in the device-specific datasheets.

2.1 Conventions

TIMERn_CTRL - Control Register

The "n" denotes the numeric instance for modules that might have more than one instance.

Some registers are grouped which leads to a group name following the module prefix:

GPIO_Px_DOUT - Port Data Out Register,

where xdenotes the port instance (A,B,...).

Bit Fields

Registers contain one or more bit fields which can be 1 to 32 bits wide. Multi-bit fields are denoted with

(x:y), where xis the start bit and yis the end bit.

Address

The address for each register can be found by adding the base address of the module (found in the

Memory Map), and the offset address for the register (found in module Register Map).

Access Type

The register access types used in the register descriptions are explained in Table 2.1 (p. 3) .

Table 2.1. Register Access Types

Access Type Description

R Read only. Writes are ignored.

RW Readable and writable.

RW1 Readable and writable. Only writes to 1 have effect.

RW1H Readable, writable and updated by hardware. Only writes to

1 have effect.

W1 Read value undefined. Only writes to 1 have effect.

W Write only. Read value undefined.

RWH Readable, writable and updated by hardware.

Number format

0x prefix is used for hexadecimal numbers.

0b prefix is used for binary numbers.

Numbers without prefix are in decimal representation.

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Reserved

Registers and bit fields marked with reserved are reserved for future use. These should be written to 0

unless otherwise stated in the Register Description. Reserved bits might be read as 1 in future devices.

Reset Value

The reset value denotes the value after reset.

Registers denoted with X have an unknown reset value and need to be initialized before use. Note

that, before these registers are initialized, read-modify-write operations might result in undefined register

values.

Pin Connections

Pin connections are given as a module prefix followed by a short pin name:

USn_TX (USARTn TX pin)

The pin locations referenced in this document are given in the device-specific datasheet.

2.2 Related Documentation

Further documentation on the EFM32G family and the ARM Cortex-M3 can be found at the Silicon

Laboratories and ARM web pages:

www.silabs.com

www.arm.com

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3 System Overview

3.1 Introduction

The EFM32 MCUs are the world’s most energy friendly microcontrollers. With a unique combination

of the powerful 32-bit ARM Cortex-M3, innovative low energy techniques, short wake-up time from

energy saving modes, and a wide selection of peripherals, the EFM32G microcontroller is well suited for

any battery operated application, as well as other systems requiring high performance and low-energy

consumption, see Figure 3.1 (p. 7) .

3.2 Features

•ARM Cortex-M3 CPU platform

• High Performance 32-bit processor @ up to 32 MHz

• Memory Protection Unit

• Wake-up Interrupt Controller

•Flexible Energy Management System

• 20 nA @ 3 V Shutoff Mode

• 0.6 µA @ 3 V Stop Mode, including Power-on Reset, Brown-out Detector, RAM and CPU

retention

• 0.9 µA @ 3 V Deep Sleep Mode, including RTC with 32.768 kHz oscillator, Power-on

Reset, Brown-out Detector, RAM and CPU retention

• 45 µA/MHz @ 3 V Sleep Mode

• 180 µA/MHz @ 3 V Run Mode, with code executed from flash

•128/64/32/16 KB Flash

•16/8 KB RAM

•Up to 90 General Purpose I/O pins

• Configurable push-pull, open-drain, pull-up/down, input filter, drive strength

• Configurable peripheral I/O locations

• 16 asynchronous external interrupts

•8 Channel DMA Controller

• Alternate/primary descriptors with scatter-gather/ping-pong operation

•8 Channel Peripheral Reflex System

• Autonomous inter-peripheral signaling enables smart operation in low energy modes

•External Bus Interface (EBI)

• Up to 4x64 MB of external memory mapped space

•Integrated LCD Controller for up to 4×40 Segments

• Voltage boost, adjustable contrast adjustment and autonomous animation feature

•Hardware AES with 128/256-bit Keys in 54/75 cycles

•Communication interfaces

• 3× Universal Synchronous/Asynchronous Receiver/Transmitter

• UART/SPI/SmartCard (ISO 7816)/IrDA

• Triple buffered full/half-duplex operation

• 4-16 data bits

• 1× Universal Asynchronous Receiver/Transmitter

• Triple buffered full/half-duplex operation

• 8-9 data bits

• 2× Low Energy UART

• Autonomous operation with DMA in Deep Sleep Mode

• 1× I2C Interface with SMBus support

• Address recognition in Stop Mode

•Timers/Counters

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• 3× 16-bit Timer/Counter

• 3 Compare/Capture/PWM channels

• Dead-Time Insertion on TIMER0

• 16-bit Low Energy Timer

• 24-bit Real-Time Counter

• 3× 8-bit Pulse Counter

• Asynchronous pulse counting/quadrature decoding

• Watchdog Timer with dedicated RC oscillator @ 50 nA

•Ultra low power precision analog peripherals

• 12-bit 1 Msamples/s Analog to Digital Converter

• 8 input channels and on-chip temperature sensor

• Single ended or differential operation

• Conversion tailgating for predictable latency

• 12-bit 500 ksamples/s Digital to Analog Converter

• 2 single ended channels/1 differential channel

• 2× Analog Comparator

• Programmable speed/current

• Capacitive sensing with up to 8 inputs

• Supply Voltage Comparator

•Ultra efficient Power-on Reset and Brown-Out Detector

•2-pin Serial Wire Debug interface

• 1-pin Serial Wire Viewer

•Temperature range -40 - 85°C

•Single power supply 1.98 - 3.8 V

•Packages

• QFN32

• QFN64

• TQFP48

• TQFP64

• LQFP100

• LFBGA112

3.3 Block Diagram

Figure 3.1 (p. 7) shows the block diagram of EFM32G. The color indicates peripheral availability in

the different energy modes, described in Section 3.4 (p. 7) .

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Figure 3.1. Block Diagram of EFM32G

Clock Management Energy Management

Serial Interfaces

I/O Ports

Core andMemory

Timers andTriggers Analog Interfaces Security

ARM Cortex™- M3 processor

Flash

Program

Memory

Peripheral

Reflex

System

High Frequency

Oscillator

High Frequency

Crystal

Oscillator

Timer/

Counter

Low Energy

Timer™

Pulse

Counter

Real Time

Counter

Low Frequency

Crystal

Oscillator

Low Frequency

Oscillator

LCD

Controller

Voltage

Regulator

Watchdog

Timer

RAM

Memory

Voltage

Comparator

Power-on

Reset Brown-out

Detector

Analog

Comparator

External

Bus

Interface

General

Purpose

I/ O

Low

Energy

UART™

Watchdog

Oscillator

Memory

Protection

Unit

ADC DAC

DMA

Controller

Debug

Interface

External

Interrupts Pin

Reset

USART

UART AES

Gecko

32-bit bus

Peripheral Reflex System

Figure 3.2. Energy Mode Indicator

01 2 3 4

Note In the energy mode indicator, the numbers indicates Energy Mode, i.e EM0-EM4.

3.4 Energy Modes

There are five different Energy Modes (EM0-EM4) in the EFM32G, see Table 3.1 (p. 8). The

EFM32G is designed to achieve a high degree of autonomous operation in low energy modes. The

intelligent combination of peripherals, RAM with data retention, DMA, low-power oscillators, and short

wake-up time, makes it attractive to remain in low energy modes for long periods and thus saving energy

consumption.

Tip

Throughout this document, the first figure in every module description contains an Energy Mode

Indicator showing which energy mode(s) the module can operate (see Table 3.1 (p. 8) ).

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Table 3.1. Energy Mode Description

Energy Mode Name Description

01 2 3 4 EM0 – Energy Mode 0

(Run mode)

In EM0, the CPU is running and consuming as little as 180 µA/MHz, when

running code from flash. All peripherals can be active.

01 2 3 4 EM1 – Energy Mode 1

(Sleep Mode) In EM1, the CPU is sleeping and the power consumption is only 45 µA/MHz.

All peripherals, including DMA, PRS and memory system, are still available.

01 2 3 4 EM2 – Energy Mode 2

(Deep Sleep Mode)

In EM2 the high frequency oscillator is turned off, but with the 32.768 kHz

oscillator running, selected low energy peripherals (LCD, RTC, LETIMER,

PCNT, LEUART, I2C, WDOG and ACMP) are still available. This gives a high

degree of autonomous operation with a current consumption as low as 0.9 µA

with RTC enabled. Power-on Reset, Brown-out Detection and full RAM and

CPU retention is also included.

01 2 3 4 EM3 - Energy Mode 3

(Stop Mode)

In EM3, the low-frequency oscillator is disabled, but there is still full CPU

and RAM retention, as well as Power-on Reset, Pin reset and Brown-

out Detection, with a consumption of only 0.6 µA. The low-power ACMP,

asynchronous external interrupt, PCNT, and I2C can wake-up the device.

Even in this mode, the wake-up time is a few microseconds.

01 2 3 4 EM4 – Energy Mode 4

(Shutoff Mode)

In EM4, the current is down to 20 nA and all chip functionality is turned off

except the pin reset and the Power-On Reset. All pins are put into their reset

state.

3.5 Product Overview

Table 3.2(p. 8) shows a device overview of the EFM32G Microcontroller Series, including peripheral

functionality. For more information, the reader is referred to the device specific datasheets.

Table 3.2. EFM32G Microcontroller Series

EFM32G Part #

Flash

RAM

GPIO(pins)

LCD

USART+UART

LEUART

I2C

Timer(PWM)

LETIMER

RTC

PCNT

Watchdog

ADC(pins)

DAC(pins)

ACMP(pins)

AES

EBI

Package

200F16 16 8 24 - 2 1 1 2

(6) 111 11

(4) 1 (1) 2 (5) - - QFN32

200F32 32 8 24 - 2 1 1 2

(6) 111 11

(4) 1 (1) 2 (5) - - QFN32

200F64 64 16 24 - 2 1 1 2

(6) 111 11

(4) 1 (1) 2 (5) - - QFN32

210F128 128 16 24 - 2 1 1 2

(6) 111 11

(4) 1 (1) 2 (5) Y - QFN32

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EFM32G Part #

Flash

RAM

GPIO(pins)

LCD

USART+UART

LEUART

I2C

Timer(PWM)

LETIMER

RTC

PCNT

Watchdog

ADC(pins)

DAC(pins)

ACMP(pins)

AES

EBI

Package

230F32 32 8 56 - 3 2 1 3

(9) 113 11

(8) 2 (2) 2

(16) Y - QFN64

230F64 64 16 56 - 3 2 1 3

(9) 113 11

(8) 2 (2) 2

(16) Y - QFN64

230F128 128 16 56 - 3 2 1 3

(9) 113 11

(8) 2 (2) 2

(16) Y - QFN64

280F32 32 8 85 - 3+1 2 1 3

(9) 113 11

(8) 2 (2) 2

(16) Y Y LQFP100

280F64 64 16 85 - 3+1 2 1 3

(9) 113 11

(8) 2 (2) 2

(16) Y Y LQFP100

280F128 128 16 85 - 3+1 2 1 3

(9) 113 11

(8) 2 (2) 2

(16) Y Y LQFP100

290F32 32 8 90 - 3+1 2 1 3

(9) 113 11

(8) 2 (2) 2

(16) Y Y LFBGA112

290F64 64 16 90 - 3+1 2 1 3

(9) 113 11

(8) 2 (2) 2

(16) Y Y LFBGA112

290F128 128 16 90 - 3+1 2 1 3

(9) 113 11

(8) 2 (2) 2

(16) Y Y LFBGA112

840F32 32 8 56 4x24 3 2 1 3

(9) 113 11

(8) 2 (2) 2 (8) Y - QFN64

840F64 64 16 56 4x24 3 2 1 3

(9) 113 11

(8) 2 (2) 2 (8) Y - QFN64

840F128 128 16 56 4x24 3 2 1 3

(9) 113 11

(8) 2 (2) 2 (8) Y - QFN64

880F32 32 8 85 4x40 3+1 2 1 3

(9) 113 11

(8) 2 (2) 2

(16) Y Y 1LQFP100

880F64 64 16 85 4x40 3+1 2 1 3

(9) 113 11

(8) 2 (2) 2

(16) Y Y1LQFP100

880F128 128 16 85 4x40 3+1 2 1 3

(9) 113 11

(8) 2 (2) 2

(16) Y Y1LQFP100

890F32 32 8 90 4x40 3+1 2 1 3

(9) 113 11

(8) 2 (2) 2

(16) Y Y1LFBGA112

890F64 64 16 90 4x40 3+1 2 1 3

(9) 113 11

(8) 2 (2) 2

(16) Y Y1LFBGA112

890F128 128 16 90 4x40 3+1 2 1 3

(9) 113 11

(8) 2 (2) 2

(16) Y Y1LFBGA112

1EBI and LCD share pins in the part. Only a reduced pin count LCD driver can be used simultaneously with the EBI.

3.6 Device Revision

The device revision number is read from the ROM Table. The major revision number and the chip family

number is read from PID0 and PID1 registers. The minor revision number is extracted from the PID2 and

PID3 registers, as illustrated in Figure 3.3 (p. 10). The Fam[5:2] and Fam[1:0] must be combined

to complete the chip family number, while the Minor Rev[7:4] and Minor Rev[3:0] must be combined to

form the complete revision number.

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Figure 3.3. Revision Number Extraction

PID1 (0xE00FFFE4)

31:4 3:0

PID0 (0xE00FFFE0)

31:7 6:5 5:0

Major Rev[5:0]

PID3 (0xE00FFFEC)

31:8 7:4 3:0

Minor Rev[3:0]

Fam[1:0] Fam[5:2]

PID2 (0xE00FFFE8)

31:8 7:4 3:0

Minor Rev[7:4]

For the latest revision of the Gecko family, the chip family number is 0x00 and the major revision number

is 0x01. The minor revision number is to be interpreted according to Table 3.3 (p. 10) .

Table 3.3. Minor Revision Number Interpretation

Minor Rev[7:0] Revision

0x00 A

0x01 B

0x02 C

0x03 D

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