Silicon Laboratories EFM8SB2 User manual

EFM8 Sleepy Bee Family

EFM8SB2 Reference Manual

The EFM8SB2, part of the Sleepy Bee family of MCUs, is the

world’s most energy friendly 8-bit microcontrollers with a compre-

hensive feature set in small packages.

These devices offer lowest power consumption by combining innovative low energy tech-

niques and short wakeup times from energy saving modes into small packages, making

them well-suited for any battery operated applications. With an efficient 8051 core, 6-bit

current reference, and precision analog, the EFM8SB2 family is also optimal for embed-

ded applications.

EFM8SB2 applications include the following:

ENERGY FRIENDLY FEATURES

• Lowest MCU sleep current with supply

brownout detection (50 nA)

•Lowest MCU active current with these

features (170 μA / MHz at 24.5 MHz clock

rate)

• Lowest MCU sleep current using internal

RTC operating and supply brownout

detection (<300 nA)

• Ultra-fast wake up for digital and analog

peripherals (< 2 μs)

• Integrated low drop out (LDO) voltage

regulator to maintain ultra-low active

current at all voltages

• Hand-held devices

•Industrial controls

• Battery-operated consumer electronics

•Sensor interfaces

SecurityI/O Ports

Core / Memory Clock Management

CIP-51 8051 Core

(25 MHz)

Energy Management

Internal LDO

Regulator

Brown-Out Detector

Power-On Reset

8-bit SFR bus

Serial Interfaces Timers and Triggers Analog Interfaces

2 x SPI Pin Reset Timers

0/1/2/3 PCA/PWM

Watchdog

Timer

Comparator 0 16/32-bit CRC

Flash Program

Memory

(up to 64 KB)

RAM Memory

(4352 bytes)

Debug Interface

with C2

Lowest power mode with peripheral operational:

IdleNormal Suspend Sleep

High Frequency

24.5 MHz RC

Oscillator

Pin Wakeup

External

Interrupts

General

Purpose I/O

I2C / SMBus

UART

External 32 kHz

RTC Oscillator

Low Power 20

MHz RC

Oscillator

External

Oscillator

Real Time

Clock

Internal Voltage

Reference

Comparator 1

ADC

Internal Current Reference

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1. System Overview

1.1 Introduction

P0.n

P1.n

Digital Peripherals

UART

Timers 0,

1, 2, 3

PCA/WDT

SMBus

Priority

Crossbar

Decoder

Crossbar Control

Port I/O Configuration

CIP-51 8051 Controller

Core

64/32/16 KB ISP Flash

Program Memory

256 Byte SRAM

4096 Byte XRAM

SPI 0,1

Power Net

VDD

GND

XTAL1

SYSCLK

System Clock

Configuration

External

Oscillator

Circuit

Precision

24.5 MHz

Oscillator

Debug /

Programming

Hardware

Power On

Reset/PMU

Reset

C2D

C2CK/RSTb

Wake

XTAL2

Low Power

20 MHz

Oscillator

XTAL3

XTAL4

VREG Digital

Power

Analog

Power

Port 0

Drivers

Port 1

Drivers

Port 2

Drivers P2.n

RTC

Oscillator

CRC

External Memory Interface

Control

Address

Data

Analog Peripherals

SFR

Bus

Comparators

6-bit

IREF IREF0

AMUX

10-bit

300ksps

ADC

Temp

Sensor

External

VREF

Internal

VREF VDD

VREF

GND

Figure 1.1. Detailed EFM8SB2 Block Diagram

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System Overview

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1.2 Power

All internal circuitry draws power from the VDD supply pin. External I/O pins are powered from the VIO supply voltage (or VDD on devi-

ces without a separate VIO connection), while most of the internal circuitry is supplied by an on-chip LDO regulator. Control over the

device power can be achieved by enabling/disabling individual peripherals as needed. Each analog peripheral can be disabled when

not in use and placed in low power mode. Digital peripherals, such as timers and serial buses, have their clocks gated off and draw little

power when they are not in use.

Table 1.1. Power Modes

Power Mode Details Mode Entry Wake-Up Sources

Normal Core and all peripherals clocked and fully operational — —

Idle • Core halted

•All peripherals clocked and fully operational

• Code resumes execution on wake event

Set IDLE bit in PCON0 Any interrupt

Suspend • Core and digital peripherals halted

•Internal oscillators disabled

• Code resumes execution on wake event

1. Switch SYSCLK to

HFOSC0 or LPOSC0

2. Set SUSPEND bit in

PMU0CF

• RTC0 Alarm Event

• RTC0 Fail Event

• Port Match Event

• Comparator 0 Rising

Edge

Sleep • Most internal power nets shut down

•Select circuits remain powered

• Pins retain state

• All RAM and SFRs retain state

• Code resumes execution on wake event

1. Disable unused ana-

log peripherals

2. Set SLEEP bit in

PMU0CF

• RTC0 Alarm Event

• RTC0 Fail Event

• Port Match Event

• Comparator 0 Rising

Edge

1.3 I/O

Digital and analog resources are externally available on the device’s multi-purpose I/O pins. Port pins P0.0-P2.6 can be defined as gen-

eral-purpose I/O (GPIO), assigned to one of the internal digital resources through the crossbar or dedicated channels, or assigned to an

analog function. Port pin P2.7 can be used as GPIO. Additionally, the C2 Interface Data signal (C2D) is shared with P2.7.

• Up to 24 multi-functions I/O pins, supporting digital and analog functions.

• Flexible priority crossbar decoder for digital peripheral assignment.

• Two drive strength settings for each pin.

• Two direct-pin interrupt sources with dedicated interrupt vectors (INT0 and INT1).

• Up to 16 direct-pin interrupt sources with shared interrupt vector (Port Match).

1.4 Clocking

The CPU core and peripheral subsystem may be clocked by both internal and external oscillator resources. By default, the system

clock comes up running from the 20 MHz low power oscillator divided by 8.

• Provides clock to core and peripherals.

• 20 MHz low power oscillator (LPOSC0), accurate to +/- 10% over supply and temperature corners.

• 24.5 MHz internal oscillator (HFOSC0), accurate to +/- 2% over supply and temperature corners.

• External RTC 32 kHz crystal.

• External RC, C, CMOS, and high-frequency crystal clock options (EXTCLK).

• Clock divider with eight settings for flexible clock scaling: Divide the selected clock source by 1, 2, 4, 8, 16, 32, 64, or 128.

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System Overview

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1.5 Counters/Timers and PWM

Real Time Clock (RTC0)

The RTC is an ultra low power, 36 hour 32-bit independent time-keeping Real Time Clock with alarm. The RTC has a dedicated 32 kHz

oscillator. No external resistor or loading capacitors are required, and a missing clock detector features alerts the system if the external

crystal fails. The on-chip loading capacitors are programmable to 16 discrete levels allowing compatibility with a wide range of crystals.

The RTC module includes the following features:

• Up to 36 hours (32-bit) of independent time keeping.

• Support for external 32 kHz crystal or internal self-oscillate mode.

• Internal crystal loading capacitors with 16 levels.

• Operation in the lowest power mode and across the full supported voltage range.

• Alarm and oscillator failure events to wake from the lowest power mode or reset the device.

Programmable Counter Array (PCA0)

The programmable counter array (PCA) provides multiple channels of enhanced timer and PWM functionality while requiring less CPU

intervention than standard counter/timers. The PCA consists of a dedicated 16-bit counter/timer and one 16-bit capture/compare mod-

ule for each channel. The counter/timer is driven by a programmable timebase that has flexible external and internal clocking options.

Each capture/compare module may be configured to operate independently in one of five modes: Edge-Triggered Capture, Software

Timer, High-Speed Output, Frequency Output, or Pulse-Width Modulated (PWM) Output. Each capture/compare module has its own

associated I/O line (CEXn) which is routed through the crossbar to port I/O when enabled.

• 16-bit time base.

• Programmable clock divisor and clock source selection.

• Up to six independently-configurable channels

• 8, 9, 10, 11 and 16-bit PWM modes (edge-aligned operation).

• Frequency output mode.

• Capture on rising, falling or any edge.

• Compare function for arbitrary waveform generation.

• Software timer (internal compare) mode.

• Integrated watchdog timer.

Timers (Timer 0, Timer 1, Timer 2, and Timer 3)

Several counter/timers are included in the device: two are 16-bit counter/timers compatible with those found in the standard 8051, and

the rest are 16-bit auto-reload timers for timing peripherals or for general purpose use. These timers can be used to measure time inter-

vals, count external events and generate periodic interrupt requests. Timer 0 and Timer 1 are nearly identical and have four primary

modes of operation. The other timers offer both 16-bit and split 8-bit timer functionality with auto-reload and capture capabilities.

Timer 0 and Timer 1 include the following features:

• Standard 8051 timers, supporting backwards-compatibility with firmware and hardware.

• Clock sources include SYSCLK, SYSCLK divided by 12, 4, or 48, the External Clock divided by 8, or an external pin.

• 8-bit auto-reload counter/timer mode

• 13-bit counter/timer mode

• 16-bit counter/timer mode

• Dual 8-bit counter/timer mode (Timer 0)

Timer 2 and Timer 3 are 16-bit timers including the following features:

• Clock sources include SYSCLK, SYSCLK divided by 12, or the External Clock divided by 8.

• 16-bit auto-reload timer mode

• Dual 8-bit auto-reload timer mode

• Comparator 0 or RTC0 capture (Timer 2)

• Comparator 1 or EXTCLK/8 capture (Timer 3)

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Watchdog Timer (WDT0)

The device includes a programmable watchdog timer (WDT) integrated within the PCA0 peripheral. A WDT overflow forces the MCU

into the reset state. To prevent the reset, the WDT must be restarted by application software before overflow. If the system experiences

a software or hardware malfunction preventing the software from restarting the WDT, the WDT overflows and causes a reset. Following

a reset, the WDT is automatically enabled and running with the default maximum time interval. If needed, the WDT can be disabled by

system software. The state of the RSTb pin is unaffected by this reset.

The Watchdog Timer integrated in the PCA0 peripheral has the following features:

• Programmable timeout interval

• Runs from the selected PCA clock source

• Automatically enabled after any system reset

1.6 Communications and Other Digital Peripherals

Universal Asynchronous Receiver/Transmitter (UART0)

UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support

allows a wide range of clock sources to generate standard baud rates. Received data buffering allows UART0 to start reception of a

second incoming data byte before software has finished reading the previous data byte.

The UART module provides the following features:

• Asynchronous transmissions and receptions

• Baud rates up to SYSCLK/2 (transmit) or SYSCLK/8 (receive)

• 8- or 9-bit data

• Automatic start and stop generation

Serial Peripheral Interface (SPI0 and SPI1)

The serial peripheral interface (SPI) module provides access to a flexible, full-duplex synchronous serial bus. The SPI can operate as a

master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and slaves on a single SPI bus. The slave-select

(NSS) signal can be configured as an input to select the SPI in slave mode, or to disable master mode operation in a multi-master

environment, avoiding contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can also be

configured as a firmware-controlled chip-select output in master mode, or disabled to reduce the number of pins required. Additional

general purpose port I/O pins can be used to select multiple slave devices in master mode.

The SPI module includes the following features:

• Supports 3- or 4-wire operation in master or slave modes.

• Supports external clock frequencies up to SYSCLK / 2 in master mode and SYSCLK / 10 in slave mode.

• Support for four clock phase and polarity options.

• 8-bit dedicated clock clock rate generator.

• Support for multiple masters on the same data lines.

System Management Bus / I2C (SMB0)

The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specifica-

tion, version 1.1, and compatible with the I2C serial bus.

The SMBus module includes the following features:

• Standard (up to 100 kbps) and Fast (400 kbps) transfer speeds.

• Support for master, slave, and multi-master modes.

• Hardware synchronization and arbitration for multi-master mode.

• Clock low extending (clock stretching) to interface with faster masters.

• Hardware support for 7-bit slave and general call address recognition.

• Firmware support for 10-bit slave address decoding.

• Ability to inhibit all slave states.

• Programmable data setup/hold times.

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System Overview

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External Memory Interface (EMIF0)

The External Memory Interface (EMIF) enables access of off-chip memories and memory-mapped devices connected to the GPIO

ports. The external memory space may be accessed using the external move instruction (MOVX) with the target address specified in

either 8-bit or 16-bit formats.

• Supports multiplexed memory access.

• Four external memory modes:

• Internal only.

• Split mode without bank select.

• Split mode with bank select.

• External only

• Configurable ALE (address latch enable) timing.

• Configurable address setup and hold times.

• Configurable write and read pulse widths.

16/32-bit CRC (CRC0)

The cyclic redundancy check (CRC) module performs a CRC using a 16-bit or 32-bit polynomial. CRC0 accepts a stream of 8-bit data

and posts the result to an internal register. In addition to using the CRC block for data manipulation, hardware can automatically CRC

the flash contents of the device.

The CRC module is designed to provide hardware calculations for flash memory verification and communications protocols. The CRC

module includes the following features:

• Support for CCITT-16 polynomial (0x1021).

• Support for CRC-32 polynomial (0x04C11DB7).

• Byte-level bit reversal.

• Automatic CRC of flash contents on one or more 1024-byte blocks.

• Initial seed selection of 0x0000/0x00000000 or 0xFFFF/0xFFFFFFFF.

1.7 Analog

Programmable Current Reference (IREF0)

The programmable current reference (IREF0) module enables current source or sink with two output current settings: Low Power Mode

and High Current Mode. The maximum current output in Low Power Mode is 63 µA (1 µA steps) and the maximum current output in

High Current Mode is 504 µA (8 µA steps).

The IREF module includes the following features:

• Capable of sourcing or sinking current in programmable steps.

• Two operational modes: Low Power Mode and High Current Mode.

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System Overview

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10-Bit Analog-to-Digital Converter (ADC0)

The ADC is a successive-approximation-register (SAR) ADC with 10- and 8-bit modes, integrated track-and hold and a programmable

window detector. The ADC is fully configurable under software control via several registers. The ADC may be configured to measure

different signals using the analog multiplexer. The voltage reference for the ADC is selectable between internal and external reference

sources.

• Up to 22 external inputs.

• Single-ended 10-bit mode.

• Supports an output update rate of 300 ksps samples per second.

• Operation in low power modes at lower conversion speeds.

• Asynchronous hardware conversion trigger, selectable between software, external I/O and internal timer sources.

• Output data window comparator allows automatic range checking.

• Support for burst mode, which produces one set of accumulated data per conversion-start trigger with programmable power-on set-

tling and tracking time.

• Conversion complete and window compare interrupts supported.

• Flexible output data formatting.

• Includes an internal 1.65 V fast-settling reference and support for external reference.

• Integrated temperature sensor.

Low Current Comparators (CMP0, CMP1)

Analog comparators are used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is higher.

External input connections to device I/O pins and internal connections are available through separate multiplexers on the positive and

negative inputs. Hysteresis, response time, and current consumption may be programmed to suit the specific needs of the application.

The comparator module includes the following features:

• Up to 12 external positive inputs.

• Up to 11 external negative inputs.

• Additional input options:

• Capacitive Sense Comparator output.

• VDD.

• VDD divided by 2.

• Internal connection to LDO output.

• Direct connection to GND.

• Synchronous and asynchronous outputs can be routed to pins via crossbar.

• Programmable hysteresis between 0 and +/-20 mV.

• Programmable response time.

• Interrupts generated on rising, falling, or both edges.

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System Overview

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1.8 Reset Sources

Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur:

•The core halts program execution.

• Module registers are initialized to their defined reset values unless the bits reset only with a power-on reset.

• External port pins are forced to a known state.

• Interrupts and timers are disabled.

All registers are reset to the predefined values noted in the register descriptions unless the bits only reset with a power-on reset. The

contents of RAM are unaffected during a reset; any previously stored data is preserved as long as power is not lost. The Port I/O latch-

es are reset to 1 in open-drain mode. Weak pullups are enabled during and after the reset. For Supply Monitor and power-on resets,

the RSTb pin is driven low until the device exits the reset state. On exit from the reset state, the program counter (PC) is reset, and the

system clock defaults to an internal oscillator. The Watchdog Timer is enabled, and program execution begins at location 0x0000.

Reset sources on the device include the following:

• Power-on reset

• External reset pin

• Comparator reset

• Software-triggered reset

• Supply monitor reset (monitors VDD supply)

• Watchdog timer reset

• Missing clock detector reset

• Flash error reset

• RTC0 alarm or oscillator failure

1.9 Debugging

The EFM8SB2 devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow flash programming and in-system debug-

ging with the production part installed in the end application. The C2 interface uses a clock signal (C2CK) and a bi-directional C2 data

signal (C2D) to transfer information between the device and a host system. See the C2 Interface Specification for details on the C2

protocol.

1.10 Bootloader

All devices come pre-programmed with a UART bootloader. This bootloader resides in flash and can be erased if it is not needed.

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System Overview

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2. Memory Organization

2.1 Memory Organization

The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory

spaces: program memory and data memory. Program and data memory share the same address space but are accessed via different

instruction types. Program memory consists of a non-volatile storage area that may be used for either program code or non-volatile

data storage. The data memory, consisting of "internal" and "external" data space, is implemented as RAM, and may be used only for

data storage. Program execution is not supported from the data memory space.

2.2 Program Memory

The CIP-51 core has a 64 KB program memory space. The product family implements some of this program memory space as in-sys-

tem, re-programmable flash memory. Flash security is implemented by a user-programmable location in the flash block and provides

read, write, and erase protection. All addresses not specified in the device memory map are reserved and may not be used for code or

data storage.

MOVX Instruction and Program Memory

The MOVX instruction in an 8051 device is typically used to access external data memory. On the devices, the MOVX instruction is

normally used to read and write on-chip XRAM, but can be re-configured to write and erase on-chip flash memory space. MOVC in-

structions are always used to read flash memory, while MOVX write instructions are used to erase and write flash. This flash access

feature provides a mechanism for the product to update program code and use the program memory space for non-volatile data stor-

age.

2.3 Data Memory

The RAM space on the chip includes both an "internal" RAM area which is accessed with MOV instructions, and an on-chip "external"

RAM area which is accessed using MOVX instructions. Total RAM varies, based on the specific device. The device memory map has

more details about the specific amount of RAM available in each area for the different device variants.

Internal RAM

There are 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memo-

ry are used for general purpose registers and scratch pad memory. Either direct or indirect addressing may be used to access the lower

128 bytes of data memory. Locations 0x00 through 0x1F are addressable as four banks of general purpose registers, each bank con-

sisting of eight byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as bytes or as 128 bit

locations accessible with the direct addressing mode.

The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the same address space as the

Special Function Registers (SFR) but is physically separate from the SFR space. The addressing mode used by an instruction when

accessing locations above 0x7F determines whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. In-

structions that use direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the upper

128 bytes of data memory.

General Purpose Registers

The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of general-purpose registers. Each

bank consists of eight byte-wide registers designated R0 through R7. Only one of these banks may be enabled at a time. Two bits in

the program status word (PSW) register, RS0 and RS1, select the active register bank. This allows fast context switching when entering

subroutines and interrupt service routines. Indirect addressing modes use registers R0 and R1 as index registers.

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Memory Organization

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Bit Addressable Locations

In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through 0x2F are also ac-

cessible as 128 individually addressable bits. Each bit has a bit address from 0x00 to 0x7F. Bit 0 of the byte at 0x20 has bit address

0x00 while bit 7 of the byte at 0x20 has bit address 0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished

from a full byte access by the type of instruction used (bit source or destination operands as opposed to a byte source or destination).

The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where XX is the byte address and B

is the bit position within the byte. For example, the instruction:

Mov C, 22.3h

moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag.

Stack

A programmer's stack can be located anywhere in the 256-byte data memory. The stack area is designated using the Stack Pointer

(SP) SFR. The SP will point to the last location used. The next value pushed on the stack is placed at SP+1 and then SP is incremen-

ted. A reset initializes the stack pointer to location 0x07. Therefore, the first value pushed on the stack is placed at location 0x08, which

is also the first register (R0) of register bank 1. Thus, if more than one register bank is to be used, the SP should be initialized to a

location in the data memory not being used for data storage. The stack depth can extend up to 256 bytes.

External RAM

On devices with more than 256 bytes of on-chip RAM, the additional RAM is mapped into the external data memory space (XRAM).

Addresses in XRAM area accessed using the external move (MOVX) instructions.

Note: The 16-bit MOVX write instruction is also used for writing and erasing the flash memory. More details may be found in the flash

memory section.

EFM8SB2 Reference Manual

Memory Organization

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