Silicon Laboratories I2C User manual

Si5338

I2C-PROGRAMMABLE ANY-FREQUENCY, ANY-OUTPUT

QUAD CLOCK GENERATOR

Features

Applications

Description

The Si5338 is a high-performance, low-jitter clock generator capable of

synthesizing any frequency on each of the device's four output drivers. This timing

IC is capable of replacing up to four different frequency crystal oscillators or

operating as a frequency translator. Using its patented MultiSynth™ technology,

the Si5338 allows generation of four independent clocks with 0 ppm precision.

Each output clock is independently configurable to support various signal formats

and supply voltages. The Si5338 provides low-jitter frequency synthesis in a

space-saving 4 x 4 mm QFN package. The device is programmable via an I2C/

SMBus-compatible serial interface and supports operation from a 1.8, 2.5, or

3.3 V core supply. I2C device programming is made easy with the ClockBuilder™

Desktop software available at www.silabs.com/ClockBuilder.

Low power MultiSynth™ technology

enables independent, any-frequency

synthesis on four differential output

drivers

Highly-configurable output drivers with

up to four differential outputs, eight

single-ended clock outputs, or a

combination of both

Low phase jitter of 0.7 ps RMS typ

High precision synthesis allows true

zero ppm frequency accuracy on all

outputs

Flexible input reference:

External crystal: 8 to 30 MHz

CMOS input: 5 to 200 MHz

SSTL/HSTL input: 5 to 350 MHz

Differential input: 5 to 710 MHz

Independently configurable outputs

support any frequency or format:

LVPECL/LVDS: 0.16 to 710 MHz

HCSL: 0.16 to 250 MHz

CMOS: 0.16 to 200 MHz

SSTL/HSTL: 0.16 to 350 MHz

Independent output voltage per driver:

1.5, 1.8, 2.5, or 3.3 V

Single supply core with excellent

PSRR: 1.8, 2.5, 3.3 V

Independent frequency increment/

decrement feature enables

glitchless frequency adjustments in

1 ppm steps

Independent phase adjustment on

each of the output drivers with an

accuracy of <20 ps steps

Highly configurable spread

spectrum (SSC) on any output:

Any frequency from 5 to 350 MHz

Any spread from 0.5 to 5.0%

Any modulation rate from 33 to

63 kHz

External feedback mode allows

zero-delay mode

Loss of lock and loss of signal

alarms

I2C/SMBus compatible interface

Easy to use programming software

Small size: 4 x 4 mm, 24-QFN

Low power: 45 mA core supply typ

Wide temperature range: –40 to

+85 °C

Ethernet switch/router

PCI Express 2.0/3.0

Broadcast video/audio timing

Processor and FPGA clocking

Any-frequency clock conversion

MSAN/DSLAM/PON

Fibre Channel, SAN

Telecom line cards

1 GbE and 10 GbE

Ordering Information:

See page 41.

Pin Assignments

IN1

CLK2B

CLK2A

VDDO2

VDDO1

CLK1B

CLK1A

VDD VDD

SCL

CLK3A

CLK3B

INTR

SDA

VDDO0

CLK0B

CLK0A

RSVD_GND

VDDO3

GND

Pad

613

987

IN2

IN3

IN4

IN5

IN6

Top View

11 12

192021

222324

Si5338

2 Rev. 1.2

Functional Block Diagram

Phase

Frequency

Detector

Loop

Filter VCO

CLK0A

÷P2

VDDO1

VDDO2

VDDO3

VDDO0

MultiSynth

÷M0

I2C_LSB/PDEC/FDEC

OEB/PINC/FINC

CLK0B

CLK1A

CLK1B

CLK2A

CLK2B

CLK3A

CLK3B

÷P1

IN3

IN2

IN1

÷R1

MultiSynth

÷M1

MultiSynth

÷M2

MultiSynth

÷M3

IN6

IN4

IN5

Osc

MultiSynth

÷N

Control NVM

(OTP)

÷R0

÷R2

÷R3

Synthesis

Stage 1

(PLL)

Synthesis

Stage 2 Output

Stage

P1DIV_IN

Control & Memory

SCL

SDA

INTR

VDD

ref

RAM

P2DIV_IN

noclk

Si5338

Rev. 1.2 3

TABLE OF CONTENTS

Section Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

3.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

3.2. Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

3.3. Synthesis Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

3.4. Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

3.5. Configuring the Si5338 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

3.6. Status Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

3.7. Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

3.8. Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

3.9. Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

3.10. Features of the Si5338 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

4. Applications of the Si5338 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

4.1. Free-Running Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

4.2. Synchronous Frequency Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

4.3. Configurable Buffer and Level Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

5. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

6. Si5338 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

7. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

8. Device Pinout by Part Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

9. Package Outline: 24-Lead QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

10. Recommended PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

11. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

11.1. Si5338 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

11.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

12. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

13. Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

13.1. Description: Spread Modulation Rate and Nominal Frequency Error . . . . . . . . . . .42

13.2. Affected Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

13.3. Impacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

13.4. Workarounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

13.5. Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Si5338

4 Rev. 1.2

1. Electrical Specifications

Table 1. Recommended Operating Conditions

(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Ambient Temperature TA–40 25 85 °C

Core Supply Voltage VDD

2.97 3.3 3.63 V

2.25 2.5 2.75 V

1.71 1.8 1.98 V

Output Buffer Supply

Voltage VDDOn 1.4 — 3.63 V

Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.

Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.

Table 2. Absolute Maximum Ratings1

Parameter Symbol Test Condition Value Unit

DC Supply Voltage VDD –0.5 to 3.8 V

Storage Temperature Range TSTG –55 to 150 °C

ESD Tolerance HBM

(100 pF, 1.5 k)2.5 kV

ESD Tolerance CDM 550 V

ESD Tolerance MM 175 V

Latch-up Tolerance JESD78 Compliant

Junction Temperature TJ150 °C

Peak Soldering Reflow Temperature2260 °C

Notes:

1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be

restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum

rating conditions for extended periods may affect device reliability.

2. Refer to JEDEC J-STD-020 standard for more information.

Si5338

Rev. 1.2 5

Table 3. DC Characteristics

(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Core Supply Current IDD 100 MHzonall outputs,

25 MHz refclk —4560mA

Core Supply Current

(Buffer Mode) IDDB 50 MHz refclk — 12 — mA

Output Buffer Supply Current IDDOx

LVPECL, 710 MHz — — 30 mA

LVDS, 710 MHz — — 8 mA

HCSL, 250 MHz

2pFload ——20mA

CML, 350 MHz — 12 — mA

SSTL, 350 MHz — — 19 mA

CMOS, 50 MHz

15 pF load1—6 9mA

CMOS, 200 MHz1,2

3.3 V VDD0 —1318mA

CMOS, 200 MHz1,2

2.5 V —1014mA

CMOS, 200 MHz1,2

1.8 V —710mA

HSTL, 350 MHz — — 19 mA

Notes:

1. Single CMOS driver active.

2. Measured into a 5” 50 trace with 2 pF load.

Table 4. Thermal Characteristics

Parameter Symbol Test Condition Value Unit

Thermal Resistance

Junction to Ambient JA Still Air 37 °C/W

Thermal Resistance

Junction to Case JC Still Air 25 °C/W

Si5338

6 Rev. 1.2

Table 5. Performance Characteristics

(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

PLL Acquisition Time tACQ ——25 ms

PLL Tracking Range fTRACK 5000 20000 — ppm

PLL Loop Bandwidth fBW —1.6— MHz

MultiSynth Frequency

Synthesis Resolution fRES Output frequency < Fvco/8 0 0 1 ppb

CLKIN Loss of Signal Detect

Time tLOS —2.6 5 µs

CLKIN Loss of Signal Release

Time tLOSRLS 0.01 0.2 1 µs

PLL Loss of Lock Detect Time tLOL —510ms

POR to Output Clock Valid

(Pre-programmed Devices) tRDY —— 2 ms

Input-to-Output Propagation

Delay tPROP Buffer Mode

(PLL Bypass) —2.5 4 ns

Output-Output Skew tDSKEW Rn divider = 11——100 ps

POR to I2C Ready ——15 ms

Programmable Initial

Phase Offset POFFSET –45 — +45 ns

Phase Increment/Decrement

Accuracy PSTEP ——20 ps

Phase Increment/Decrement

Range PRANGE –45 — +45 ns

MultiSynth range for phase

increment/decrement fPRANGE 5—Fvco/8

2MHz

Phase Increment/Decrement

Update Time PUPDATE Pin control2,3

MultiSynth output >18 MHz 667 — — ns

Notes:

1. Outputs at integer-related frequencies and using the same driver format. See "3.10.3. Programmable Initial Phase

Offset" on page 26.

2. The maximum step size is only limited by the register lengths; however, the MultiSynth output frequency must be kept

between 5 MHz and Fvco/8.

3. Update rate via I2C is also limited by the time it takes to perform a write operation.

4. Default value is 0.5% down spread.

5. Default value is ~31.5 kHz.

Si5338

Rev. 1.2 7

Phase Increment/Decrement

Update Time PUPDATE Pin control2,3

MultiSynth output <18 MHz

Number of periods of

MultiSynth output frequency

—1012Periods

Frequency Increment/

Decrement Step Size fSTEP R divider not used 1 — See

Note 2ppm

MultiSynth range for frequency

increment/decrement fRANGE R divider not used 5 — Fvco/8 MHz

Frequency Increment/

Decrement Update Time fUPDATE Pin control2,3

MultiSynth output >18 MHz ——667 ns

Frequency Increment/

Decrement Update Time fUPDATE Pin control2,3

MultiSynth output <18 MHz

Number of periods of

MultiSynth output frequency

—1012Periods

Spread Spectrum PP

Frequency Deviation SSDEV MultiSynth Output < ~Fvco/8 0.1 — 5.04%

Spread Spectrum Modulation

Rate SSDEV MultiSynthOutput<~Fvco/8 30 — 635kHz

Table 5. Performance Characteristics (Continued)

(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Notes:

1. Outputs at integer-related frequencies and using the same driver format. See "3.10.3. Programmable Initial Phase

Offset" on page 26.

2. The maximum step size is only limited by the register lengths; however, the MultiSynth output frequency must be kept

between 5 MHz and Fvco/8.

3. Update rate via I2C is also limited by the time it takes to perform a write operation.

4. Default value is 0.5% down spread.

5. Default value is ~31.5 kHz.

Si5338

8 Rev. 1.2

Table 6. Input and Output Clock Characteristics

(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Units

Input Clock (AC Coupled Differential Input Clocks on Pins IN1/2, IN5/6)1

Frequency fIN 5—710MHz

Differential Voltage

Swing VPP 710 MHz input 0.4 — 2.4 VPP

Rise/Fall Time2tR/tF20%–80% — — 1.0 ns

Duty Cycle DC < 1 ns tr/tf 40 — 60 %

Duty Cycle DC

(PLL bypass)3< 1 ns tr/tf 45 — 55 %

Input Impedance1RIN 10 — — k

Input Capacitance CIN —3.5—pF

Input Clock (DC-Coupled Single-Ended Input Clock on Pins IN3/4)

Frequency fIN CMOS 5 — 200 MHz

Input Voltage VI–0.1 — 3.73 V

Input Voltage Swing 200 MHz 0.8 — VDD+10% Vpp

Rise/Fall Time4tR/tF10%–90% — — 4 ns

Rise/Fall Time4tR/tF20%–80% — — 2.3 ns

Duty Cycle5DC < 4 ns tr/tf 40 — 60 %

Input Capacitance CIN —2.0—pF

Output Clocks (Differential)

Frequency6fOUT LVPECL, LVDS,

CML 0.16 — 350 MHz

367 — 473.33 MHz

550 — 710 MHz

HCSL 0.16 — 250 MHz

Notes:

1. Use an external 100 resistor to provide load termination for a differential clock. See Figure 3.

2. For best jitter performance, keep the midpoint differential input slew rate on pins 1,2,5,6 faster than 0.3 V/ns.

3. Minimum input frequency in clock buffer mode (PLL bypass) is 5 MHz. Operation to 1 MHz is also supported in buffer

mode, but loss-of-signal (LOS) status is not functional.

4. For best jitter performance, keep the mid point input single ended slew rate on pins 3 or 4 faster than 1 V/ns.

5. Not in PLL bypass mode.

6. Only two unique frequencies above 350 MHz can be simultaneously output, Fvco/4 and Fvco/6. See "3.3. Synthesis

Stages" on page 18.

7. CML output format requires ac-coupling of the differential outputs to a differential 100 load at the receiver.

8. Includes effect of internal series 22 resistor.

Si5338

Rev. 1.2 9

LVPECL Output

Voltage VOC common mode — VDDO–

1.45 V —V

VSEPP peak-to-peak sin-

gle-ended swing 0.55 0.8 0.96 VPP

LVDS Output Voltage

(2.5/3.3 V) VOC common mode 1.125 1.2 1.275 V

VSEPP Peak-to-Peak

Single-Ended

Swing

0.25 0.35 0.45 VPP

LVDS Output

Voltage (1.8 V) VOC Common Mode 0.8 0.875 0.95 V

VSEPP Peak-to-Peak

Single-Ended

Swing

0.25 0.35 0.45 VPP

HCSL Output Voltage VOC Common Mode 0.35 0.375 0.400 V

VSEPP Peak-to-Peak

Single-Ended

Swing

0.575 0.725 0.85 VPP

CML Output Voltage VOC Common Mode — See Note 7—V

VSEPP Peak-to-Peak

Single-Ended

Swing

0.67 0.860 1.07 VPP

Rise/Fall Time tR/tF20%–80% — — 450 ps

Duty Cycle5DC 45 — 55 %

Output Clocks (Single-Ended)

Frequency fOUT CMOS 0.16 — 200 MHz

SSTL, HSTL 0.16 — 350 MHz

CMOS 20%–80%

Rise/Fall Time tR/tF2 pF load — 0.45 0.85 ns

CMOS 20%–80%

Rise/Fall Time tR/tF15 pF load — — 2.0 ns

Table 6. Input and Output Clock Characteristics (Continued)

(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Units

Notes:

1. Use an external 100 resistor to provide load termination for a differential clock. See Figure 3.

2. For best jitter performance, keep the midpoint differential input slew rate on pins 1,2,5,6 faster than 0.3 V/ns.

3. Minimum input frequency in clock buffer mode (PLL bypass) is 5 MHz. Operation to 1 MHz is also supported in buffer

mode, but loss-of-signal (LOS) status is not functional.

4. For best jitter performance, keep the mid point input single ended slew rate on pins 3 or 4 faster than 1 V/ns.

5. Not in PLL bypass mode.

6. Only two unique frequencies above 350 MHz can be simultaneously output, Fvco/4 and Fvco/6. See "3.3. Synthesis

Stages" on page 18.

7. CML output format requires ac-coupling of the differential outputs to a differential 100 load at the receiver.

8. Includes effect of internal series 22 resistor.

Si5338

10 Rev. 1.2

CMOS Output

Resistance —50—

SSTL Output

Resistance —50—

HSTL Output

Resistance —50—

CMOS Output

Voltage8VOH 4 mA load VDDO – 0.3 — V

VOL 4 mA load — 0.3 V

SSTL Output Voltage VOH SSTL-3

VDDOx = 2.97 to

3.63 V

0.45xVDDO+0.41 — — V

VOL — — 0.45xVDDO

–0.41 V

VOH SSTL-2

VDDOx = 2.25to

2.75 V

0.5xVDDO+0.41 — — V

VOL — — 0.5xVDDO–

0.41 V

VOH SSTL-18

VDDOx = 1.71 to

1.98 V

0.5xVDDO+0.34 — V

VOL — — 0.5xVDDO–

0.34 V

HSTL Output Voltage VOH VDDO = 1.4 to

1.6 V 0.5xVDDO+0.3 — — V

VOL — — 0.5xVDDO –

0.3 V

Duty Cycle5DC 45 — 55 %

Table 6. Input and Output Clock Characteristics (Continued)

(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Units

Notes:

1. Use an external 100 resistor to provide load termination for a differential clock. See Figure 3.

2. For best jitter performance, keep the midpoint differential input slew rate on pins 1,2,5,6 faster than 0.3 V/ns.

3. Minimum input frequency in clock buffer mode (PLL bypass) is 5 MHz. Operation to 1 MHz is also supported in buffer

mode, but loss-of-signal (LOS) status is not functional.

4. For best jitter performance, keep the mid point input single ended slew rate on pins 3 or 4 faster than 1 V/ns.

5. Not in PLL bypass mode.

6. Only two unique frequencies above 350 MHz can be simultaneously output, Fvco/4 and Fvco/6. See "3.3. Synthesis

Stages" on page 18.

7. CML output format requires ac-coupling of the differential outputs to a differential 100 load at the receiver.

8. Includes effect of internal series 22 resistor.

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