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2016, SiFive Inc. All rights reserved. 3
Quad-SPI Flash
A dedicated quad-SPI (QSPI) flash interface is provided to hold code and data for the system.
The QSPI interface supports burst reads of 32 bytes over TileLink to accelerate instruction cache
refills. The QSPI can be programmed to support eXecute-In-Place modes to reduce SPI command
overhead on instruction cache refills. The QSPI interface also supports single-word data reads
over the primary TileLink interface, as well as programming operations using memory-mapped
control registers.
GPIO Complex
The GPIO complex manages the connection of digital I/O pads to digital peripherals, including
SPI, UART, and PWM controllers, as well as for regular programmed I/O operations. FE310-G000
has two additional QSPI controllers in the GPIO block, one with four chip selects and one with
one. FE310-G000 also has two UARTs. FE310-G000 has three PWM controllers, two with 16-bit
precision and one with 8-bit precision.
Always-On (AON) Block
The AON block contains the reset logic for the chip, an on-chip low-frequency oscillator, a watch-
dog timer, connections for an off-chip low-frequency crystal oscillator, the real-time clock, a pro-
grammable power-management unit, and 16×32-bit backup registers that retain state while the
rest of the chip is powered down.
The AON can be instructed to put the system to sleep. The AON can be programmed to exit sleep
mode on a real-time clock interrupt or when the external digital wakeup pin, dwakeup n, is pulled
low. The dwakeup n input supports wired-OR connections of multiple wakeup sources.
Power Supply
FE310-G000 requires two dedicated power rails providing 1.8 V power to the always-on block and
core logic, and 3.3 V to the I/O pads.
