SiFive E31 User manual
SiFive E31 Core Complex Manual
v2p0
© SiFive, Inc.
SiFive E31 Core Complex Manual
Proprietary Notice
Copyright © 2017–2018, SiFive Inc. All rights reserved.
Information in this document is provided “as is,” with all faults.
SiFive expressly disclaims all warranties, representations, and conditions of any kind, whether
express or implied, including, but not limited to, the implied warranties or conditions of mer-
chantability, fitness for a particular purpose and non-infringement.
SiFive does not assume any liability rising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation indirect, incidental, spe-
cial, exemplary, or consequential damages.
SiFive reserves the right to make changes without further notice to any products herein.
Release Information
Version Date Changes
v2p0 June 01, 2018
• Updated E31 Core Complex definition; 4 hw
breakpoints and 127 Global interrupts.
• Moved Interface and Debug Interface chapters
to User Guide.
v1p2 October 11, 2017
• Core Complex branding
• Added references
• Updated interrupt chapter
v1p1 August 25, 2017
• Updated text descriptions
• Updated register and memory map tables for
consistency
v1p0 May 04, 2017
• Initial release
• Describes the functionality of the SiFive E31
Core Complex
Contents
1 Introduction .............................................................................................................. 4
1.1 E31 Core Complex Overview .......................................................................................4
1.2 E31 R SC‑V Core ....................................................................................................... 5
1.3 Debug Support ........................................................................................................... 5
1.4 nterrupts ................................................................................................................... 6
1.5 Memory System.......................................................................................................... 6
2 List of Abbreviations and Terms ...................................................................7
3 E31 RISC-V Core .................................................................................................... 8
3.1 nstruction Memory System..........................................................................................8
3.1.1 -Cache Reconfigurability ....................................................................................9
3.2 nstruction Fetch Unit .................................................................................................. 9
3.3 Execution Pipeline ...................................................................................................... 9
3.4 Data Memory System................................................................................................10
3.5 Atomic Memory Operations........................................................................................10
3.6 Local nterrupts......................................................................................................... 10
3.7 Supported Modes ..................................................................................................... 11
3.8 Physical Memory Protection (PMP).............................................................................11
3.8.1 Functional Description ......................................................................................11
3.8.2 Region Locking ................................................................................................11
3.9 Hardware Performance Monitor..................................................................................12
4 Memory Map ........................................................................................................... 14
5 Interrupts.................................................................................................................. 15
5.1 nterrupt Concepts .................................................................................................... 15
5.2 nterrupt Entry and Exit..............................................................................................16
5.3 nterrupt Control Status Registers...............................................................................17
1
5.3.1 Machine Status Register (mstatus)..................................................................17
5.3.2 Machine nterrupt Enable Register (mie)............................................................17
5.3.3 Machine nterrupt Pending (mip).......................................................................18
5.3.4 Machine Cause Register (mcause)....................................................................18
5.3.5 Machine Trap Vector (mtvec)............................................................................20
5.4 nterrupt Priorities ..................................................................................................... 21
5.5 nterrupt Latency....................................................................................................... 21
6 Core Local Interruptor (CLINT).....................................................................22
6.1 CL NT Memory Map.................................................................................................. 22
6.2 MS P Registers......................................................................................................... 22
6.3 Timer Registers ........................................................................................................ 23
7 Platform-Level Interrupt Controller (PLIC) .............................................24
7.1 Memory Map ............................................................................................................ 24
7.2 nterrupt Sources ...................................................................................................... 25
7.3 nterrupt Priorities ..................................................................................................... 26
7.4 nterrupt Pending Bits................................................................................................26
7.5 nterrupt Enables ...................................................................................................... 27
7.6 Priority Thresholds .................................................................................................... 28
7.7 nterrupt Claim Process .............................................................................................28
7.8 nterrupt Completion.................................................................................................. 28
8 Debug......................................................................................................................... 30
8.1 Debug CSRs ............................................................................................................ 30
8.1.1 Trace and Debug Register Select (tselect)......................................................30
8.1.2 Trace and Debug Data Registers (tdata1-3)....................................................31
8.1.3 Debug Control and Status Register (dcsr).........................................................32
8.1.4 Debug PC dpc.................................................................................................32
8.1.5 Debug Scratch dscratch ................................................................................32
8.2 Breakpoints .............................................................................................................. 32
8.2.1 Breakpoint Match Control Register mcontrol ....................................................32
8.2.2 Breakpoint Match Address Register (maddress)................................................34
2
8.2.3 Breakpoint Execution........................................................................................34
8.2.4 Sharing Breakpoints Between Debug and Machine Mode ....................................35
8.3 Debug Memory Map.................................................................................................. 35
8.3.1 Debug RAM and Program Buffer (0x300–0x3FF)...............................................35
8.3.2 Debug ROM (0x800–0xFFF)............................................................................35
8.3.3 Debug Flags (0x100–0x110,0x400–0x7FF)....................................................36
8.3.4 Safe Zero Address ...........................................................................................36
9 References .............................................................................................................. 37
3
Chapter 1
Introduction
SiFive’s E31 Core Complex is a high performance implementation of the R SC‑V RV32 MAC
architecture. The SiFive E31 Core Complex is guaranteed to be compatible with all applicable
R SC‑V standards, and this document should be read together with the official R SC‑V user-
level, privileged, and external debug architecture specifications.
A summary of features in the E31 Core Complex can be found in Table 1.
E31 Core Complex Feature Set
Feature Description
Number of Harts 1 Hart.
E31 Core 1× E31 R SC‑V core.
Local nterrupts 16 Local nterrupt signals per hart which can be connected to
off core complex devices.
PL C nterrupts 127 nterrupt signals which can be connected to off core
complex devices.
PL C Priority Levels The PL C supports 7 priority levels.
Hardware Breakpoints 4 hardware breakpoints.
Physical Memory Protection
Unit
PMP with 8 x regions and a minimum granularity of 4 bytes.
Table 1: E31 Core Complex Feature Set
1.1 E31 Core Complex verview
An overview of the SiFive E31 Core Complex is shown in Figure 1. This R SC-V Core P
includes a 32-bit R SC‑V microcontroller core, memory interfaces including an instruction cache
as well as instruction and data tightly integrated memory, local and global interrupt support,
physical memory protection, a debug unit, outgoing external TileLink platform ports, and an
incoming TileLink master port.
4
Figure 1: E31 Core Complex Block Diagram
The E31 Core Complex memory map is detailed in Chapter 4, and the interfaces are described
in full in the E31 Core Complex User Guide.
1.2 E31 RISC‑V Core
The E31 Core Complex includes a 32-bit E31 R SC‑V core, which has a high-performance sin-
gle-issue in-order execution pipeline, with a peak sustainable execution rate of one instruction
per clock cycle. The E31 core supports Machine and User privilege modes as well as standard
Multiply, Atomic, and Compressed R SC‑V extensions (RV32 MAC).
The core is described in more detail in Chapter 3.
1.3 Debug Support
The E31 Core Complex provides external debugger support over an industry-standard JTAG
port, including 4 hardware-programmable breakpoints per hart.
Copyrig t © 2017–2018, SiFive Inc. All rig ts reserved. 5
Debug support is described in detail in Chapter 8, and the debug interface is described in the
E31 Core Complex User Guide.
1.4 Interrupts
The E31 Core Complex supports 16 high-priority, low-latency local vectored interrupts per-hart.
This Core Complex includes a R SC-V standard platform-level interrupt controller (PL C), which
supports 127 global interrupts with 7 priority levels. This Core Complex also provides the stan-
dard R SC‑V machine-mode timer and software interrupts via the Core Local nterruptor
(CL NT).
nterrupts are described in Chapter 5. The CL NT is described in Chapter 6. The PL C is
described in in Chapter 7.
1.5 Memory System
The E31 Core Complex memory system has Tightly ntegrated nstruction and Data Memory
sub-systems optimized for high performance. The instruction subsystem consists of a 16 KiB
2-way instruction cache with the ability to reconfigure a single way into a fixed-address tightly
integrated memory. The data subsystem allows for a maximum DT M size of 64 KiB.
The memory system is described in more detail in Chapter 3.
Copyrig t © 2017–2018, SiFive Inc. All rig ts reserved. 6
Chapter 2
List of Abbreviations and Terms
Term Definition
BHT Branch History Table
BTB Branch Target Buffer
RAS Return-Address Stack
CLINT Core Local nterruptor. Generates per-hart software interrupts and timer
interrupts.
hart HARdware Thread
DTIM Data Tightly ntegrated Memory
ITIM nstruction Tightly ntegrated Memory
JTAG Joint Test Action Group
LIM Loosely ntegrated Memory. Used to describe memory space delivered in
a SiFive Core Complex but not tightly integrated to a CPU core.
PMP Physical Memory Protection
PLIC Platform-Level nterrupt Controller. The global interrupt controller in a
R SC-V system.
TileLink A free and open interconnect standard originally developed at UC Berke-
ley.
R Used to describe a Read Only register field.
RW Used to describe a Read/Write register field.
W Used to describe a Write Only registers field.
WARL Write-Any Read-Legal field. A register field that can be written with any
value, but returns only supported values when read.
WIRI Writes- gnored, Reads- gnore field. A read-only register field reserved for
future use. Writes to the field are ignored, and reads should ignore the
value returned.
WLRL Write-Legal, Read-Legal field. A register field that should only be written
with legal values and that only returns legal value if last written with a
legal value.
WPRI Writes-Preserve Reads- gnore field. A register field that might contain
unknown information. Reads should ignore the value returned, but writes
to the whole register should preserve the original value.
7
Chapter 3
E31 RISC-V Core
This chapter describes the 32-bit E31 R SC‑V processor core used in the E31 Core Complex.
The E31 processor core comprises an instruction memory system, an instruction fetch unit, an
execution pipeline, a data memory system, and support for local interrupts.
The E31 feature set is summarized in Table 2.
Feature Description
SA RV32 MAC.
nstruction Cache 16 KiB 2-way instruction cache.
nstruction Tightly ntegrated Memory The E31 has support for an T M with a maxi-
mum size of 8 KiB.
Data Tightly ntegrated Memory 64 KiB DT M.
Modes The E31 supports the following modes:
Machine Mode, User Mode.
Table 2: E31 Feature Set
3.1 Instruction Memory System
The instruction memory system consists of a dedicated 16 KiB 2-way set-associative instruction
cache. The access latency of all blocks in the instruction memory system is one clock cycle. The
instruction cache is not kept coherent with the rest of the platform memory system. Writes to
instruction memory must be synchronized with the instruction fetch stream by executing a
FENCE. instruction.
The instruction cache has a line size of 64 bytes, and a cache line fill triggers a burst access
outside of the E31 Core Complex. The core caches instructions from executable addresses,
with the exception of the nstruction Tightly ntegrated Memory ( T M), which is further described
in Section 3.1.1. See the E31 Core Complex Memory Map in Chapter 4 for a description of exe-
cutable address regions that are denoted by the attribute X.
Trying to execute an instruction from a non-executable address results in a synchronous trap.
8
Table of contents
Other SiFive Microcontroller manuals
Popular Microcontroller manuals by other brands
AMS
AMS AS7261 Demo Kit user guide
Novatek
Novatek NT6861 manual
Espressif Systems
Espressif Systems ESP8266 SDK AT Instruction Set
Nuvoton
Nuvoton ISD61S00 ChipCorder Design guide
STMicrolectronics
STMicrolectronics ST7 Assembler Linker user manual
Texas Instruments
Texas Instruments Chipcon CC2420DK user manual
Texas Instruments
Texas Instruments TMS320F2837 D Series Workshop Guide and Lab Manual
CYPRES
CYPRES CY14NVSRAMKIT-001 user guide
Texas Instruments
Texas Instruments INA-DUAL-2AMP-EVM user guide
Espressif Systems
Espressif Systems ESP8266EX Programming guide
Abov
Abov AC33M8128L user manual
Laird
Laird BL654PA user guide