SiFive E3* Core IP Series User manual
SiFive Core IP FPGA Eval Kit User Guide
v3p0
© SiFive, Inc.
2SiFive Core IP FPGA Eval Kit User Guide v3p0
SiFive Core IP FPGA Eval Kit User
Guide
Proprietary Notice
Copyright © 2016-2019, SiFive Inc. All rights reserved.
Information in this document is provided “as is”, with all faults.
SiFive expressly disclaims all warranties, representations and conditions of any kind, whether
express or implied, including, but not limited to, the implied warranties or conditions of
merchantability, fitness for a particular purpose and non-infringement.
SiFive does not assume any liability rising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation indirect, incidental, special,
exemplary, or consequential damages.
SiFive reserves the right to make changes without further notice to any products herein.
Release Information
Version Date Changes
v3p0 Feb 28, 2019 Updated for 19.02 Core IP Release
• Supports v19.02 Core IP Package
• Added descriptions for Arty-100T
• Added Chapters for E2, E3/S5, E7/S7 MCS
Images
v2p0 Feb 2, 2018 Updated to match v2p0 of the Evaluation MCS:
• FPGA Eval includes ITIM
• DTIM size increased to 64kiB
• Number of HWBP increased to 8
• Added User Mode Support
• Updated various links
v1p0 May 4, 2017 First release
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ii SiFive Core IP FPGA Eval Kit User Guide v3p0
Contents
SiFive Core IP FPGA Eval Kit User Guide i
List of Figures v
1 Introduction 1
1.1 About this Document .................................. 1
1.2 About this Release ................................... 1
1.3 Evaluation Version Limitations ............................. 1
2 Required Hardware 3
2.1 Xilinx Arty A7 Artix-7 FPGA Evaluation Kit ...................... 3
2.2 USB A to Micro-B Cable ................................ 3
2.3 Olimex ARM-USB-TINY-H Debugger ......................... 3
2.4 USB A to B Cable .................................... 3
2.5 Male-To-Female Jumper Cables (10) ......................... 4
3 Board Setup 5
3.1 Connecting the USB Interface ............................. 5
3.2 Connecting the Debugger ............................... 5
4 FPGA Flash Programming File 9
4.1 Programming the Arty 35T SPI Flash ......................... 9
4.2 Programming the Arty 100T SPI Flash ........................ 10
5 Boot and Run 11
5.1 Serial Setup ....................................... 11
5.1.1 Reset and boot ................................ 13
5.1.2 Load a Program ............................... 13
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iv SiFive Core IP FPGA Eval Kit User Guide v3p0
5.2 Default Demo Program ................................. 13
5.2.1 Terminal Log ................................. 13
6 Software Development Flow 15
6.1 Supported Platforms .................................. 15
6.2 Software Development Using Freedom Studio IDE .................. 15
6.3 Software Development Using Freedom E SDK Command Line Tools ....... 15
6.3.1 Setting Up Freedom-E-SDK ......................... 16
6.3.2 Cloning the Repository ............................ 16
6.4 Freedom E SDK Arty BSP ............................... 17
6.5 Example Programs ................................... 17
6.6 Using the Freedom E SDK ............................... 18
6.6.1 Building an Example ............................. 18
6.6.2 Uploading to the Target Board ........................ 18
6.6.3 Debugging a Target Program ........................ 19
6.6.4 Cleaning a Target Program Build Directory ................. 19
6.6.5 Create a Standalone Project ......................... 19
7 E2 Core IP FPGA Eval Kit MCS Image Contents 21
7.1 Core IP FPGA Eval Kit Memory Map ......................... 21
7.2 Core IP FPGA Eval Kit Clock and Reset ....................... 21
7.3 Core IP FPGA Eval Kit Pinout ............................. 21
8 E3 / S5 Core IP FPGA Eval Kit MCS Image Contents 25
8.1 Core IP FPGA Eval Kit Memory Map ......................... 25
8.2 Core IP FPGA Eval Kit Clock and Reset ....................... 25
8.3 Core IP FPGA Eval Kit Pinout ............................. 25
9 E7 / S7 MCS Image Contents 29
9.1 Core IP FPGA Eval Kit Memory Map ......................... 29
9.2 Core IP FPGA Eval Kit Clock and Reset ....................... 29
9.3 Core IP FPGA Eval Kit Pinout ............................. 29
10 For More Information 33
List of Figures
3.1 Debugging Connections between Olimex ARM-USB-TINY-H and Arty Board’s
PMOD header JD ..................................... 6
3.2 Debug Connections To the Olimex ARM-USB-TINY-H ................. 6
3.3 Debug Connections to the Arty Board JD PMOD Header ................ 6
3.4 Photo of the Arty Board showing USB and Debug Connections ............ 7
7.1 E2 Core IP FPGA Eval Kit Block Diagram ........................ 22
8.1 E3 / S5 Core IP FPGA Eval Kit Block Diagram ..................... 26
9.1 E7 / S7 Core IP FPGA Eval Kit Block Diagram ..................... 30
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vi SiFive Core IP FPGA Eval Kit User Guide v3p0
Chapter 1
Introduction
1.1 About this Document
This document gives necessary information for a user of the SiFive Core IP FPGA Eval Kit. To
learn more about the functionality of your specific Core IP please read the appropriate Core IP
Manual.
This guide will help you download and flash the Core IP FPGA Eval Kit image to an FPGA
development board. It will help you install software tools to allow you to write, upload, and debug
code on the Eval Kit. It also contains information about what is contained in the MCS file for the
Core IP FPGA Eval Kit.
1.2 About this Release
This Eval Kit allows you to prototype and benchmark your target RISC-V software without
modifying, integrating, or synthesizing any Verilog code.
This release is intended for evaluation purposes only.
1.3 Evaluation Version Limitations
Version v19.02 of the Core IP FPGA Eval Kit has the following limitations compared with the fully
functional Core IP:
• DTIM is limited in size to 64kB.
• Peripheral Bus, System Bus, and Front Bus are not exported for additional user connections.
The evaluation can utilize the peripherals included on the FPGA.
• Not all Local and Global interrupts are exported at the top level.
To target a different FPGA platform or perform synthesis or simulation, you may obtain an
Evaluation Version of the Core IP RTL from sifive.com.
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2SiFive Core IP FPGA Eval Kit User Guide v3p0
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