NXP Semiconductors I.MX 6Dual User manual

NXP Semiconductors

Chip Errata

This document details the silicon errata known at the time of publication for the i.MX 6Dual/6Quad and

i.MX 6DualPlus/6QuadPlus multimedia applications processors.

Table 2 provides a revision history for this document.

Table 3 contains a summary of the silicon errata. Bolded rows are specific to either i.MX 6Dual/6Quad or

i.MX 6DualPlus/6QuadPlus (see the errata description column).

Table 4 lists the ARM errata excluded from detailed description in this document.

To identify the silicon revision, refer to the last letter of the part number. See Table 1 for examples.

For additional information, see either the i.MX 6Dual/6Quad Applications Processor Reference Manual

(IMX6DQRM) or the i.MX 6DualPlus/6QuadPlus Applications Processor Reference Manual

(IMX6DQPRM).

Table 1. Part number/silicon revision examples

Example Part Numbers Silicon Revision

MCIMX6Q6AVT10ACi.MX 6Quad, Revision 1.2

MCIMX6D6AVT10ADi.MX 6Dual, Revision 1.3

MCIMX6QP6AVT1AAi.MX 6QuadPlus, Revision 1.0

MCIMX6DP6AVT1AAi.MX 6DualPlus, Revision 1.0

IMX6DQCE

Rev. 6.1, 06/2016

Chip Errata for

the i.MX 6Dual/6Quad and

i.MX 6DualPlus/6QuadPlus

Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016

2NXPSemiconductors

NOTE

BSP functionality in some configurations and use cases, or your own/added

software functionality, may be affected by an erratum. We have made our

bestattemptatprovidingsoftwareworkaroundrequirementsandBSPstatus

foreacherratuminthisdocument.Whether a software workaround hasbeen

implemented in the BSP or not, the user should evaluate his specific use

cases and take any (additional) necessary actions to prevent the occurrence

or impact of each erratum. Go through your support channel if you have any

questions or concerns.

Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016

NXP Semiconductors 3

The following table provides a revision history for this document.

Table 2. Document Revision History

Rev.

Number Date Substantive Changes

Rev. 6.1 06/2016 • Updated ERR004536 in Table 3 and ERR004536 changing from: Silicon revision 1.3 to; No fix

scheduled and removing i.MX 6Dual/6Quad Only.

Rev. 6 02/2016 • Updated the following i.MX 6Dual/6Quad-specific errata:

–ERR004300, ERR004484, ERR004536, ERR005216, ERR005723, ERR005768, ERR005908,

ERR006282, ERR006687, ERR007966, ERR008506,

• Added the following i.MX 6Dual/6Quad-specific errata:

–ERR007926, ERR008587, ERR009219

• Added the following i.MX 6DualPlus/6QuadPlus-specific errata:

–ERR009619, ERR009623, ERR009624

• Added the following i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus-specific errata:

– ERR007555, ERR007556, ERR007557, ERR007573, ERR007575, ERR007577, ERR007881,

ERR008990, ERR009165, ERR009218, ERR009535, ERR009596, ERR009598, ERR009604,

ERR009605, ERR009606, ERR009678, ERR009704, ERR009742, ERR009743, ERR009858

• Updated the following i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus-specific errata:

– ERR004366

• Added Table 4 describing ARM errata not documented in this deliverable.

• Updated the following ARM errata:

• ERR003717, ERR003718, ERR003719, ERR003720, ERR003721, ERR003723, ERR003724,

ERR003725, ERR003726, ERR003727, ERR003728, ERR003729, ERR003730, ERR003731,

ERR003732, ERR003735, ERR003736, ERR003737, ERR003738, ERR003740, ERR003741,

ERR004324, ERR004326, ERR004327, ERR005175, ERR005183, ERR005185, ERR005187,

ERR005199, ERR005200, ERR005382, ERR005383, ERR005385, ERR005386, ERR005387,

ERR007006, ERR007007, ERR007008

• Removed errata:

– ERR005779

Rev. 5 06/2015 • Update to ERR006282

Rev. 4 06/2014 • Added ERR007805

• Added ERR008001

• Added ERR008000

• Added ERR007554

• Added ERR007926

• Added ERR007966

• Removed ERR003742. This item was ARM erratum 732672. Access to this information must come

directly from ARM.

• Removed ERR007005. This item was ARM erratum 791420. Access to this information must come

directly from ARM.

Rev. 3 11/2013 • Added the following: ERR007005, ERR007006, ERR007007, ERR007008, ER007117, ER007220,

ERR007265, ERR007266

• Updated the following: ERR003740, ERR003742, ERR003778, ERR004512

Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016

4NXPSemiconductors

Rev. 2 5/2013 • Deleted ERR003775—Addressed in rev. 1 of the i.MX 6Dual/6Quad Applications Processor Reference

Manual (IMX6DQRM).

• Added the following errata:

– ERR006282

– ERR006308

– ERR006358

– ERR006687

• Updated the following:

– ERR004353

– ERR004446

– ERR005829

Rev. 1.1 2/2013 Restored pages omitted in Rev. 1.

Rev. 1 1/2013 • Added the following:

–ERR006223

–ERR006259

–ERR006281

• Updated ERR004367

– Deleted ERR005384 (not relevant to this Freescale implementation of the ARM®core)

Rev. 0 10/2012 Initial public release.

Table 2. Document Revision History (continued)

Rev.

Number Date Substantive Changes

Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016

NXP Semiconductors 5

Table 3. Summary of Silicon Errata

Errata Name Solution Page

Analog

ERR005852 Analog: Transition from Deep Sleep Mode to LDO Bypass Mode may cause the slow

response of the VDDARM_CAP output No fix scheduled 15

ARM®

ERR003717 ARM: 740657—Global Timer can send two interrupts for the same event No fix scheduled 16

ERR003718 ARM: 743622—Faulty logic in the Store Buffer may lead to data corruption No fix scheduled 18

ERR003719 ARM/MP: 751469 — Overflow in PMU counters may not be detected No fix scheduled 20

ERR003720 ARM/MP: 751472—An interrupted ICIALLUIS operation may prevent the completion

of a following broadcast operation No fix scheduled 22

ERR003721 ARM: 751473—Under very rare circumstances, Automatic Data prefetcher can lead

to deadlock or data corruption No fix scheduled 24

ERR003723 ARM: 751476—May miss a watchpoint on the second part of an unaligned access

that crosses a page boundary No fix scheduled 25

ERR003724 ARM: 754322—Possible faulty MMU translations following an ASID switch No fix scheduled 26

ERR003725 ARM: 725631—ISB is counted in Performance Monitor events 0x0C and 0x0D No fix scheduled 28

ERR003726 ARM: 729817—MainID register alias addresses are not mapped on Debug APB

interface No fix scheduled 29

ERR003727 ARM: 729818—In debug state, next instruction is stalled when sdabort flag is set,

instead of being discarded No fix scheduled 30

ERR003728 ARM: 740661—Event 0x74 / PMUEVENT[38:37] may be inaccurate No fix scheduled 31

ERR003729 ARM: 740663—Event 0x68 / PMUEVENT[9:8] may be inaccurate No fix scheduled 32

ERR003730 ARM: 743623—Bad interaction between a minimum of seven PLDs and one

Non-Cacheable LDM can lead to a deadlock No fix scheduled 34

ERR003731 ARM: 743626—An imprecise external abort, received while the processor enters

WFI, may cause a processor deadlock No fix scheduled 36

ERR003732 ARM: 751471—DBGPCSR format is incorrect No fix scheduled 37

ERR003733 ARM: 751480—Conditional failed LDREXcc can set the exclusive monitor No fix scheduled 39

ERR003734 ARM: 752519—An imprecise abort may be reported twice on non-cacheable reads No fix scheduled 40

ERR003735 ARM: 754323—Repeated Store in the same cache line may delay the visibility of the

Store No fix scheduled 41

ERR003736 ARM: 756421—Sticky Pipeline Advance bit cannot be cleared from debug APB

accesses No fix scheduled 43

ERR003737 ARM: 757119—Some “Unallocated memory hint” instructions generate an

UNDEFINED exception instead of being treated as NOP No fix scheduled 44

ERR003738 ARM/MP: 751475—Parity error may not be reported on full cache line access

(eviction / coherent data transfer / cp15 clean operations) No fix scheduled 45

Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016

6NXPSemiconductors

ERR003739 ARM: 751470—Imprecise abort on the last data of a cache linefill may not be

detected No fix scheduled 46

ERR003740 ARM/PL310: 752271—Double linefill feature can cause data corruption [i.MX

6Dual/6Quad only] No fix scheduled 47

ERR003741 ARM/PL310: 729815—The “High Priority for SO and Dev reads” feature can cause

Quality of Service issues to cacheable read transactions No fix scheduled 48

ERR003743 ARM/PL310: 754670—A continuous write flow can stall a read targeting the same

memory area No fix scheduled 49

ERR004324 ARM/MP: 761319—Ordering of read accesses to the same memory location may not

be ensured No fix scheduled 50

ERR004325 ARM/MP: 764369—Data or unified cache line maintenance operation by MVA may

not succeed on an Inner Shareable memory region No fix scheduled 51

ERR004326 ARM/MP: 761321—MRC and MCR are not counted in event 0x68 No fix scheduled 53

ERR004327 ARM/MP: 764319—Read accesses to DBGPRSR and DBGOSLSR may generate

an unexpected UNDEF No fix scheduled 54

ERR005175 ARM/MP: 771221—PLD instructions may allocate data in the DataCache regardless

of the Cache Enable bit value No fix scheduled 55

ERR005183 ARM/MP: 771224—Visibility of Debug Enable accessrightstoenable/disable tracing

is not ensured by an ISB No fix scheduled 56

ERR005185 ARM/MP: 771225—Speculative cacheable reads to aborting memory region clear

the internal exclusive monitor, may lead to livelock No fix scheduled 57

ERR005187 ARM/MP: 771223—Parity errors on BTAC and GHB are reported on

PARITYFAIL[7:6], regardless of the Parity Enable bit value No fix scheduled 59

ERR005198 ARM/PL310: 780370—DATAERR, TAGERR, and Tag parity errors are incorrectly

sampled by the eviction buffer, leading to data corruption No fix scheduled 60

ERR005199 ARM/MP: 769419—No automatic Store Buffer drain, visibility of written data requires

an explicit Cache Sync operation [i.MX 6Dual/6Quad Only] No fix scheduled 63

ERR005200 ARM/MP: 765569—Prefetcher can cross 4 KB boundary if offset is programmed with

value 23 No fix scheduled 64

ERR005382 ARM/MP: 775419—PMU event 0x0A (exception return) might count twice the LDM

PC ^ instructions with base address register write-back No fix scheduled 65

ERR005383 ARM/MP: 775420—A data cache maintenance operation that aborts, followed by an

ISB and without any DSB in-between, might lead to deadlock No fix scheduled 66

ERR005385 ARM/MP: 782772—A speculative execution of a Load-Exclusive or Store-Exclusive

instruction after a write to Strongly Ordered memory might deadlock the processor No fix scheduled 67

ERR005386 ARM/MP: 782773—Updating a translation entry to move a page mapping might

erroneously cause an unexpected translation fault No fix scheduled 69

ERR005387 ARM/MP: 782774—A spurious event 0x63, “STREX passed,” can be reported on an

LDREX that is preceded by a write to Strongly Ordered memory region No fix scheduled 71

Table 3. Summary of Silicon Errata (continued)

Errata Name Solution Page

Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016

NXP Semiconductors 7

ERR006259 ARM: Debug/trace functions (PMU, PTM and ETB) are disabled with absence of

JTAG_TCK clock after POR No fix scheduled 72

ERR007006 ARM/MP:794072-- Short loop including a DMB instruction might cause a denial of

service No fix scheduled 73

ERR007007 ARM/MP: 794073 -- Speculative instruction fetches with MMU disabled might not

comply with architectural requirements No fix scheduled 75

ERR007008 ARM/MP: 794074 --A write request to Uncacheable Shareable memory region might

be executed twice No fix scheduled 76

ERR009604 ARM (CA9): 845369 — Under very rare timing circumstances, transition into

streaming mode might create a data corruption No fix scheduled 78

ERR009605 ARM (CA9): 761320—Full cache line writes to the same memory region from at least

two processors might deadlock the processor No fix scheduled 80

ERR009742 ARM: 795769 - “Write Context ID" event is updated on read access No fix scheduled 82

ERR009743 ARM: 799770 - DBGPRSR Sticky Reset status bit is set to 1 by the CPUdebug reset

instead of by the CPU non-debug reset No fix scheduled 83

ERR009858 ARM/PL310: 796171 When data banking is implemented, data parity errors can be

incorrectly generated No fix scheduled 84

CAAM

ERR004320 CAAM: Three encryption functions may show up as available, even though they are

not No fix scheduled 85

ERR004347 CAAM: False read access error No fix scheduled 86

ERR004348 CAAM: Internal 16 Kb RAM (CAAM) does not support wrapped accesses No fix scheduled 87

ERR005766 CAAM:CAAMcannothandleinterleavedREAD data“beats”returnedbytwodifferent

slaves in the system, in reply to two different AXI-ID accesses No fix scheduled 88

CCM

ERR006223 CCM: Failure to resume from Wait/Stop mode with power gating No fix scheduled 89

ERR007265 CCM: When improper low-power sequence is used, the SoC enters low power mode

before the ARM core executes WFI No fix scheduled 90

ERR009219 CCM: Asynchronous clock switching can cause unpredictable behavior [i.MX

6Dual/6Quad Only] No fix scheduled 91

eCSPI

ERR009165 eCSPI: TXFIFO empty flag glitch can cause the current FIFO transfer to be sent twice No fix scheduled 93

ERR009535 eCSPI: Burst completion by SS signal in slave mode is not functional No fix scheduled 94

ERR009606 eCSPI: In master mode, burst lengths of 32n+1 will transmit incorrect data No fix scheduled 95

EIM

ERR004446 EIM: AUS mode is nonfunctional for devices larger than 32 MB No fix scheduled 96

Table 3. Summary of Silicon Errata (continued)

Errata Name Solution Page

Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016

8NXPSemiconductors

ERR009218 EIM: Signals fail to drive as outputs during boundary scan test No fix scheduled 97

ENET

ERR004512 ENET: 1 Gb Ethernet MAC (ENET) system limitation No fix scheduled 98

ERR005783 ENET: ENET Status FIFO may overflow due to consecutive short frames No fix scheduled 99

ERR005895 ENET: ENET 1588 channel 2 event capture mode not functional No fix scheduled 100

ERR006358 ENET: Write to Transmit Descriptor Active Register (ENET_TDAR) is ignored No fix scheduled 101

ERR006687 ENET: Only the ENET wake-up interrupt request can wake the system from Wait

mode [i.MX 6Dual/6Quad Only] No fix scheduled 102

ESAI

ERR008000 ESAI: ESAI may encounter channel swap when overrun/underrun occurs No fix scheduled 103

EXSC

ERR004365 EXSC: Exclusive accesses to certain memories are not supported to full AXI

specification No fix scheduled 104

ERR005828 EXSC: Protecting the EIM memory map region causes unpredictable behavior No fix scheduled 105

FlexCAN

ERR005829 FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in

a specific moment during the arbitration process No fix scheduled 106

GPMI

ERR008001 GPMI: GPMI does not support the Set Feature command in Toggle mode No fix scheduled 108

GPU

ERR004341 GPU2D: Accessing GPU2D when it is power-gated will cause a deadlock in the

system No fix scheduled 109

ERR005908 GPU2D: Image quality degradation observed for stretch blits when the stretch factor

is exactly an integer [i.MX 6Dual/6Quad Only] No fix scheduled 110

ERR004300 GPU3D: L1 cache performance drop [i.MX 6Dual/6Quad Only] No fix scheduled 111

ERR004484 GPU3D: L1 cache “Write Address Data” pairing error [i.MX 6Dual/6Quad Only] No fix scheduled 112

ERR005216 GPU3D: Black texels in Android App Singularity 3D [i.MX 6Dual/6Quad Only] No fix scheduled 113

HDMI

ERR003744 HDMI: 9000446457—Audio DMA does not generate an interrupt after software stops

DMA transaction No fix scheduled 114

ERR003745 HDMI: 9000440660—Audio DMA fails to stop after ERROR detection No fix scheduled 115

ERR004308 HDMI:8000504668—The arithmeticunitmayget wrong video timing values although

the FC_* registers hold correct values No fix scheduled 116

Table 3. Summary of Silicon Errata (continued)

Errata Name Solution Page

Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016

NXP Semiconductors 9

ERR004323 HDMI: The DMA burst read transaction address region is limited to 8 KB No fix scheduled 117

ERR004366 HDMI: 9000482480—ARM core read operation returns incorrect data for certain

HDCP registers No fix scheduled 124

ERR005171 HDMI: HDMI Tx audio may have noise due to audio DMA FIFO overflow No fix scheduled 118

ERR005172 HDMI: Under certain circumstances, the HDCP may transmit incorrect Ainfo value,

causing a failure on the receiver side No fix scheduled 119

ERR005173 HDMI: Clarification on HDMI programming procedure to avoid FIFO overflow No fix scheduled 120

ERR005174 HDMI: HDMI AHB Audio DMA stream misalignment on system initialization No fix scheduled 122

I2C

ERR007805 I2C: When the I2C clock speed is configured for 400 kHz, the SCL low period violates

the I2C specification No fix scheduled 126

I/O

ERR004307 I/O: MIPI_HSI, USB_HSIC, and ENET I/O interfaces should not be configured to

Differential input mode No fix scheduled 126

IPU

ERR009623 IPU: IDMAC burst errors when crossing a 4k boundary using NI/PI 420/422 formats

[i.MX 6DualPlus/6QuadPlus Only] No fix scheduled 127

MIPI

ERR004310 MIPI: Glitch or unknown clock frequency on MIPI input clock may occur in case the

CCM source clock is modified No fix scheduled 128

ERR005190 MIPI: CSI2 Data lanes are activated before the HS clock from the CSI Tx side

(camera) starts No fix scheduled 129

ERR005191 MIPI: Corruption of short command packets with Word Count (WC) greater than

16’hFFEE, during video mode transmission by the MIPI Generic Interface No fix scheduled 130

ERR005192 MIPI: Reverse direction long packets with no payload incorrectly issue a CRC error

for MIPI DSI No fix scheduled 131

ERR005193 MIPI: The bits for setting the MIPI DSI video mode cannot be changed on the fly No fix scheduled 132

ERR005194 MIPI: On MIPI DSI, there is a possible corruption of the video packets caused by

overlapping of the current line over the next line, if the configuration is programmed

incorrectly when using the DPI interface

No fix scheduled 133

ERR005195 MIPI: Incorrect blanking packet may be sent by the MIPI DSI interface No fix scheduled 134

ERR005196 MIPI: Error Interrupt generated by the MIPI CSI interface for certain legal packet

types No fix scheduled 135

ERR005197 MIPI: Null and Blanking data packets activate ‘dvalid’ signal No fix scheduled 136

ERR009704 MIPI: CSI-2: CRC error produced in 4-lane configuration No fix scheduled 137

Table 3. Summary of Silicon Errata (continued)

Errata Name Solution Page

Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016

10 NXPSemiconductors

MLB

ERR004312 MLB: Multi frame per sub-buffer mode is not supported No fix scheduled 138

MMDC

ERR005778 MMDC: DDR Controller’smeasureunitmayreturn an incorrectvaluewhen operating

below 100 MHz No fix scheduled 139

ERR009596 MMDC: ARCR_GUARD bits of MMDC Core AXI Re-ordering Control register

(MMDC_MAARCR) doesn't behave as expected No fix scheduled 140

PCIe

ERR003747 PCIe: 9000436491—Reading the Segmented Buffer Depth Port Logic registers

returns all zeros No fix scheduled 141

ERR003748 PCIe: 9000427578—Root ports with address translation drop inbound requests,

without reporting an error No fix scheduled 142

ERR003749 PCIe: 9000426180—MSI Interrupt Controller Status Register bit not cleared after

being written by software No fix scheduled 143

ERR003751 PCIe: 9000413207—PME Requester ID overwritten when two PMEs are received

consecutively No fix scheduled 144

ERR003753 PCIe: 9000405932—AXI/AHB Bridge Slave does not return a response to an

outbound non-posted request No fix scheduled 145

ERR003754 PCIe: 9000403702—AHB/AXI Bridge Master responds with UR status instead of CA

status for inbound MRd requesting greater than CX_REMOTE_RD_REQ_SIZE No fix scheduled 146

ERR003755 PCIe: 9000402443—Uncorrectable Internal Error Severity register bit has incorrect

default value No fix scheduled 147

ERR003756 PCIe: 9000387484—LTSSM: Software-initiated transitions to Disabled, Hot Reset,

Configuration, or Loopback states sometimes take longer than expected No fix scheduled 148

ERR003757 PCIe: 9000448152—Internal Address Translation Unit (iATU): Inbound Vendor

Defined Message (VDM) ‘ID Match Mode’ is not functional No fix scheduled 149

ERR003758 PCIe: 9000441819—Upstream Port does not transition to Recovery after receiving

TS OSs during “ENTER_L2 negotiation” No fix scheduled 150

ERR003759 PCIe: 9000439510—Internal Address Translation Unit (iATU) can sometimes

overwrite Outbound (Tx) Vendor Messages and MSIs No fix scheduled 151

ERR003760 PCIe: 9000439175—Poisoned Atomic Op requests targeting RTRGT0 receive UR

response instead of CA response No fix scheduled 152

ERR004297 PCIe: 9000336356—Link configuration sometimes proceeds when incorrect TS

Ordered Sets are received No fix scheduled 153

ERR004298 PCIe: 9000471173—Bad DLLP error status checking is too strict No fix scheduled 154

ERR004299 PCIe: 9000493959—L1 ASPM incorrectly entered after link down event during L1

ASPM entry negotiation No fix scheduled 155

ERR004321 PCIe: 9000470913—Power Management Control: Core might enter L0s/L1 before

Retry buffer is empty No fix scheduled 156

Table 3. Summary of Silicon Errata (continued)

Errata Name Solution Page

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