MaxLinear XR77103-A1R0 User manual
XR77103-A1R0 Universal PMIC 3 Output Buck Regulator EVB User Manual Revision History
March 10, 2022 010-A1R0UMR00 ii
Revision History
Document No. Release Date Change Description
010-A1R0UMR00 March 10, 2022 Updated:
■"Quick Set Up - Factory Settings" section.
■"Simplified Block Diagram, XR77103-A1R0 EVB" figure.
■"Jumper J8 Pull Up Options for the PGOOD Pin" table.
■"XR77103EVB-A1R0 Schematic" figure.
■"XR77103EVB-A1R0 Bill of Materials" table.
Removed:
■"VOUT Programming" section.
1A 4/26/16 Initial release of document.
XR77103-A1R0 Universal PMIC 3 Output Buck Regulator EVB User Manual Table of Contents
March 10, 2022 010-A1R0UMR00 iii
Table of Contents
Introduction...........................................................................................................................................................................1
Quick EVB Set Up and Start Up....................................................................................................................................1
Factory Settings ...................................................................................................................................................1
Quick Start Up ......................................................................................................................................................1
Reference Documentation ...................................................................................................................................................3
Ordering Information............................................................................................................................................................3
Evaluation Board Overview .................................................................................................................................................4
I/O and Test Points ...............................................................................................................................................................4
System Set-Up ......................................................................................................................................................................5
Jumper J3......................................................................................................................................................................5
Jumper J8......................................................................................................................................................................5
Jumper J11....................................................................................................................................................................5
XR77103EVB-A1R0 Schematic............................................................................................................................................7
XR77103EVB-A1R0 PCB Layers..........................................................................................................................................8
XR77103EVB-A1R0 Bill of Materials .................................................................................................................................10
XR77103-A1R0 Universal PMIC 3 Output Buck Regulator EVB User Manual List of Figures
March 10, 2022 010-A1R0UMR00 iv
List of Figures
Figure 1: Connecting and Monitoring VIN and VOUT...............................................................................................................2
Figure 2: Top View of XR77103-A1R0, REV2.0.....................................................................................................................3
Figure 3: Simplified Block Diagram, XR77103-A1R0 EVB .....................................................................................................4
Figure 4: XR77103EVB-A1R0 Schematic ..............................................................................................................................7
Figure 5: Silkscreen Top.........................................................................................................................................................8
Figure 6: Assembly Top/Layer 1.............................................................................................................................................8
Figure 7: Layer 2 ....................................................................................................................................................................8
Figure 8: Layer 3 ....................................................................................................................................................................8
Figure 9: Assembly Bottom ....................................................................................................................................................9
XR77103-A1R0 Universal PMIC 3 Output Buck Regulator EVB User Manual List of Tables
March 10, 2022 010-A1R0UMR00 v
List of Tables
Table 1: Jumper Connections for VIN, VOUT and PGND ........................................................................................................1
Table 2: Evaluation Board Ordering Part Number..................................................................................................................3
Table 3: Test Points................................................................................................................................................................4
Table 4: Factory Settings........................................................................................................................................................5
Table 5: Jumper J3 Options for the EN Pin ............................................................................................................................5
Table 6: Jumper J8 Pull Up Options for the PGOOD Pin .......................................................................................................5
Table 7: Jumper J11 and Operation from a 5V Rail ...............................................................................................................6
Table 8: XR77103EVB-A1R0 Bill of Materials......................................................................................................................10
XR77103-A1R0 Universal PMIC 3 Output Buck Regulator EVB User Manual Introduction
March 10, 2022 010-A1R0UMR00 1
Introduction
The XR77103-A1R0 evaluation board provides a platform to evaluate the features and performance of the XR77103-A1R0
Universal PMIC 3 Output Buck Regulator. The XR77103-A1R0 output voltages are set via an external resistor divider down
to 0.8V with a 4.5V to 14V input voltage range, and it is packaged in a 4mm x 4mm TQFN.
Quick EVB Set Up and Start Up
Factory Settings
The evaluation board has been set up with the following
factory default configuration for quick set up and operation:
■VIN = 5.5V to 14V, optimized for a 12V input rail.
■Maximum IOUT per channel is 2A.
■1MHz Switching frequency.
■Two channels may be paralleled for output currents up
to 5A peak and 4A steady state (however additional
hardware modification is required for parallel
operation).
■Low power spectral density (PSM) mode operation
enabled.
Quick Start Up
To quickly see the regulator in operation:
1. Use the factory settings and default configuration. If
other settings or components are desired, apply them
before the next steps. For more information, see
“System Set-Up” on page 5 for more.
2. Connect a turned-off power supply that is within the
above VIN specification (from 5.5V to 14V, 12V typical)
to VIN+ and VIN- with short and thick leads. Use test
pins EXT. VIN (J39) and AGND (J7) to connect and
monitor VIN+ and VIN- respectively. See locations in
Figure 1 on page 2.
3. Initially set to 0A, connect electronic loads to each
desired channel that will be no more than the maximum
IOUT (2A) to VOUTx and PGNDx (where x = the
channel number) with short and thick leads. Use test
pins in Table 1 on page 1 to connect and monitor
VOUTx and PGNDx respectively. See locations in
Figure 1 on page 2. For all channels with the electronic
load connected, ensure that the respective VIN jumper
is installed per Table 1 on page 1.
4. Turn on the 12V power supply and check VOUT. The
EVB powers up and regulates the enabled outputs at
3.3V (Ch1), 1.8V (Ch2) and 2.5V (Ch3) (factory default
settings). PGOOD is asserted active high once
sequencing is done, outputs are in regulation, and
reset timer expires.
5. Set or vary the load (do not exceed the maximum IOUT)
and check VOUT and other desired performance levels
such as regulation and efficiency. For more information
about monitoring, see “I/O and Test Points” on page 4 .
1. Factory default: jumpers installed.
Table 1: Jumper Connections for VIN, VOUT and PGND
Channel VIN(1) VOUT PGND
1 J14 VOUT1, J31 PGND1, J35
2 J20 VOUT2, J33 PGND2, J36
3 J24 VOUT3, J1 PGND3, J4
XR77103-A1R0 Universal PMIC 3 Output Buck Regulator EVB User Manual Quick EVB Set Up and Start Up
March 10, 2022 010-A1R0UMR00 2
Figure 1: Connecting and Monitoring VIN and VOUT
VIN+
VIN-
PGND1
VOUT1
VOUT2
PGND2
PGND3
VOUT3
XR77103-A1R0 Universal PMIC 3 Output Buck Regulator EVB User Manual Reference Documentation
March 10, 2022 010-A1R0UMR00 3
Figure 2: Top View of XR77103-A1R0, REV2.0
Reference Documentation
For additional information, refer to the XR77103-A1R0 data
sheet, including a full list of IC features, pinout, pin
descriptions, typical performance characteristics, and
external component calculations.
This manual provides the EVB schematics (“XR77103EVB-
A1R0 Schematic” on page 7 ), the PCB layout
(“XR77103EVB-A1R0 PCB Layers” on page 8 ) and the bill
of materials (“XR77103EVB-A1R0 Bill of Materials” on
page 10 ) that you can use on your board design.
For more information about the schematics, go to
www.maxlinear.com/XR77103-A1R0.
Ordering Information
Note: For the most up-to-date information, go to www.maxlinear.com/XR77103-A1R0.
Table 2: Evaluation Board Ordering Part Number
Evaluation Board Board Description
XR77103EVB-A1R0 XR77103-A1R0 evaluation board.
XR77103-A1R0 Universal PMIC 3 Output Buck Regulator EVB User Manual Evaluation Board Overview
March 10, 2022 010-A1R0UMR00 4
Evaluation Board Overview
The XR77103-A1R0 EVB block diagram is shown in Figure 3.
Figure 3: Simplified Block Diagram, XR77103-A1R0 EVB
I/O and Test Points
VIN, LX and PGOOD Test Points
Test points are available for VIN (TP8), the LX switching nodes (TP6 for LX1, TP7 for LX2, and TP1 for LX3), the
compensation pins (TP4 for COMP1, TP5 for COMP2, TP3 for COMP3), and PGOOD (TP2) for monitoring.
The PGOOD output can be used externally. For more information about PGOOD options, see “Jumper J8” on page 5 .
Table 3: Test Points
Test Point Function
TP1 LX3
TP2 PGOOD
TP3 COMP3
TP4 COMP1
TP5 COMP2
TP6 LX1
TP7 LX7
TP8 VIN
XR77103-A1R0
VIN VOUT1
EN
PGOOD
VCC
VOUT2
VOUT3
VIN1
VIN2
VIN3
J3
J14
J20
J24 VCC
J8
VCC
J11
J15 (SYNC)
XR77103-A1R0 Universal PMIC 3 Output Buck Regulator EVB User Manual System Set-Up
March 10, 2022 010-A1R0UMR00 5
System Set-Up
Table 4 lists a summary of the jumpers and factory settings to configure the EVB for operation. For additional information,
refer to the XR77103-A1R0 data sheet.
Jumper J3
Jumper J8
Jumper J11
For operation from a 5V rail, it is required that the LDO
output is connected to VIN, which can be accomplished by
populating J11. This enhances the operation of the drivers
for VIN < 5V.
Important: Remove J11 for operation at higher VIN. The
board also has Zener diode placeholders which can be
installed to protect the IC if higher VIN is accidentally
applied.
Table 4: Factory Settings
Jumper Factory Setting Description
EN Pin
J3 Jumper 1-2 EN pin is tied to VCC and channels are enabled at power up.
PGOOD Pin
J8 Jumper 1-2 PGOOD is pulled up to VCC.
5V Operation
J11 No jumper LDO output is not tied to VIN.
VIN Connection to Individual Channels
J14, J20, J24 Jumpers installed VIN is connected to VIN1, VIN2, and VIN3.
SYNC Pin
J15 No jumper SYNC is not tied to GND on the board.
Table 5: Jumper J3 Options for the EN Pin
Jumper Options Description
Jumper 1-2 (default) The EN (enable) pin is tied to VCC and channels are enabled at power up.
Jumper 2-3 The EN (enable) pin is tied to GND, permanently disabling the channels.
No jumper The jumper is open, allowing EN to be controlled external to the board.
Table 6: Jumper J8 Pull Up Options for the PGOOD Pin
Jumper Options Description
Jumper 1-2 (default) PGOOD is pulled up to the VCC pin.
No jumper PGOOD is not pulled up by this jumper.
Table of contents
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