Marvell Integrated Controller 88F6281 User manual

Marvell. Moving Forward Faster

Doc. No. MV-S104859-U0, Rev. E

December 2, 2008, Preliminary

Document Classification: Proprietary Information

Cover

88F6281

Integrated Controller

Hardware Specifications

Document Conventions

Note: Provides related information or information of special importance.

Caution: Indicates potential damage to hardware or software, or loss of data.

Warning: Indicates a risk of personal injury.

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Doc Status: Preliminary Technical Publication: 0.xx

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88F6281

Hardware Specifications

Page 2 Document Classification: Proprietary Information December 2, 2008, Preliminary

88F6281

Integrated Controller

Hardware Specifications

December 2, 2008, Preliminary Document Classification: Proprietary Information Page 3

PRODUCT OVERVIEW

The Marvell®88F6281 is a high-performance, highly integrated controller. The 88F6281 is based on the Marvell

proprietary, ARMv5TE-compliant, high-speed Sheeva™CPU core. The CPU core integrates a 256 KB L2 cache.

Sheeva™ CPU Core

16 KB-I, 16 KB-D

Up to 1.5 GHz

AES/DES/

3DES SHA-1/MD5

Processor

Memory

Security Engine

Cache

256 KB

DDR

SDRAM

Controller

JTAG Interface PCI Express

SATA

USB 2.0

High Speed I/0

PCI Express x1

Dual SATA ports

USB 2.0 port

88F6281 Functional Block Diagram

External DDR

800 MHz

Misc

FXS / FXO

SPI, NAND, SDIO

Slow Bus

TDM

UART x2

GPIO, TWSI

Flash, SDIO

4 XOR/DMA channels

XOR Engine

Internal Bus

Gigabit Ethernet

IEEE 1588AVB support

MPEG2-TS

I2S / S/PDIF

Media Interfaces

MPEG TS

Audio

88F6281

Hardware Specifications

Page 4 Document Classification: Proprietary Information December 2, 2008, Preliminary

FEATURES

The 88F6281 includes:

•High-performance CPU core, running at up to

1.5 GHz, with integrated, four-way, set-associative

L1 16-KB I-cache/16-KB D-cache and unified,

256-KB, four-way, set-associative L2 cache

•High-bandwidth dual-port DDR2 memory interface

(16-bit DDR2 SDRAM @ up to 800 MHz data rate)

•PCI Express (x1) port with integrated PHY

•Two Gigabit Ethernet (10/100/1000 Mbps) MACs

•USB 2.0 port with integrated PHY

•Two SATA 2.0 ports with integrated 3 Gbps SATA II

PHY

•Security Cryptographic engine

•S/PDIF (Sony/Philips Digital Interconnect Format) /

I2S (Integrated Interchip Sound) Audio in/out

interface

•SD/SDIO/MMC interface

•TDM SLIC/SLAC Codec interface

•Two XOR engines, each containing two XOR/DMA

channels (a total of four XOR/DMA channels)

•MPEG Transport Stream (TS) interface

•SPI port with SPI flash boot support

•8-bit NAND flash interface with boot support

•Two 16550 compatible UART interfaces

•TWSI port

•50 multi-purpose pins

•Internal Real Time Clock (RTC)

•Interrupt controller

•Timers

•128-bit eFuse (one-time programmable memory)

Sheeva™CPU core

•Up to 1.5 GHz

•32-bit and 16-bit RISC architecture

•Compliant with v5TE architecture, as published in

the ARM Architect Reference Manual, Second

Edition

•Includes MMU to support virtual memory features

•256-KB, four-way, set-associative L2 unified cache

•16-KB, four-way, set-associative I-cache

•16-KB, four-way, set-associative D-cache

•64-bit internal data bus

•Branch Prediction Unit

•Supports JTAG/ARM ICE

•Supports both Big and Little Endian modes

DDR2 SDRAM controller

•16-bit interface

•Up to 400 MHz clock frequency (800 MHz data

rate)

•DDR SDRAM with a clock ratio of 1:N and 2:N

between the DDR SDRAM and the CPU core,

respectively

•SSTL 1.8V I/Os

•Auto calibration of I/Os output impedance

•Supports four DRAM chip selects

•Supports all DDR devices densities up to 2 Gb

•Supports up to 32 open pages (page per bank)

•Up to 2 GB total address space

•Supports on-board DDR designs (no DIMM

support)

•Supports 2T mode, to enable high-frequency

operation under heavy load configuration

•Supports DRAM bank interleaving

•Supports up to a 128-byte burst per single memory

access

PCI Express interface (x1)

•PCI Express Base 1.1 compatible

•Integrated low-power SERDES PHY, based on

proven Marvell®SERDES technology

•Serves as a Root Complex or an Endpoint port

•x1 link width

•2.5 Gbps data rate

•Lane polarity reversal support

•Maximum payload size of 128 bytes

•Single Virtual Channel (VC-0)

•Replay buffer support

•Extended PCI Express configuration space

•Advanced Error Reporting (AER) support

•Power management: L0s and software L1 support

•Interrupt emulation message support

•Error message support

PCI Express master specific features

•Single outstanding read transaction

•Maximum read request of up to 128 bytes

•Maximum write request of up to 128 bytes

•Up to four outstanding read transactions in

Endpoint mode

PCI Express target specific features

•Supports up to eight read request transactions

•Maximum read request size of 4 KB

•Maximum write request of 128 bytes

•Supports PCI Express access to all of the

controller’s internal registers

Two Integrated GbE (10/100/1000) MAC ports

•Supports 10/100/1000 Mbps

•Dedicated DMA for data movement between

memory and port

Features

December 2, 2008, Preliminary Document Classification: Proprietary Information Page 5

•Priority queuing on receive based on Destination

Address (DA), VLAN Tag, and IP TOS

•Layer 2/3/4 frame encapsulation detection

•TCP/IP checksum on receive and transmit

•Supports proprietary 200 Mbps Marvell MII (MMII)

interface

•Supports four modes:

-Port 0 RGMII, Port 1 RGMII

-Port 0 RGMII, Port 1 MII/MMII

-Port 0 MII/MMII, port 1 RGMII

-Port 0 GMII, Port 1 N/A

•DA filtering

Precise Timing Protocol (PTP)

•Supports precise time stamping for packets, as

defined in IEEE 1588 PTP v1 and v2 and IEEE

802.1AS draft standards

•Supports Flexible Time Application interface to

distribute PTP clock and time to other devices in

the system

•Optionally accepts an external clock input for time

stamping

Audio Video Bridging networks

•Supports IEEE 802.1Qav draft Audio Video

Bridging networks

•Supports time- and priority-aware egress pacing

algorithm to prevent bunching and bursting

effects—suitable for audio/video applications

•Supports Egress Jitter Pacer for AVB-Class A and

AVB-Class B traffic and strict priority for legacy

traffic queues

USB 2.0 port

•Serves as a peripheral or host

•USB 2.0 compliant

•Integrated USB 2.0 PHY

•Enhanced Host Controller Interface (EHCI)

compatible as a host

•As a host, supports direct connection to all

peripheral types (LS, FS, HS)

•As a peripheral, connects to all host types (HS, FS)

and hubs

•Up to four independent endpoints, supporting

control, interrupt, bulk, and isochronous data

transfers

•Dedicated DMA for data movement between

memory and port

Two Integrated Marvell 3 Gbps (Gen2i) SATA PHYs

•Compliant with SATA II Phase 1 specifications

-Supports SATA II Native Command Queuing

(NCQ), up to 128 outstanding commands per

port

-Fully supports first party DMA (FPDMA)

-Backwards compatible with SATA I devices

•Supports SATA II Phase 2 advanced features

-3 Gbps (Gen2i) SATA II speed

-Port Multiplier (PM)—Performs FIS-based

switching, as defined in SATA working group PM

definition

-Port Selector (PS)—Issues the protocol-based

Out-Of-Band (OOB) sequence for selecting the

active host port

•Supports device 48-bit addressing

•Supports ATA Tag Command Queuing

SATA II Host Controller

•Enhanced-DMA (EDMA) for the SATA ports

•Automatic command execution, without host

intervention

•Command queuing support, for up to 32

outstanding commands

•Separate SATA request/response queues

•64-bit addressing support for descriptors and data

buffers in system memory

•Read ahead

•Advanced interrupt coalescing

•Target mode operation—supports attaching two

88F6281 controllers through their Serial-ATA ports,

enabling data communication between the

88F6281 controllers

•Advanced drive diagnostics via the ATA SMART

command

Cryptographic engine

•Hardware implementation on encryption and

authentication engines, to boost packet processing

speed

•Dedicated DMA to feed the hardware engines with

data from the internal SRAM memory or from the

DDR memory

•Implements AES, DES, and 3DES encryption

algorithms

•Implements SHA1 and MD5 authentication

algorithms

S/PDIF / I2S Audio In/Out interface

•Either S/PDIF or I2S inputs can be active at one

time

•Both S/PDIF and I2S outputs can be

simultaneously active, transferring the same PCM

data

S/PDIF-specific features

•Compliant with 60958-1, 60958-3, and IEC61937

specifications

•Sample rates of 44.1/48/96 kHz

•16/20/24-bit depths

88F6281

Hardware Specifications

Page 6 Document Classification: Proprietary Information December 2, 2008, Preliminary

I2S-specific features

•Sample rates of 44.1/48/96 kHz

•I2S input and I2S output operate at the same

sample rate

•16/24-bit depths

•I2S in and I2S out support independent bit depths

(16 bit/24 bit)

•Supports plain I2S, right-justified and left-justified

formats

SD/SDIO/MMC host interface

•1-bit/4-bit SDmem, SDIO, and MMC cards

•Up to 50 MHz

•Hardware generate/check CRC, on all command

and data transactions on the card bus

TDM SLIC/SLAC Codec interface

•Generic interface to standard SLIC/SLAC codec

devices

•Compatible with standard PCM highway formats

•TDM protocol support for two channels, up to

128 time slots

•Dedicated SPI interface for codec management

•Integrated DMA to transfer voice data to/from

memory buffer

Two XOR engines and DMA

•Two XOR/DMA channels per XOR engine (for a

total of four XOR/DMA channels)

•Chaining via linked-lists of descriptors

•Moves data from source interface to destination

interface

•Supports increment or hold on both Source and

Destination Addresses

•Supports XOR operation, on up to eight source

blocks—useful for RAID applications

•Supports iSCSI CRC-32 calculation

NAND flash controller

•8-bit NAND flash interface

•Glueless interface to CE Care and CE Don’t Care

NAND flash devices

•Boot support

Serial Peripheral Interface (SPI) controller

•Up to 50 MHz clock

•Supports direct boot from external SPI serial flash

memory

MPEG Transport Stream (TS) interface

•ISO/IEC 13818-1 standard compliant

•Supports any one of the following modes:

-Parallel (8 bit) input

-Parallel output

-Two independent serial interfaces

•Data rate up to 80 Mbps

Two UART Interfaces

•16550 UART compatible

•Two pins for transmit and receive operations

•Two pins for modem control functions

Two-Wire Serial Interface (TWSI)

•General purpose TWSI master/slave port

•Can also be used for serial ROM initialization

50 dedicated Multi-Purpose Pins (MPPs) for

peripheral functions and general purpose I/O

•Each pin can be configured independently.

•GPIO inputs can be used to register interrupts from

external devices, and to generate maskable

interrupts.

•Only two of the following multiplexed interfaces

may be configured simultaneously:

-Audio

-TS

-TDM

-GbE Port 0 in GMII mode or GbE Port 1

Interrupt Controller

Maskable interrupts to CPU core

(and PCI Express for a PCI Express endpoint)

Two general purpose 32-bit timers/counters

Internal architecture

•Mbus-L bus for high-performance, low-latency CPU

core to DDR SDRAM connectivity

•Advanced Mbus architecture

•Dual port DDR SDRAM controller connectivity to

both CPU and Mbus

Bootable from

•SPI flash

•SATA device

•NAND flash

•PCI Express

•UART (for debug purpose)

288-pin HSBGA package, 19 x 19 mm, 1 mm ball

pitch

Features

December 2, 2008, Preliminary Document Classification: Proprietary Information Page 7

x16

TDM

Usage Model Example: VoIP Gateway

PCI Express

Mini Card Wi-Fi

SD Card

USB Host

SATA Port

Multiplier HDD

Audio

A/D – D/A GbE PHY FXS FXO

NAND Flash

SPI Flash (op.)

On Board DDR2

88F6281

Hardware Specifications

Page 8 Document Classification: Proprietary Information December 2, 2008, Preliminary

Table of Contents

Product Overview.......................................................................................................................................3

Features.......................................................................................................................................................4

Preface.......................................................................................................................................................15

About this Document.......................................................................................................................................15

Related Documentation...................................................................................................................................15

Document Conventions...................................................................................................................................16

1 Pin and Signal Descriptions.......................................................................................................17

1.1 Pin Logic .........................................................................................................................................................18

1.2 Pin Descriptions ..............................................................................................................................................19

1.3 Internal Pull-up and Pull-down Pins................................................................................................................48

2 Unused Interface Strapping........................................................................................................49

3 88F6281 Pin Map and Pin List ....................................................................................................50

4 Pin Multiplexing...........................................................................................................................51

4.1 Multi-Purpose Pins Functional Summary........................................................................................................51

4.2 Gigabit Ethernet (GbE) Pins Multiplexing on MPP..........................................................................................57

4.3 TSMP (TS Multiplexing Pins) on MPP.............................................................................................................59

5 Clocking .......................................................................................................................................60

5.1 Spread Spectrum Clock Generator (SSCG)....................................................................................................62

6 System Power Up/Down and Reset Settings............................................................................63

6.1 Power-Up/Down Sequence Requirements......................................................................................................63

6.2 Hardware Reset ..............................................................................................................................................64

6.3 PCI Express Reset..........................................................................................................................................66

6.4 Sheeva™CPU TAP Controller Reset..............................................................................................................66

6.5 Pins Sample Configuration..............................................................................................................................66

6.6 Serial ROM Initialization..................................................................................................................................70

6.7 Boot Sequence................................................................................................................................................71

7 JTAG Interface.............................................................................................................................73

7.1 TAP Controller.................................................................................................................................................73

7.2 Instruction Register .........................................................................................................................................73

7.3 Bypass Register..............................................................................................................................................74

7.4 JTAG Scan Chain ...........................................................................................................................................74

7.5 ID Register ......................................................................................................................................................74

Table of Contents

December 2, 2008, Preliminary Document Classification: Proprietary Information Page 9

8 Electrical Specifications (Preliminary) ......................................................................................75

8.1 Absolute Maximum Ratings ............................................................................................................................75

8.2 Recommended Operating Conditions.............................................................................................................77

8.3 Thermal Power Dissipation .............................................................................................................................79

8.4 Current Consumption......................................................................................................................................80

8.5 DC Electrical Specifications............................................................................................................................81

8.6 AC Electrical Specifications ............................................................................................................................86

8.7 Differential Interface Electrical Characteristics..............................................................................................118

9 Thermal Data (Preliminary).......................................................................................................129

10 Package......................................................................................................................................130

11 Part Order Numbering/Package Marking ................................................................................132

11.1 Part Order Numbering...................................................................................................................................132

11.2 Package Marking ..........................................................................................................................................133

A Revision History ........................................................................................................................134

88F6281

Hardware Specifications

Page 10 Document Classification: Proprietary Information December 2, 2008, Preliminary

List of Tables

1 Pin and Signal Descriptions ............................................................................................................17

Table 1: Pin Functions and Assignments Table Key ......................................................................................19

Table 2: Interface Pin Prefix Codes................................................................................................................19

Table 3: Power Pin Assignments....................................................................................................................21

Table 4: Miscellaneous Pin Assignments.......................................................................................................23

Table 5: DDR SDRAM Interface Pin Assignments .........................................................................................24

Table 6: PCI Express Interface Pin Assignments...........................................................................................26

Table 7: SATA Port Interface Pin Assignment................................................................................................27

Table 8: Gigabit Ethernet Port0/1 Interface Pin Assignments .......................................................................28

Table 9: Serial Management Interface (SMI) Pin Assignments......................................................................32

Table 10: USB 2.0 Interface Pin Assignments..................................................................................................33

Table 11: JTAG Pin Assignment.......................................................................................................................34

Table 12: RTC Interface Pin Assignments........................................................................................................35

Table 13: NAND Flash Interface Pin Assignment.............................................................................................36

Table 14: MPP Interface Pin Assignment.........................................................................................................37

Table 15: Two-Wire Serial Interface (TWSI) Interface Pin Assignment............................................................38

Table 16: UART Port 0/1 Interface Pin Assignment .........................................................................................39

Table 17: Audio (S/PDIF / I2S) Interface Signal Assignment............................................................................40

Table 18: Serial Peripheral Interface (SPI) Interface Signal Assignment .........................................................41

Table 19: Secure Digital Input/Output (SDIO) Interface Signal Assignment.....................................................42

Table 20: Time Division Multiplexing (TDM) Interface Signal Assignment .......................................................43

Table 21: Transport Stream (TS) Interface Signal Assignment........................................................................45

Table 22: Precise Timing Protocol (PTP) Interface Signal Assignment............................................................47

Table 23: Internal Pull-up and Pull-down Pins..................................................................................................48

2 Unused Interface Strapping.............................................................................................................49

Table 24: Unused Interface Strapping..............................................................................................................49

3 88F6281 Pin Map and Pin List .........................................................................................................50

4 Pin Multiplexing ................................................................................................................................51

Table 25: MPP Functionality.............................................................................................................................52

Table 26: MPP Function Summary...................................................................................................................53

Table 27: Ethernet Ports Pins Multiplexing.......................................................................................................57

Table 28: TS Port Pin Multiplexing .................................................................................................................59

5 Clocking.............................................................................................................................................60

Table 29: 88F6281Clocks.................................................................................................................................60

Table 30: Supported Clock Combinations........................................................................................................61

6 System Power Up/Down and Reset Settings .................................................................................63

Table 31: I/O and Core Voltages......................................................................................................................63

Table 32: Reset Configuration..........................................................................................................................67