HP 3000 III Series User manual

HP 3000SERIE5;:11I

COMPUJ"ER SYSTEM

';',.,:

.•.•

;

REFERENCE/T~AIN1N,G

MANUAL

Manual

P~rt,No.~30000-90143

Printed in U.S.A.

6179

HEWLETT·PACKARD

COMPANY

5303

STEVENS

CREEK

BLVD.,

SANTA

CLARA,

CALIFORNIA,

95060

NOTICE

The

information contained

this

document is subject to change

without

notice.

HEWLETT-PACKARD MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATER-

IAL, INCLUDING, BUT NOT LIMITED TO,

THE

IMPLIED WARRANTIES OF MERCHANTABILITY

AND FITNESS

FOR

APARTICULAR PURPOSE.

Hewlett-Packard

shall

not

be liable for

errors

contained

herein

or for incidental or consequential

damages

connection

with

the

furnishing, perfor-

mance

use

this

material.

This

document contains

proprietary

information which is protected by copyright. All

rights

are

reserved.

part

this

document

may

be photocopied or reproduced

without

the

prior

written

consent of

Hewlett-Packard

Company.

HEWLETT-PACKARD

COMPANY

LIST

EFFECTIVE

PAGES

The List

Effective

Pages

gives

the date

the current edition and

any pages changed in updates

that

edition. Within

the manual, any page changed since the last edition

indicated by printing the date the changes were made on the bottom

the page. Changes are marked with avertical bar in the margin.

an update

incorporated when an edition

reprinted,

th.ese

bars are removed but the dates remain. No information

incorporated into areprinting unless

appears

prior update.

All

pages in this manual are original issne.

iii

PRINTING

HISTORY

New

editions are complete revisions

the manual. Update packages, which are issued between editions, contain additional

and replacement pages to be merged into the manual by the customer. The date on the title page and back cover

the

manual changes only when anew edition

pUblished.

When

an edition

reprinted,

all

the prior updates

the edition

are incorporated.

information

incorporated into areprinting unless it appears

aprior update. The edition does

not change.

First Edition Jun 1979

PREFACE

This

manual

contains

hardware-oriented

reference

information

for

the

3000

Series

III

Computer

Systems.

Specifically,

this

man-

ual

contains

reference

reading

material

for

all

persons

that

are

attend

Hewlett-Packard's

3000

Series

III

Computer

System

Hard-

ware

Training

Courses.

Since

the

information

contained

this

manual

approximately

the

same

that

presented

during

class-

room

lectures,

this

manual

should

used

for

classroom

refer-

ence,

note

taking

purposes,

and

post

school

reference.

The

3000

Series

III

Computer

Systems

are

divided

into

two

pro-

duct

lines;

the

3242lA

Series

III

and

the

32435A

Series

III.

Unless

otherwise

stated,

the

content

this

manual

applies

equally

both

product

lines.

CONTENTS

SECTION I

Paragraph

INTRODUCTION

Page

SYSTEM FEATURES

•••••••••••••••

Stack

Architecture

••••••••

Microprogrammed

Operations

Data

Base

Management

Facilities

Five

Progrannning

Languages

Virtual

Memory .

Fault

Control

Memory

Concurrent

I/O

and

CPU

Operations

Reentrant

Code

and

Private

Data

Opera

ting

System

HARDWARE

FEATURES

SOFTWARE

FEATURES

SYSTEM CONFIGURATIONS

...

1-1

1-2

1-3

1-4

SECTION

Paragraph

SYSTEM/CPU OVERVIEW

Page

....

HARDWARE

ORGANIZATION

Bus

System

CTL BUS

lOP

BUS

SELECTOR

CHANNEL

BUS

PORT

CON'rROLLER BUS

MULTIPLEXER

CHANNEL

BUS

POWER

BUS

••.•••••••••••

Functional

Hardware

Elements

CENTRAL PROCESSOR

MODULE

MAIN

MEMORy

.....•.......

MULTIPLEXER

CHANNEL

••••••

PORT

CON'rROLLER/SELECTOR

CHANNEL

DEVICE CONTROLLERS

CTL

Bus

ior

OPERATING ENVIRONMENT

Virtual

Memory

Variable-Length

Segmentation

Processes

Data

Stacks

CPU

Registers

CODE

SEGMENT

REGISTERS

DATA

SEGl-1ENT

REG! STERS

Basic

Table

Structures

CODE

SEGMENT

TABLE

AND

CODE

SEGMEN'I'

EXTENSION

2-1

2-2

2-3

2-4

2-5

2-6

2-7

2-8

2-9

2-11

2-12

2-13

2-15

CONTENTS

(continued)

SECTION

(CaNT)

Paragraph

Page

..........

·........

2-16

2-22

2-27

2-28

2-30

2-31

2-32

2-34

2-35

2-36

2-38

2-40

2-41

2-42

2-43

2-45

2--45

2-45

2-46

2-49

2-50

...

....

.....

...

....

.....

.......

·....

·.......

.....

........

.....

...

.....

...

..........

.......

.....

...

.....

.........

DA'rA

SEGHENT

TABLE

Code

Segment

Linkage

Stack

Operation

••••••

INSTRUCTION

AND

STAlJ:IUS

WORD

FORMATS

•••••

Instruction

Formats

••••••••••••

GENERAL

FORttJA'Il

STACK

•••••••

SHIFT

BRANCH

BIT

'I1EST

MOVE

•••••

SPECIAL

IMMEDIATE

FIELD

CONTROL

PROGRAM

CON'I'ROL

I/O

AND

INTERRUPT

LOOP

CONTROL

MEMORY

ADDRESS

Status

Word

Format

Condi

tion

Codes

OPERATING

MODES

ADDRESSING

CONVENTIONS

Memory

Addressing

Indirect

Addressing

CODE

INDIRECT

DATA

INDIRECT

Indexing

••••••••

CODE

INDEXING

DATA

INDEXING

•••••

Byte

Addres

sing

••••••

DIRECT

BYTE

ADDRESSING

DIRECT,

INDEXED

BYTE

ADDRESSING

INDIRECT

BYTE

ADDRESSING

•••••••

INDIRECT,

INDEXED

BYTE

ADDRESSING

Double-Word

Indexing

Accessing

DB-

Area

WORD

ADDRESSING

BYTE

ADDRESSING

••••••

Bounds

Checking

•••••••••

PROGRAM

TRANSFER

LIMIT

PROGRAM

REFERENCE

LIMITS

••••

DATA

REFERENCE

LIMITS

STACK

OVERFLOW

LIMIT

•••

STACK

UNDERFLOW

LIMIT

CPU

OVERVIEW

Pipel

ines

DATA

PIP

IN E

MICROCODE

PIPELINE

CPU

Component

Descriptions

N I R

••••••••••••••••••••

vii

CONTENTS

(continued)

SECTION

(CONT)

.................................................

2-50

2-51

2-52

2-53

2-54

2-55

2-56

2-57

2-58

2-59

2-60

2-61

Page

....

· .

·...........

·.....

......

..............

.................

.........

....................

.....,....

...

.....

...

CIR

CMUX

AND

Cr.1UX

CON'rROL

MAPPER

AND

MAPPER

CONTROL

LUT

ROM

••••••••••••••••••

VBUS

MUX

AND

VBUS

CONTROL

.RA.R

••••••••••••••••••

SAVE

ROM

••••••••••

RORI

AND

ROR2

••••••••••

Microcode

Jumps

S-Bus

Fie

Decoder

(S)

Store

Field

Decoder

(STORE)

Function

Field

Decoder

(FCN)

Skip

Field

Decoder

(SKIP)

••••••••

Shift

Field

Decoder

(SHIFT)

•••••

Special

Field

Decoder

(SP)

MCU

Option

Field

Decoder

(MeU)

R-Bus

Field

Decoder

(R)

PROCESSOR

REGISTERS

Renamer

Logic

•••••••

gis

r s

•••••••

Index

Reg

iste

(X)

••

Stack

Limit

(Z)

Program

Limit

(PL)

Scratch

Pad

(SPO)

Scratch

Pad

(SPl)

c k

g i s

r (S

Program

Base

(PB)

Data

Limit

(DL)

Stac

kMemory

(8M)

Data

Base

(DB)

gis

r (Q )

Scratch

Pad

(SP2)

Scratch

Pad 3

(SP3)

•••••

Proces

Clock

Regi

ste

(PCLOC

Program

Cbunter

(P)

•••••••••••••••••

Operand

(OPND)

Status

(STA)

Counte

rReg

iste

(CNTR)

OVERFLOW

FLIP-FLOP

(OVFL)

CARRY

FLIP-FLOP

(CRRY)

CONDITION

CODE

LOGIC

(CCO

AND

CCl)

••••

PRE-ADDER

•••••

R-BUS

••••

S-BUS REGISTER

••••

ALU

•••••••••••

SHIFTER

••••••••••••••••

MAL

CORRE

CTOR

•••••••••••••••••••••

ADDRESS

COMPUTER

OUTPUT

(ACOR)

DATA

COMPUTER

OUTPUT

(DCOR)

••

INTERRUPT

STATUS

••••••••••••••

Paragraph

viii

CONTENTS

(continued)

SECTION

(CONT)

Paragraph

Page

..............

INTERRUPT STATUS REGIS'I'ER 2(CPX2)

••••••••••••••••••

CPU

Servicing

Information

••••••••••••

READ-ONLY

MEMORY

(ROM)

PCA

••••••••

SKIP

AND

SPECIAL

FIELD

(SSF)

PCA

S-BUS

PCA

••••••••••••••••••••••••••

CURRENT

INSTRUCTION REGISTER

(CIR)

PCA

••••••••••••••

2-61

2-62

2-63

2-64

SECTION

III

SYSTEM

VERIFICATION

AND

TROUBLESHOOTING

Paragraph

Page

. .

......................................

......

..............................

............................................

3-1

3-2

3-4

3-6

3-23

3-24

3-25

3-26

3-28

DIAGNOSTIC

AND

VERIFICATION

PROGRAMS

••••.•••••••••••••••••

On-Line

Verification

Programs

••••••••••••••••••••••••

Stand-Alone

Diagnostic

Programs

••••••••••••••••••••••

Microdiagnostics

•••••••••••••••••••••••••••••••••••••

SLEu'rH

3000

SYSTEM

TROUBLESHOOTING

AND

REPAIR

•••••••••••••••••••••••••

SYSTEM

CONTROL

Ph~EL

MAINTENANCE

PANEL

Switch/Lamp

Identification

and

Description

••••••••••

era

t i

Pre

uti

••••••••••••••••••••••••••••••••••

Preparation

For

Use

••••••••••••••••••••••••••••••••

General

Operating

Method

•••••••••••••••••••••••••••

Using

Maintenance

Panel

and

System

Gbntrol

Panel

Stack

•••••••••••••••••••••••••••••

CPU

Displays

••••••••••••••••••••••••••••••••••

General-Use

splay

intenance

Panel

Tes

•••••••••••••••••••••••••••••••••

LAMP

TEST

•••••••••••••••••••••••••••

ITCH TEST

•••••••••••••••••••••••••

SECTION IV -

MACHINE

INSTRUCTIONS

AND

STACK

OPERATIONS

Paragr

aph

Page

...................................

......................................

....................

...................

............................................

4-1

4-3

4-10

4-11

4-12

4-13

4-14

4-15

4-17

......................................

INSTRU CTION DECODING

TRAPS

AND

INTERRUPTS

CONDITION

CODE

INSTIU CTION

FORMATS

INSTRU CTION

DEF

INITIONS

Stack

Instructions

••••••••••••••••••••••••••••••••••

Shift

Instructions

•••••••••••••••••••••••••••••••••••••

Branch

Instr

uctions

••••••••••••••••••••••••••••••••••••

lvbve

Instructions

••••••••••••••••••••••••••••••••••••••

Privileged

Memory

Reference

Instructions

•••••••••••••••

Immed

uct

ions

•••••••••••••••••••••••••••••••••

Control

Instructions

••••••••••••••••••••••••••

Program

Control

and

Special

Instructions

•••••••••••••••

I/O

Instructions

•••••••••••••••••••••••••••••••••••••••

CONTENTS

(continued)

SECTION IV (CONT)

Paragraph

Memory

Address

Instructions

Instruction

Commentary

STACK

OPERATION

EXAMPLES

Basic

ithme

tic

Procedure

Calls

cur

ion

••••••

MAIN

PROGRAM

CALL

TEST

FOR

ZERO

FIRST

RECURSIVE

CALL

SUCCESSIVE RECURSIONS

FIRST

EXIT

•••••••••••

FIRST

RECURSIVE EXIT

•••

SUCCESSIVE EXITS

•••••

........

..............

...

....

...

Page

4-19

4-21

4-37

4-39

4-43

4-46

4-48

SECTION V

SYSTEM

MICROCODE

....

Page

5-1

5-2

5-3

5-4

5-5

...

....

· .

·....

·.....

.......

...

.....

...

GENERAL

INFORMATION

•••••••

Stack

Element

Locations

PUSH

•••

POP

QUP

QDWN

Reading

Microprogram

Listings

CROINSTRU CTION DESCRIPTIONS

R-Bus

Field

S-Bus

Field

Function

Fie

Shift

Field

Store

Field

Special

Fie

MCU

Option

Field

••

Skip

Field

MICRODIAGNOSTICS

Paragr

aph

SECTION

MODULE

CON'rROL

UNIT/MAIN

MEMORY

OVERVIEW

Paragraph

Page

.........................

MCU

OPERATIONS

Fetch

Instruction

Operations

CPU

ADDRESS

TRANSMIT

••••••••

MEMORY

RECEIVE

AND

TRANSMIT

CPU

RECEIVE

•••••••••••••

Fetch

Operand

Operations

CPU

ADDRESS

TRANSMIT

MEMORY

RECEIVE

AND

TRANSMIT

CPU

RECE

IVE

•••••••••••••••••

.....

6-1

6-3

6-5

Table of contents

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