Cypress Semiconductor CY7C1018DV33 User manual

1-Mbit (128K x 8) Static RAM

CY7C1018DV33

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document #: 38-05465 Rev. *D Revised November 8, 2006

Features

• Pin- and function-compatible with CY7C1018CV33

• High speed

—t

AA = 10 ns

• Low Active Power

—I

CC = 60 mA @ 10 ns

• Low CMOS Standby Power

—I

SB2 = 3 mA

• 2.0V Data retention

• Automatic power-down when deselected

• CMOS for optimum speed/power

• Center power/ground pinout

• Easy memory expansion with CE and OE options

• Available in Pb-free 32-pin 300-Mil wide Molded SOJ

Functional Description[1]

The CY7C1018DV33 is a high-performance CMOS static

RAM organized as 131,072 words by 8 bits. Easy memory

expansion is provided by an active LOW Chip Enable (CE), an

active LOW Output Enable (OE), and tri-state drivers. This

device has an automatic power-down feature that significantly

reduces power consumption when deselected.

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O

pins (I/O0through I/O7) is then written into the location

specified on the address pins (A0through A16).

Reading from the device is accomplished by taking Chip

Enable (CE) and Output Enable (OE) LOW while forcing Write

Enable (WE) HIGH. Under these conditions, the contents of

the memory location specified by the address pins will appear

on the I/O pins.

The eight input/output pins (I/O0through I/O7) are placed in a

high-impedance state when the device is deselected (CE

HIGH), the outputs are disabled (OE HIGH), or during a write

operation (CE LOW, and WE LOW).

The CY7C1018DV33 is available in Pb-free 32-pin 300-Mil

wide Molded SOJ.

Logic Block Diagram

COLUMN

DECODER

ROW DECODER

SENSE AMPS

INPUTBUFFER

POWER

DOWN

I/O0

I/O1

I/O2

I/O3

I/O7

I/O6

I/O5

I/O4

A13

A11

A12

A10

128K × 8

ARRAY

A14

A15

A16

14 19

Top View

SOJ

15 17

I/O

Pin Configuration

Note

1. For guidelines on SRAMsystem designs, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.

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CY7C1018DV33

Document #: 38-05465 Rev. *D Page 2 of 9

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage on VCC to Relative GND[2] ...–0.3V to + 4.6V

DC Voltage Applied to Outputs[2]

in High-Z State.......................................–0.3V to VCC + 0.3V

DC Input Voltage[2] ................................–0.3V to VCC + 0.3V

Current into Outputs (LOW).........................................20 mA

Static Discharge Voltage...........................................> 2001V

(per MIL-STD-883, Method 3015)

Latch-up Current.....................................................> 200 mA

Selection Guide

–10 (Industrial) Unit

Maximum Access Time 10 ns

Maximum Operating Current 60 mA

Maximum Standby Current 3 mA

Operating Range

Range Ambient

Temperature VCC Speed

Industrial –40°C to +85°C 3.3V ±0.3V 10 ns

DC Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions –10 (Industrial) Unit

Min. Max.

VOH Output HIGH Voltage VCC = Min.,

IOH = –4.0 mA 2.4 V

VOL Output LOW Voltage VCC = Min.,

IOL = 8.0 mA 0.4 V

VIH Input HIGH Voltage 2.0 VCC + 0.3 V

VIL Input LOW Voltage[2] –0.3 0.8 V

IIX Input Leakage Current GND < VI< VCC –1 +1 µA

IOZ Output Leakage Current GND < VI <VCC, Output Disabled –1 +1 µA

ICC VCC Operating Supply Current VCC = Max.,

IOUT = 0 mA,

f = fMAX = 1/tRC

100MHz 60 mA

83MHz 55 mA

66MHz 45 mA

40MHz 30 mA

ISB1 Automatic CE Power-down

Current—TTL Inputs Max. VCC, CE > VIH

VIN > VIH or VIN < VIL, f = fMAX 10 mA

ISB2 Automatic CE Power-down

Current—CMOS Inputs Max. VCC, CE > VCC – 0.3V,

VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 3mA

Note

2. VIL (min.) = –2.0V and VIH(max) = VCC + 1V for pulse durations of less than 5 ns.

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CY7C1018DV33

Document #: 38-05465 Rev. *D Page 3 of 9

Capacitance[3]

Parameter Description Test Conditions Max. Unit

CIN Input Capacitance TA= 25°C, f = 1 MHz, VCC = 3.3V 8 pF

COUT Output Capacitance 8 pF

Thermal Resistance[3]

Parameter Description Test Conditions 400-Mil

Wide SOJ Unit

ΘJA Thermal Resistance

(Junction to Ambient) Still Air, soldered on a 3 × 4.5 inch,

four-layer printed circuit board 57.61 °C/W

ΘJC Thermal Resistance

(Junction to Case) 40.53 °C/W

AC Test Loads and Waveforms[4]

90%

10%

3.0V

GND

90%

10%

ALL INPUT PULSES

* CAPACITIVE LOAD CONSISTS

OF ALL COMPONENTS OF THE

TEST ENVIRONMENT Rise Time: 1 V/ns Fall Time: 1 V/ns

30 pF*

OUTPUT

Z = 50

Ω

50Ω

1.5V (b)

(a)

3.3V

OUTPUT

5 pF

(c)

R 317Ω

351Ω

High-Z characteristics:

Notes

3. Tested initially and after any design or process changes that may affect these parameters.

4. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load

shown in Figure (c).

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CY7C1018DV33

Document #: 38-05465 Rev. *D Page 4 of 9

AC Switching CharacteristicsOver the Operating Range [5]

Parameter Description –10 (Industrial) Unit

Min. Max.

Read Cycle

tpower[6] VCC(typical) to the first access 100 µs

tRC Read Cycle Time 10 ns

tAA Address to Data Valid 10 ns

tOHA Data Hold from Address Change 3 ns

tACE CE LOW to Data Valid 10 ns

tDOE OE LOW to Data Valid 5 ns

tLZOE OE LOW to Low-Z 0 ns

tHZOE OE HIGH to High-Z[7, 8] 5ns

tLZCE CE LOW to Low-Z[8] 3ns

tHZCE CE HIGH to High-Z[7, 8] 5ns

tPU[9] CE LOW to Power-up 0 ns

tPD[9] CE HIGH to Power-down 10 ns

Write Cycle[10, 11]

tWC Write Cycle Time 10 ns

tSCE CE LOW to Write End 8 ns

tAW Address Set-up to Write End 8 ns

tHA Address Hold from Write End 0 ns

tSA Address Set-up to Write Start 0 ns

tPWE WE Pulse Width 7 ns

tSD Data Set-up to Write End 5 ns

tHD Data Hold from Write End 0 ns

tLZWE WE HIGH to Low-Z[8] 3ns

tHZWE WE LOW to High-Z[7, 8] 5ns

Notes

5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.

6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.

7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (c) of AC Test Loads. Transition is measured when the outputs enter a high impedance state.

8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.

9. This parameter is guaranteed by design and is not tested.

10.The internal Write time of the memory is defined by the overlap of CELOW and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of any of these

signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.

11. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.

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CY7C1018DV33

Document #: 38-05465 Rev. *D Page 5 of 9

Data Retention Characteristics (Over the Operating Range)

Parameter Description Conditions Min. Max. Unit

VDR VCC for Data Retention 2 V

ICCDR Data Retention Current VCC = VDR = 2.0V, CE > VCC – 0.3V,

VIN > VCC – 0.3V or VIN < 0.3V 3mA

tCDR [3] Chip Deselect to Data Retention Time 0 ns

tR[12] Operation Recovery Time tRC ns

Data Retention Waveform

Switching Waveforms

Read Cycle No. 1 (Address Transition Controlled)[13, 14]

Read Cycle No. 2 (OE Controlled)[14, 15]

3.0V3.0V

tCDR

VDR > 2V

DATA RETENTION MODE

VCC

PREVIOUS DATA VALID DATA VALID

tAA

tOHA

tRC

ADDRESS

DATA OUT

50%

DATA VALID

tRC

tACE

tDOE

tLZOE

tLZCE

tPU

HIGH IMPEDANCE

tHZOE tHZCE

tPD

HIGH

ICC

ISB

IMPEDANCE

ADDRESS

DATA OUT

VCC

SUPPLY

CURRENT

Notes

12.Full device operation requires linear VCC ramp from VDR to VCC(min.) >50 µs or stable at VCC(min.) >50 µs.

13.Device is continuously selected. OE, CE = VIL.

14.WE is HIGH for Read cycle.

15.Address valid prior to or coincident with CEtransition LOW.

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CY7C1018DV33

Document #: 38-05465 Rev. *D Page 6 of 9

Write Cycle No. 1 (CE Controlled)[16, 17]

Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[16, 17]

Switching Waveforms (continued)

tWC

DATA VALID

tAW

tSA

tPWE

tHA

tHD

tSD

tSCE

DATA I/O

ADDRESS

tHD

tSD

tPWE

tSA

tHA

tAW

tSCE

tWC

tHZOE

DATAIN VALID

NOTE 18

ADDRESS

DATA I/O

Notes

16.Data I/O is high impedance if OE= VIH.

17.If CEgoes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.

18.During this period the I/Os are in the output state and input signals should not be applied.

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CY7C1018DV33

Document #: 38-05465 Rev. *D Page 7 of 9

Write Cycle No. 3 (WE Controlled, OE LOW)[11, 17]

Truth Table

CE OE WE I/O0–I/O7Mode Power

H X X High-Z Power-down Standby (ISB)

L L H Data Out Read Active (ICC)

L X L Data In Write Active (ICC)

L H H High-Z Selected, Outputs Disabled Active (ICC)

Ordering Information

Speed

(ns) Ordering Code Package

Diagram Package Type Operating

Range

10 CY7C1018DV33-10VXI 51-85041 32-pin (300-Mil) Molded SOJ (Pb-free) Industrial

Please contact your local Cypress sales representative for availability of these parts.

Switching Waveforms (continued)

DATA VALID

tHD

tSD

tLZWE

tPWE

tSA

tHA

tAW

tSCE

tWC

tHZWE

NOTE 18

ADDRESS

DATA I/O

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CY7C1018DV33

Document #: 38-05465 Rev. *D Page 8 of 9

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Package Diagram

Figure 1. 32-pin (300-Mil) Molded SOJ (51-85041)

All product and company names mentioned in this document are the trademarks of their respective holders.

PIN 1 I.D

0.330

0.292 0.340

0.305

0.128

0.140

0.810

0.830

0.260

0.275

0.026

0.014

0.032

0.020

DIMENSIONS IN INCHES MIN.

MAX.

0.025

0.006

0.012

0.050

TYP.

MIN.

LEAD COPLANARITY 0.004 MAX.

51-85041-*A

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CY7C1018DV33

Document #: 38-05465 Rev. *D Page 9 of 9

Document History Page

Document Title: CY7C1018DV33, 1-Mbit (128K x 8) Static RAM

Document Number: 38-05465

REV. ECN NO. Issue Date Orig. of

Change Description of Change

** 201560 See ECN SWI Advance Information data sheet for C9 IPP

*A 238471 See ECN RKF DC parameters modified as per EROS (Spec # 01-02165)

Pb-free Offering in the Ordering Information

*B 262950 See ECN RKF Added Data Retention Characteristics table

Added Tpower Spec in Switching Characteristics table

Shaded Ordering Information

*C 307598 See ECN RKF Reduced Speed bins to -8 and -10 ns

*D 520647 See ECN VKN Converted from Preliminary to Final

Removed Commercial Operating range

Removed 8 ns speed bin

Added ICC values for the frequencies 83MHz, 66MHz and 40MHz

Updated Thermal Resistance table

Updated Ordering Information Table

Changed Overshoot spec from VCC+2V to VCC+1V in footnote #2

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