Cypress Semiconductor Perform CY62136EV30 User manual

2-Mbit (128K x 16) Static RAM

CY62136EV30

MoBL®

Cypress Semiconductor Corporation • 198ChampionCourt • San Jose,CA 95134-1709 • 408-943-2600

Document #: 38-05569 Rev. *B Revised January 6, 2006

Features

• Very high speed: 45 ns

• Wide voltage range: 2.20V–3.60V

• Pin-compatible with CY62136CV30

• Ultra low standby power

— Typical standby current: 1µA

— Maximum standby current: 7µA

• Ultra-low active power

— Typical active current: 2 mA @ f = 1 MHz

• Easy memory expansion with CE, and OE features

• Automatic power-down when deselected

• CMOS for optimum speed/power

• Offered in a Pb-free 48-ball VFBGA and 44-pin TSOP II

packages

Functional Description[1]

The CY62136EV30 is a high-performance CMOS static RAM

organized as 128K words by 16 bits. This device features

advanced circuit design to provide ultra-low active current.

This is ideal for providing More Battery Life™ (MoBL®) in

portable applications such as cellular telephones. The device

also has an automatic power-down feature that significantly

reduces power consumption by 80% when addresses are not

toggling. The device can also be put into standby mode

reducing power consumption by more than 99% when

deselected (CE HIGH). The input/output pins (I/O0through

I/O15) are placed in a high-impedance state when: deselected

(CE HIGH), outputs are disabled (OE HIGH), both Byte High

Enable and Byte Low Enable are disabled (BHE, BLE HIGH),

or during a write operation (CE LOW and WE LOW).

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable

(BLE) is LOW, then data from I/O pins (I/O0through I/O7), is

written into the location specified on the address pins (A0

through A16). If Byte High Enable (BHE) is LOW, then data

from I/O pins (I/O8through I/O15) is written into the location

specified on the address pins (A0through A16).

Reading from the device is accomplished by taking Chip

Enable (CE) and Output Enable (OE) LOW while forcing the

Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,

then data from the memory location specified by the address

pins will appear on I/O0to I/O7. If Byte High Enable (BHE) is

LOW, then data from memory will appear on I/O8to I/O15. See

the truth table at the back of this data sheet for a complete

description of read and write modes.

Note:

1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Logic Block Diagram

128K x 16

RAM Array I/O0–I/O7

ROW DECODER

COLUMN DECODER

A11

A12

A13

A14

A15

SENSE AMPS

DATA IN DRIVERS

A3I/O8–I/O15

BLE

BHE

A16

A10

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CY62136EV30

MoBL®

Document #: 38-05569 Rev. *B Page 2 of 12

Notes:

2. NC pins are not connected on the die.

3. Pins D3, H1, G2, and H6 in the BGA package are address expansion pins for 4 Mbit, 8 Mbit, 16 Mbit and 32 Mbit, respectively.

4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA= 25°C.

Pin Configuration[2, 3]

VFBGA (Top View) 44 TSOP II (Top View)

Product Portfolio[4]

Product VCC Range (V) Speed

(ns)

Power Dissipation

Operating ICC (mA)

Standby ISB2 (µA)f = 1MHz f = fmax

Min. Typ.[4] Max. Typ.[4] Max. Typ.[4] Max. Typ.[4] Max.

CY62136EV30LL 2.2 3.0 3.6 45 2 2.5 15 20 1 7

A11

A10

A3CE

I/O10

I/O8

I/O9

I/O11

I/O13

I/O12

I/O14

I/O15

VSS

Vss

I/O0

BHE

BLE

VCC

I/O2

I/O1

I/O3

I/O4

I/O5I/O6

I/O7

A15

A14

A13

A12

NC NC

A16

Vcc

14 31

15 29

VCC

A15

A14

A13

VSS

I/O15

I/O2

I/O0

I/O1

BHE

I/O3

21 23

VSS

I/O6

I/O4

I/O5

I/O7

BLE

VCC

I/O14

I/O13

I/O12

I/O11

I/O10

I/O9

I/O8

A10

A11

A12 NC

A16

[+] Feedback

CY62136EV30

MoBL®

Document #: 38-05569 Rev. *B Page 3 of 12

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature ................................–65°C to + 150°C

Ambient Temperature with

Power Applied ...........................................–55°C to + 125°C

Supply Voltage to Ground

Potential ..............................–0.3V to 3.9V (VCC MAX + 0.3V)

DC Voltage Applied to Outputs

in High-Z State[5,6]................–0.3V to 3.9V (VCC MAX + 0.3V)

DC Input Voltage[5,6]............ –0.3V to 3.9V (VCC MAX + 0.3V)

Output Current into Outputs (LOW) ............................20 mA

Static Discharge Voltage ......................................... > 2001V

(per MIL-STD-883, Method 3015)

Latch-up Current ....................................................> 200 mA

Operating Range[7]

Device Range Ambient

Temperature VCC[7]

CY62136EV30LL Industrial –40°Cto+85°C 2.2V - 3.6V

Electrical Characteristics Over the Operating Range [5, 6, 7]

Parameter Description Test Conditions

45 ns

UnitMin. Typ.[4] Max.

VOH Output HIGH

Voltage IOH = –0.1 mA VCC = 2.20V 2.0 V

IOH = –1.0 mA VCC = 2.70V 2.4 V

VOL Output LOW

Voltage IOL = 0.1 mA VCC = 2.20V 0.4 V

IOL = 2.1mA VCC = 2.70V 0.4 V

VIH Input HIGH Voltage VCC = 2.2V to 2.7V 1.8 VCC + 0.3 V

VCC= 2.7V to 3.6V 2.2 VCC + 0.3 V

VIL Input LOW Voltage VCC = 2.2V to 2.7V –0.3 0.6 V

VCC= 2.7V to 3.6V –0.3 0.8 V

IIX Input Leakage

Current GND < VI< VCC –1 +1 µA

IOZ Output Leakage

Current GND < VO <VCC, Output Disabled –1 +1 µA

ICC VCC Operating

Supply Current f = fMAX = 1/tRC VCC = VCCmax, IOUT = 0 mA

CMOS levels 15 20 mA

f = 1 MHz 2 2.5

ISB1 Automatic CE

Power-down

Current — CMOS

Inputs

CE > VCC−0.2V,

VIN>VCC–0.2V, VIN<0.2V)

f = fMAX (Address and Data Only),

f = 0 (OE, and WE),

VCC = 3.60V

17µA

ISB2 Automatic CE

Power-down

Current — CMOS

Inputs

CE > VCC – 0.2V,

VIN > VCC – 0.2V or VIN < 0.2V, f = 0,

VCC = 3.60V

17µA

Capacitance (for all packages)[8]

Parameter Description Test Conditions Max. Unit

CIN Input Capacitance TA= 25°C, f = 1 MHz,

VCC = VCC(typ) 10 pF

COUT Output Capacitance 10 pF

Notes:

5. VIL(min.) = –2.0V for pulse durations less than 20 ns.

6. VIH(max)=VCC+0.75V for pulse durations less than 20ns.

7. Full Device AC operation assumes a 100 µs ramp time from 0 to Vcc(min) and 200 µs wait time after VCC stabilization.

8. Tested initially and after any design or process changes that may affect these parameters.

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CY62136EV30

MoBL®

Document #: 38-05569 Rev. *B Page 4 of 12

Thermal Resistance[8]

Parameter Description Test Conditions VFBGA

Package TSOP II

Package Unit

ΘJA Thermal Resistance

(Junction to Ambient)[8] Still Air, soldered on a 3 × 4.5 inch, two-layer

printed circuit board 75 77 °C/W

ΘJC Thermal Resistance

(Junction to Case)[8] 10 13 °C/W

AC Test Loads and Waveforms

Parameters 2.50V 3.0V Unit

R1 16667 1103 Ω

R2 15385 1554 Ω

RTH 8000 645 Ω

VTH 1.20 1.75 V

Data Retention Characteristics (Over the Operating Range)[8, 9]

Parameter Description Conditions Min. Typ.[4] Max. Unit

VDR VCC for Data Retention 1.0 V

ICCDR Data Retention Current VCC= 1.0V

CE > VCC – 0.2V,

VIN > VCC – 0.2V or VIN < 0.2V

0.8 3 µA

tCDR[8] Chip Deselect to Data

Retention Time 0ns

tR[9] Operation Recovery

Time tRC ns

VCC

OUTPUT

30 pF

INCLUDING

JIG AND

SCOPE

GND 90%

10% 90%

10%

Rise Time = 1 V/ns Fall Time = 1 V/ns

OUTPUT VTH

Equivalent to: THÉVENIN EQUIVALENT

ALL INPUT PULSES

RTH

Data Retention Waveform

Notes:

9. Full device operation requires linear VCC ramp from VDR to VCC(min.) >100 µs or stable at VCC(min.) >100 µs.

VCC(min)

tCDR

VDR >1.0 V

DATA RETENTION MODE

VCC

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CY62136EV30

MoBL®

Document #: 38-05569 Rev. *B Page 5 of 12

Switching Characteristics Over the Operating Range [10, 11, 12, 13]

Parameter Description

45 ns

UnitMin. Max.

Read Cycle

tRC Read Cycle Time 45 ns

tAA Address to Data Valid 45 ns

tOHA Data Hold from Address Change 10 ns

tACE CE LOW to Data Valid 45 ns

tDOE OE LOW to Data Valid 22 ns

tLZOE OE LOW to LOW Z[11] 5ns

tHZOE OE HIGH to High Z[11, 12] 18 ns

tLZCE CE LOW to Low Z[11] 10 ns

tHZCE CE HIGH to High Z[11, 12] 18 ns

tPU CE LOW to Power-Up 0 ns

tPD CE HIGH to Power-Down 45 ns

tDBE BLE/BHE LOW to Data Valid 22 ns

tLZBE BLE/BHE LOW to Low Z[11] 5ns

tHZBE BLE/BHE HIGH to HIGH Z[11, 12] 18 ns

Write Cycle[13]

tWC Write Cycle Time 45 ns

tSCE CE LOW to Write End 35 ns

tAW Address Set-Up to Write End 35 ns

tHA Address Hold from Write End 0 ns

tSA Address Set-Up to Write Start 0 ns

tPWE WE Pulse Width 35 ns

tBW BLE/BHE LOW to Write End 35 ns

tSD Data Set-Up to Write End 25 ns

tHD Data Hold from Write End 0 ns

tHZWE WE LOW to High-Z[11, 12] 18 ns

tLZWE WE HIGH to Low-Z[11] 10 ns

Notes:

10.Test conditions for all parameters other than tri-state parameters assume signal transition time of3 ns (1V/ns) or less, timing reference levels of VCC(typ)/2, input

pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section.

11.At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any

given device.

12.tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedence state.

13.The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any

of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates

the write.

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MoBL®

Document #: 38-05569 Rev. *B Page 6 of 12

Switching Waveforms [14, 15]

Read Cycle 1 (Address Transition Controlled)[14, 15]

Read Cycle No. 2 (OE Controlled)[15, 16]

Notes:

14.The device is continuously selected. OE, CE= VIL, BHE and/or BLE = VIL.

15.WE is HIGH for read cycle.

16.Address valid prior to or coincident with CEand BHE, BLE transition LOW.

ADDRESS

DATA OUT PREVIOUS DATA VALID DATA VALID

tRC

tAA

tOHA

50%

DATA VALID

ACE

LZBE

LZCE

DATA OUT HIGH IMPEDANCE IMPEDANCE

HZOE

HZCE

HIGH

SUPPLY

CURRENT

HZBE

BHE/BLE t

LZOE

ADDRESS

DBE

DOE

[+] Feedback

CY62136EV30

MoBL®

Document #: 38-05569 Rev. *B Page 7 of 12

Write Cycle No. 1 (WE Controlled)[13, 17, 18]

Write Cycle No. 2 (CE Controlled)[13, 17, 18]

Notes:

17.Data I/O is high impedance if OE = VIH.

18.If CE goes HIGH simultaneously with WE = VIH, the output remains in a high-impedance state.

19.During this period, the I/Os are in output state and input signals should not be applied.

Switching Waveforms (continued)[14, 15]

tHD

tSD

tPWE

tSA

tHA

tAW

tWC

DATA I/O

ADDRESS

tHZOE

DATAIN

NOTE19

BHE/BLE tBW

tSCE

tHD

tSD

tPWE

tHA

tAW

tSCE

tWC

tHZOE

DATAIN

ADDRESS

DATA I/O

NOTE 19

BHE/BLE tBW

tSA

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CY62136EV30

MoBL®

Document #: 38-05569 Rev. *B Page 8 of 12

Write Cycle No. 3 (WE Controlled, OE LOW)[18]

Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[18]

Switching Waveforms (continued)[14, 15]

DATAIN

tHD

tSD

tLZWE

tPWE

tSA

tHA

tAW

tSCE

tWC

tHZWE

ADDRESS

DATAI/O NOTE 19

tBW

BHE/BLE

DATA I/O

ADDRESS

tWC

DATA

NOTE 19

BHE/BLE

tSCE

PWE

tHZWE tHD

tLZWE

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CY62136EV30

MoBL®

Document #: 38-05569 Rev. *B Page 9 of 12

Truth Table

CE WE OE BHE BLE Inputs/Outputs Mode Power

H X X X X High Z Deselect/Power-down Standby (ISB)

L X X H H High Z Output Disabled Active (ICC)

L H L L L Data Out (I/OO–I/O15) Read Active (ICC)

L H L H L Data Out (I/OO–I/O7);

I/O8–I/O15 in High Z Read Active (ICC)

L H L L H Data Out (I/O8–I/O15);

I/O0–I/O7 in High Z Read Active (ICC)

L H H L L High Z Output Disabled Active (ICC)

L H H H L High Z Output Disabled Active (ICC)

L H H L H High Z Output Disabled Active (ICC)

L L X L L Data In (I/OO–I/O15) Write Active (ICC)

L L X H L Data In (I/OO–I/O7);

I/O8–I/O15 in High Z Write Active (ICC)

L L X L H Data In (I/O8–I/O15);

I/O0–I/O7 in High Z Write Active (ICC)

Ordering Information

Speed

(ns) Ordering Code Package

Diagram Package Type Operating

Range

45 CY62136EV30LL-45BVXI 51-85150 48-ball Very Fine Pitch Ball Grid Array (Pb-free) Industrial

CY62136EV30LL-45ZSXI 51-85087 44-pin Thin Small Outline Package II (Pb-free)

Please contact your local Cypress sales representative for availability of other parts

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CY62136EV30

MoBL®

Document #: 38-05569 Rev. *B Page 10 of 12

Package Diagrams

A1 CORNER

0.75

Ø0.30±0.05(48X)

Ø0.25 M C A B

Ø0.05 M C

0.15(4X)

0.21±0.05

1.00 MAX

SEATING PLANE

0.55 MAX.

0.25 C

0.10 C

A1 CORNER

TOP VIEW BOTTOM VIEW

234

3.75

5.25

465231

6.00±0.10

8.00±0.10

6.00±0.10

1.875

2.625

0.26 MAX.

48-pin VFBGA (6 x 8 x 1 mm) (51-85150)

51-85150-*D

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