Cypress Semiconductor AutoStore STK14CA8 User manual

STK14CA8

128Kx8 AutoStore™nvSRAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose

CA 95134-1709 • 408-943-2600

Document Number: 001-51592 Rev. ** Revised March 04, 2009

Features

■

25, 35, 45 ns Read Access and Read/Write Cycle Time

■

Unlimited Read/Write Endurance

■

Automatic Nonvolatile STORE on Power Loss

■

Nonvolatile STORE Under Hardware or Software Control

■

Automatic RECALL to SRAM on Power Up

■

Unlimited RECALL Cycles

■

200K STORE Cycles

■

20-Year Nonvolatile Data Retention

■

Single 3.0V + 20%, -10% Operation

■

Commercial and Industrial Temperatures

■

Small Footprint SOIC and SSOP Packages (RoHS Compliant)

Description

The Cypress STK14CA8 is a 1 Mb fast static RAM with a nonvol-

atile QuantumTrap™ storage element included with each

memory cell. This SRAM provides fast access and cycle times,

ease of use, and unlimited read and write endurance of a normal

SRAM.

Data transfers automatically to the nonvolatile storage cells

when power loss is detected (the STORE operation). On power

up, data is automatically restored to the SRAM (the RECALL

operation). Both STORE and RECALL operations are also

available under software control.

The Cypress nvSRAM is the first monolithic nonvolatile memory

to offer unlimited writes and reads. It is the highest performing

and most reliable nonvolatile memory available.

ROW DECODERINPUT BUFFERS

COLUMN DEC

COLUMN I/O

POWER

CONTROL

HSB

STORE/

RECALL

CONTROL

SOFTWARE

DETECT A

– A

Quantum Trap

1024 X 1024

STATIC RAM

ARRAY

1024 X 1024

STORE

RECALL

CAP

Logic Block Diagram

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STK14CA8

Document Number: 001-51592 Rev. ** Page 2 of 16

Pinouts

Figure 1. 48-Pin SSOP Figure 2. 32-Pin SOIC

Figure 3. Relative PCB Area Usage

[1]

Pin Descriptions

VSS

A14

A12

DQ0

DQ1

VCC

DQ2

VCAP

A13

A11

A10

DQ7

DQ6

VSS

NC 23

VCC

HSB

DQ5

DQ3

DQ4

A16 A15

Note

1. See Package Diagrams on page 15 for detailed package size specifications.

CAP

HSB

Pin Name I/O Description

-A

Input Address: The 17 address inputs select one of 131,072 bytes in the nvSRAM array.

-DQ

I/O Data: Bi-directional 8-bit data bus for accessing the nvSRAM.

EInput Chip Enable: The active low E input selects the device.

WInput Write Enable: The active low W allows to write the data on the DQ pins to the address location

latched by the falling edge of E.

GInput Output Enable: The active low G input enables the data output buffers during read cycles.

De-asserting G high causes the DQ pins to tri-state.

Power Supply Power: 3.0V, +20%, -10%.

HSB I/O Hardware Store Busy: When low this output indicates a Store is in progress. When pulled low

external to the chip, it initiates a nonvolatile STORE operation. A weak pull up resistor keeps this

pin high if not connected. (Connection is optional).

CAP

Power Supply AutoStore™ Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to

nonvolatile storage elements.

Power Supply Ground.

NC No Connect Unlabeled pins have no internal connections.

[+] Feedback

STK14CA8

Document Number: 001-51592 Rev. ** Page 3 of 16

Absolute Maximum Ratings

Voltage on Input Relative to Ground.................–0.5V to 4.1V

Voltage on Input Relative to V

...........–0.5V to (V

+ 0.5V)

Voltage on DQ

0-7

or HSB......................–0.5V to (V

+ 0.5V)

Temperature under Bias............................... –55°C to 125°C

Junction Temperature................................... –55°C to 140°C

Storage Temperature.................................... –65°C to 150°C

Power Dissipation.............................................................1W

DC Output Current (1 output at a time, 1s duration)....15mA

NF (SOP-32) PACKAGE THERMAL CHARACTERISTICS

5.4 C/W; θ

44.3 [0fpm], 37.9 [200fpm], 35.1 C/W [500fpm].

RF (SSOP-48) PACKAGE THERMAL CHARACTERISTICS

6.2 C/W; θ

51.1 [0fpm], 44.7 [200fpm], 41.8 C/W [500fpm].

Note: Stresses greater than those listed under Absolute

Maximum Ratings may cause permanent damage to the device.

This is a stress rating only, and functional operation of the device

at conditions above those indicated in the operational sections

of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

reliability.

DC Characteristics

= 2.7V to 3.6V)

Note The HSB pin has I

OUT

=-10 uA for V

of 2.4 V, this parameter is characterized but not tested.

Symbol Parameter Commercial Industrial Units Notes

Min Max Min Max

CC1

Average V

Current 65

AVAV

= 25 ns

AVAV

= 35 ns

AVAV

= 45 ns

Dependent on output loading and cycle

rate. Values obtained without output loads.

CC2

Average V

Current during

STORE 3 3 mA All Inputs Don’t Care, V

= max

Average current for duration of STORE

cycle (t

STORE

)

CC3

Average V

Current at t

AVAV

200 ns

3V, 25°C, Typical

10 10 mA W

≥

– 0.2V)

All Other Inputs Cycling at CMOS Levels

Dependent on output loading and cycle

rate. Values obtained without output loads.

CC4

Average V

CAP

Current during

AutoStore Cycle 3 3 mA All Inputs Don’t Care

Average current for duration of STORE

cycle (t

STORE

)

Standby Current

(Standby, Stable CMOS Levels) 33mAE

≥ (

-0.2V)

All Others V

≤

0.2V or

≥

-0.2V)

Standby current level after nonvolatile

cycle complete

ILK

Input Leakage Current ±1±1μAV

= max

= V

to V

OLK

Off-State Output Leakage

Current ±1±1μAV

= max

= V

to V

, E or G

≥

Input Logic “1” Voltage 2.0 V

+0.3 2.0 V

+0.3 V All Inputs

Input Logic “0” Voltage V

–0.5 0.8 V

–0.5 0.8 V All Inputs

Output Logic “1” Voltage 2.4 2.4 V I

OUT

=–2 mA

Output Logic “0” Voltage 0.4 0.4 V I

OUT

= 4 mA

Operating Temperature 0 70 –40 85

Operating Voltage 2.7 3.6 2.7 3.6 V 3.3V + 0.3V

CAP

Storage Capacitance 17 120 17 120 μFBetweenV

CAP

pin and V

, 5V rated.

Nonvolatile STORE operations 200 200 K

DATA

Data Retention 20 20 Years At 55

[+] Feedback

STK14CA8

Document Number: 001-51592 Rev. ** Page 4 of 16

AC Test Conditions

Input Pulse Levels....................................................0V to 3V

Input Rise and Fall Times ................................................. ≤ 5 ns

Input and Output Timing Reference Levels....................1.5V

Output Load..................................See Figure 4 and Figure 5

Capacitance

= 25°C, f = 1.0 MHz)

Figure 4. AC Output Loading

Figure 5. AC Output Loading for Tristate Specifications

, t

WLQZ

, t

WHQZ

, t

GLQX

, t

GHQZ

)

Symbol Parameter

[2]

Max Units Conditions

Input Capacitance 7 pF

V = 0 to 3V

OUT

Output Capacitance 7 pF

V = 0 to 3V

577 Ohms

30 pF

789 Ohms

3.0V

INCLUDING

SCOPE AND

OUTPUT

FIXTURE

577 Ohms

5 pF

789 Ohms

3.0V

INCLUDING

SCOPE AND

OUTPUT

FIXTURE

Note

2. These parameters are guaranteed but not tested.

[+] Feedback

STK14CA8

Document Number: 001-51592 Rev. ** Page 5 of 16

SRAM READ Cycles #1 and #2

Figure 6. SRAM READ Cycle #1: Address Controlled

[3, 4, 6]

Figure 7. SRAM READ Cycle #2: E and G Controlled

[3, 6]

NO. Symbols Parameter STK14CA8-25 STK14CA8-35 STK14CA8-45 Units

#1 #2 Alt. Min Max Min Max Min Max

ELQV

ACS

Chip Enable Access Time 25 35 45 ns

AVAV[3]

ELEH[3]

Read Cycle Time 25 35 45 ns

AVQV[4]

Address Access Time 25 35 45 ns

GLQV

Output Enable to Data Valid 12 15 20 ns

AXQX[4]

Output Hold after Address Change 3 3 3 ns

ELQX

Address Change or Chip Enable to

Output Active 333ns

EHQZ[5]

Address Change or Chip Disable to

Output Inactive 10 13 15 ns

GLQX

OLZ

Output Enable to Output Active 0 0 0 ns

GHQZ[5]

OHZ

Output Disable to Output Inactive 10 13 15 ns

ELICCH[2]

Chip Enable to Power Active 0 0 0 ns

EHICCL[2]

Chip Disable to Power Standby 25 35 45 ns

DATA VALID

AXQX

AVQV

DQ (DATA OUT)

ADDRESS

AVAV

Notes

3. W must be high during SRAM READ cycles.

4. Device is continuously selected with E and G both low

5. Measured ±200mV from steady state output voltage.

6. HSB must remain high during READ and WRITE cycles

229

[+] Feedback

STK14CA8

Document Number: 001-51592 Rev. ** Page 6 of 16

SRAM WRITE Cycles #1 and #2

Figure 8. SRAM WRITE Cycle #1: W Controlled

[7,8]

Figure 9. SRAM WRITE Cycle #2: E Controlled

[7,8]

NO. Symbols Parameter STK14CA8-25 STK14CA8-35 STK14CA8-45 Units

#1 #2 Alt. Min Max Min Max Min Max

AVAV

Write Cycle Time 25 35 45 ns

WLWH

WLEH

Write Pulse Width 20 25 30 ns

ELWH

ELEH

Chip Enable to End of Write 20 25 30 ns

DVWH

DVEH

Data Setup to End of Write 10 12 15 ns

WHDX

EHDX

Data Hold after End of Write 0 0 0 ns

AVWH

AVEH

Address Setup to End of Write 20 25 30 ns

AVWL

AVEL

Address Setup to Start of Write 0 0 0 ns

WHAX

EHAX

Address Hold after End of Write 0 0 0 ns

WLQZ[5,7]

Write Enable to Output Disable 10 13 15 ns

WHQX

Output Active after End of Write 3 3 3 ns

Notes

7. If W is low when E goes low, the outputs remain in the high impedance state.

Eor W must be ≥V

during address transitions.

PREVIOUS DATA

DATA OUT

ADDRESS

AVAV

WHDX

DATA IN

WHAX

WLWH

AVWL

AVWH

DATA VALID

WLQZ

DVWH

HIGH IMPEDANCE

WHQX

ELWH

DATA IN

AVAV

EHDX

WLEH

EHAX

AVEL

AVEH

DATA VALID

DVEH

HIGH IMPEDANCE

ELEH

DATA OUT

ADDRESS

DATA IN

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STK14CA8

Document Number: 001-51592 Rev. ** Page 7 of 16

AutoStore/POWER UP RECALL

Figure 10. AutoStore/POWER UP RECALL

Note Read and Write cycles are ignored during STORE, RECALL, and while V

is below V

SWITCH.

NO. Symbols Parameter STK14CA8 Units Notes

Standard Alternate Min Max

HRECALL

Power up RECALL Duration 20 ms 9

STORE

HLHZ

STORE Cycle Duration 12.5 ms 10, 11

SWITCH

Low Voltage Trigger Level 2.65 V

CCRISE

Rise Time 150 μs

Notes

9. t

HRECALL

starts from the time V

rises above V

SWITCH

10.If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE takes place

11. Industrial Grade devices require maximum 15 ms.

23 23

22 22

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STK14CA8

Document Number: 001-51592 Rev. ** Page 8 of 16

Software Controlled STORE/RECALL Cycle

Figure 11. Software STORE/RECALL CYCLE: E Controlled

[13]

Figure 12. Software STORE/RECALL CYCLE: G Controlled

[13]

NO. Symbols Parameter

[12,13]

STK14CA8-35 STK14CA8-35 STK14CA8-45 Units Notes

ECont GCont Alt Min Max Min Max Min Max

AVAV

STORE/RECALL Initiation Cycle

Time 25 35 45 ns 13

AVEL

AVGL

Address Setup Time 0 0 0 ns

ELEH

GLGH

Clock Pulse Width 20 25 30 ns

EHAX

GHAX

Address Hold Time 1 1 1 ns

RECALL

RECALL Duration 50 50 50 μs

26 26

27 28

23 30

26 26

27 28

29 23 30

Notes

12.The software sequence is clocked on the falling edge of E controlled READs or G controlled READs

13.Thesixconsecutiveaddressesmustbereadin theorderlistedintheSoftwareSTORE/RECALL ModeSelectionTable.Wmustbehigh during allsixconsecutive cycles.

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STK14CA8

Document Number: 001-51592 Rev. ** Page 9 of 16

Hardware STORE Cycle

Figure 13. Hardware STORE Cycle

Soft Sequence Commands

Figure 14. Software Sequence Commands

NO. Symbols Parameter STK14CA8 Units Notes

Standard Alternate Min Max

DELAY

HLQZ

Hardware STORE to SRAM Disabled 1 70 μs 14

HLHX

Hardware STORE Pulse Width 15 ns

NO. Symbols Parameter STK14CA8 Units Notes

Standard Min Max

Soft Sequence Processing Time 70 μs15,16

33 33

Notes

14.On a hardware STORE initiation, SRAM operation continues to be enabled for time t

DELAY

to allow read/write cycles to complete.

15.This is the amount of time that it takes to take action on a soft sequence command. Vcc power must remain high to effectively register command.

16.Commands such as Store and Recall lock out I/O until operation is complete which further increases this time. See specific command.

[+] Feedback

STK14CA8

Document Number: 001-51592 Rev. ** Page 10 of 16

Mode Selection

E W G A

-A

Mode I/O Power Notes

H X X X Not Selected Output High Z Standby

L H L X Read SRAM Output Data Active

L L X X Write SRAM Input Data Active

L H L 0x04E38

0x0B1C7

0x083E0

0x07C1F

0x0703F

0x08B45

Read SRAM

AutoStore Disable

Output Data

Active

17, 18, 19

L H L 0x04E38

0x0B1C7

0x083E0

0x07C1F

0x0703F

0x04B46

Read SRAM

AutoStore Enable

Output Data

Active

17, 18, 19

L H L 0x04E38

0x0B1C7

0x083E0

0x07C1F

0x0703F

Read SRAM

Output Data

Active 17, 18, 19

0x08FC0 Nonvolatile Store Output High Z I

CC2

L H L 0x04E38

0x0B1C7

0x083E0

0x07C1F

0x0703F

0x04C63

Read SRAM

Nonvolatile Recall

Output Data

Output High Z

Active

17, 18, 19

Notes

17.The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.

18.While there are 17 addresses on the STK14CA8, only the lower 16 are used to control software modes

19.I/O state depends on the state of G. The I/O table shown assumes G low

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