Texas Instruments TPS65910A Series User manual

TPS65910Ax User's Guide For AM335x

Processors

Version C

User's Guide

Literature Number: SWCU093C

August 2011–Revised May 2013

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And may require export or re-export license for shipping it in compliance

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Contents

1 Introduction ........................................................................................................................ 5

2 Connection Diagram and TPS65910Ax EEPROM Definition ...................................................... 5

3 First Initialization ............................................................................................................... 10

3.1 I/O Polarity/Muxing Configuration .................................................................................... 10

3.2 Define Wake-Up/Interrupt Event (SLEEP or OFF) ................................................................ 10

3.3 Backup Battery Configuration ........................................................................................ 10

3.4 DCDC and Voltage Scaling Resource Configuration ............................................................. 10

3.5 Sleep Platform Configuration ......................................................................................... 10

4 Event Management Through Interrupts ................................................................................ 11

4.1 INT_STS_REG.VMBHI_IT ............................................................................................ 11

4.2 INT_STS_REG.PWRON_IT .......................................................................................... 11

4.3 INT_STS_REG.PWRON_LP_IT ..................................................................................... 11

4.4 INT_STS_REG.HOTDIE_IT .......................................................................................... 11

4.5 INT_STS_REG.VMBDCH_IT ......................................................................................... 11

4.6 INT_STS2_REG.GPIO_R/F_IT ...................................................................................... 11

4.7 INT_STS_REG. RTC_ALARM_IT ................................................................................... 11

5 Revision History ................................................................................................................ 12

SWCU093C–August 2011–Revised May 2013 Table of Contents

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List of Figures

1 AM335x Power Supply Connections with TPS65910A and TPS65910A3 .......................................... 6

2 AM335x Power Supply Connections with TPS65910A31 ............................................................. 7

3 Power-Up and Power-Down Timing Diagram........................................................................... 9

List of Tables

1 TPS65910Ax comparison.................................................................................................. 5

2 EEPROM Configuration for TPS65910Ax ............................................................................... 8

3 Revision History ........................................................................................................... 12

4List of Figures SWCU093C–August 2011–Revised May 2013

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User's Guide

SWCU093C–August 2011–Revised May 2013

TPS65910Ax User's Guide For AM335x Processors

This user's guide can be used as a reference for connectivity between the TPS65910Ax power-

management integrated circuit (PMIC) and the AM335x processor.

1 Introduction

This user's guide can be used as a reference for connectivity between the TPS65910Ax PMIC and the

AM335x processor. The TPS65910AA1 device is to support the AM335x processor with DDR2.

TPS65910A3A1 and TPS65910A31A1 devices are to support the AM335x processor with DDR3. This

user's guide does not provide details about the power resources or the functionality of the device. For

such information, refer to the full specification document, TPS65910 Data Manual.

Table 1 compares TPS65910Ax devices

Table 1. TPS65910Ax comparison

TPS65910A TPS65910A3 TPS65910A31

DDR2 DDR3 DDR3

Memory (VIO=1.8V) (VIO=1.5V) (VIO=1.5V)

Low power mode Low power mode

VRTC power mode Full power mode

(VRTC_REG.VRTC_OFFMASK (VRTC_REG.VRTC_OFFMA

in OFF state (VRTC_REG.VRTC_OFFMASK=1)

=0) SK=0)

2 Connection Diagram and TPS65910Ax EEPROM Definition

Figure 1 shows the connection diagram between the processor and the TPS65910A or TPS65910A3.

Figure 2 shows the connection diagram between the processor and TPS65910A31.

Notes for connection diagram:

• To support the processor power-up sequence, connect BOOT0 to ground and BOOT 1 to VRTC to

select EEPROM boot mode.

• The TPS65910Ax digital control signal level is defined by the VDDIO connection.

• VAUX2 can support up to 300 mA for the specific case of a 3.3-V output level.

• The VDD1 and VDD2 connections shown in Figure 1 and Figure 2 is valid for processor version ZCZ

(15 x 15). In ZCE (13 x 13), VDD_MPU and VDD_CORE are shorted internally. For ZCE, connect

VDD1 to VDD_MPU; VDD2 is free for system use.

SWCU093C–August 2011–Revised May 2013 TPS65910Ax User's Guide For AM335x Processors

VFB2

SW2

VFBIO

2.2 PH

SWIO

2.2 PF

VDIG2

VCC1

VBAT

10 PFVFB1

2.2 PH

SW1

VCC2

VCCIO

VDIG1

VDDIO

VAUX2

VAUX1

VMMC

VAUX33

VPLL

VDAC

VRTC

20 mA

VCC6

4.7 PF

VCC4

VCC3

VCC5

VCC7

VBACKUP

5 to 2000 mF

VREF

REFGND

100 nF

GND2

GND1

GNDIO

INT1

PWRON

SLEEP

NRESPWRON

GPIO_CKSYNC

(available)

TESTV

(not connected)

SW3

VFB3

VDD3

100 mA

10 K

VDD3 is a boost supplying 5 V. 4.7 PHVBAT

10 PF

4.7 PF

10 PF

2.2 PH

10 PF

2.2 PF

VBAT

TPS65910A

TPS65910A3

VDDS_DDR

VDDSHVx

VDDS_PLL_xx

VDDS_OSC,

VDDS_SRAM_CORE_BG,

VDDS_SRAM_MPU_BB

1.8/3.3V based on system I/O level

VDD3

100 mA

VDD1

1500 mA

VPLL

50 mA

VDAC

150 mA

VRTC

20 mA

PowerPadTM

VDD2

1500 mA

VIO

1000 mA

VDIG1

300 mA

VDIG2

300 mA

VAUX1

150 mA

VAUX2

150 mA

VAUX33

150 mA

VMMC

300 mA

VDD3 is a boost supplying 5 V.

5 V

VDDS_CORE

VDD_MPU

VDDSHVx

VDDS

VDDSHV

VDDA3P3V_USB0/1

VDDA1P8V_USB00/1

VDDA_ADC

VDDS_RTC

1K 2

VDDIO

1K 2

SCL_SCK

SDA_SDI

SDASR_EN2

SCLSR_EN1

CLK32KOUT

BOOT0

BOOT1

VRTC

OSC32KIN

OSC32KOUT

GPIO1_9

I2C0_SDA

I2C0_SCL

PORZ

PMIC_PWR_EN

SPIO_D1

SPIO_CS0

GPIO1_8

PWRHOLD

Processor

0.6 to 1.5 V, DVS

12.5-mV steps

Default ON 1.1 V

0.6 to 1.5 V, DVS

12.5-mV steps

Default ON 1.1 V

1.5/1.8/2.5/3.3 V

1.2/1.5/1.8/2.7 V

Default ON 1.8 V

1.0/1.1/1.2/1.8 V

Default ON 1.8 V

1.8/2.5/2.8/2.85 V

Default ON 1.8 V

1.8/2.8/2.9/3.3 V

Default ON 3.3 V

1.8/2.0/2.8/3.3 V

Default ON 3.3 V

1.8/2.8/3.0/3.3 V

Default ON 3.3 V

1.8/2.6/2.8/2.85 V

Default ON 1.8 V

1.0/1.1/1.8/2.5 V

Default ON 1.8 V

SWCU093_Block_Diagram

External Buck

Connection Diagram and TPS65910Ax EEPROM Definition

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Figure 1. AM335x Power Supply Connections with TPS65910A and TPS65910A3

6TPS65910Ax User's Guide For AM335x Processors SWCU093C–August 2011–Revised May 2013

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VFB2

SW2

VFBIO

2.2 PH

SWIO

2.2 PF

VDIG2

VCC1

VBAT

10 PFVFB1

2.2 PH

SW1

VCC2

VCCIO

VDIG1

VDDIO

VAUX2

VAUX1

VMMC

VAUX33

VPLL

VDAC

VRTC

20 mA

VCC6

4.7 PF

VCC4

VCC3

VCC5

VCC7

VBACKUP

5 to 2000 mF

VREF

REFGND

100 nF

GND2

GND1

GNDIO

INT1

PWRON

SLEEP

NRESPWRON

GPIO_CKSYNC

(available)

TESTV

(not connected)

SW3

VFB3

VDD3

100 mA

10 K

VDD3 is a boost supplying 5 V. 4.7 PHVBAT

10 PF

4.7 PF

10 PF

2.2 PH

10 PF

2.2 PF

VBAT

VDD3

100 mA

VDD1

1500 mA

VPLL

50 mA

VDAC

150 mA

VRTC

20 mA

PowerPadTM

VDD2

1500 mA

VIO

1000 mA

VDIG1

300 mA

VDIG2

300 mA

VAUX1

150 mA

VAUX2

150 mA

VAUX33

150 mA

VMMC

300 mA

SDASR_EN2

SCLSR_EN1

OSC32KIN

OSC32KOUT

BOOT0

BOOT1

VRTC

PWRHOLD

PMIC_PWR_EN

SWCU093_Block_Diagram

CLK32KOUT

GPIO1_9

I2C0_SDA

I2C0_SCL

PORZ

SPIO_D1

SPIO_CS0

GPIO1_8

1K 2

VDDIO

1K 2

SCL_SCK

SDA_SDI

VDDS_RTC

VDDS_DDR

VDDSHVx

VDDS_PLL_xx

VDDS_OSC,

VDDS_SRAM_CORE_BG,

VDDS_SRAM_MPU_BB

VDDSHVx

VDDS

VDDSHV

VDDA3P3V_USB0/1

VDDA1P8V_USB00/1

VDDA_ADC

1.8/3.3V based on system I/O level

1.2/1.5/1.8/2.7 V

Default ON 1.8 V

1.0/1.1/1.2/1.8 V

Default ON 1.8 V

1.8/2.5/2.8/2.85 V

Default ON 1.8 V

1.8/2.8/2.9/3.3 V

Default ON 3.3 V

1.8/2.0/2.8/3.3 V

Default ON 3.3 V

1.8/2.8/3.0/3.3 V

Default ON 3.3 V

1.8/2.6/2.8/2.85 V

Default ON 1.8 V

1.0/1.1/1.8/2.5 V

Default ON 1.8 V

VDDS_CORE

VDD_MPU

Processor

0.6 to 1.5 V, DVS

12.5-mV steps

Default ON 1.1 V

0.6 to 1.5 V, DVS

12.5-mV steps

Default ON 1.1 V

1.5/1.8/2.5/3.3 V

VDD3 is a boost supplying 5 V.

5 V

TPS65910A31A1

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Connection Diagram and TPS65910Ax EEPROM Definition

Figure 2. AM335x Power Supply Connections with TPS65910A31

SWCU093C–August 2011–Revised May 2013 TPS65910Ax User's Guide For AM335x Processors

Connection Diagram and TPS65910Ax EEPROM Definition

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Table 2 lists the EEPROM definition of the TPS65910Ax and Figure 3 shows the corresponding power-up

sequence.

Table 2. EEPROM Configuration for TPS65910Ax

VDD1_OP_REG SEL VDD1 voltage level selection for boot 1.1

VDD1_REG VGAIN_SEL VDD1 gain selection, x1 or x2 x1

EEPROM VDD1 time slot selection 6

DCDCCTRL_REG VDD1_PSKIP VDD1 pulse skip mode enable Skip enabled

VDD2_OP_REG / SEL VDD2 voltage level selection for boot 1.1

VDD2_SR_REG

VDD2_REG VGAIN_SEL VDD2 gain selection, x1 or x3 x1

EEPROM VDD2 time slot selection 7

DCDCCTRL_REG VDD2_PSKIP VDD2 pulse skip mode enable Skip enabled

TPS65910AA1 1.8V

(DDR2)

TPS65910A3A1 1.5V

VIO_REG SEL VIO voltage selection (DDR3)

TPS65910A31A1 1.5V

(DDR3)

EEPROM VIO time slot selection 4

DCDCCTRL_REG VIO_PSKIP VIO pulse skip mode enable Skip enabled

EEPROM VDD3 time slot OFF

VDIG1_REG SEL LDO voltage selection 1.8

EEPROM LDO time slot 2

VDIG2_REG SEL LDO voltage selection 1.8

EEPROM LDO time slot 2

VDAC_REG SEL LDO voltage selection 1.8

EEPROM LDO time slot 1

VPLL_REG SEL LDO voltage selection 1.8

EEPROM LDO time slot 3

VAUX1_REG SEL LDO voltage selection 1.8

EEPROM LDO time slot 3

VMMC_REG SEL LDO voltage selection 3.3

EEPROM LDO time slot 5

VAUX33_REG SEL LDO voltage selection 3.3

EEPROM LDO time slot 5

VAUX2_REG SEL LDO voltage selection 3.3

EEPROM LDO time slot 5

CLK32KOUT pin CLK32KOUT time slot 7

NRESPWRON pin NRESPWRON time slot 7 + 1

TPS65910AA1 Low-

0 = VRTC LDO will be in low-power mode during power mode

OFF state. TPS65910A3A1 Low-

VRTC_REG VRTC_OFFMASK 1 = VRC LDO will be in full-power mode during power mode

OFF state. TPS65910A31A1 High-

power mode

0 = RTC in normal-power mode

DEVCTRL_REG RTC_PWDN 1 = Clock gating of RTC register and logic, low- 1

power mode

0 = Clock source is crystal/external clock.

DEVCTRL_REG CK32K_CTRL RC

1 = Clock source is internal RC oscillator.

Boot sequence time slot duration:

DEVCTRL2_REG TSLOT_LENGTH 0 = 0.5 ms 2 ms

1 = 2 ms

8TPS65910Ax User's Guide For AM335x Processors SWCU093C–August 2011–Revised May 2013

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VDDA3P3V_USB0/1, USB_VUSB0/1

Processor/System signal

TPS65910

signal

Vbat/5 V supply VCC7

VRTC

PMIC start-up r ason PWRHOLD

VDDS VDAC 1.8 V

VDDS_PLL_xx, VDDS_OSC,

VDDS__SRAM_CORE/MPU_BG VDIG2 1.8 V

VDDSHVx VDIG1 1.8 V

VDDA1P8V_USB0/1 VAUX1 1.8 V

VDDA_ADC VPLL 1.8 V

VDDS_DDR VIO 1.8V (DDR2)

1.5V (DDR3)

VDDSHVx VAUX2 3.3 V

VDDSHVx VMMC 3.3 V

VAUX33 3.3 V

VDD_MPU VDD1 1.1 V

VDD_CORE VDD2 1.1 V

CLK32KOUT

PORZ NRESPWRON

Switch-on s qu nc Switch-off s qu nc

Slot number: 0 1 2 3 4 5 6 7

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Connection Diagram and TPS65910Ax EEPROM Definition

Table 2. EEPROM Configuration for TPS65910Ax (continued)

0 = INT1 signal will be active low.

DEVCTRL2_REG IT_POL Active high

1 = INT1 signal will be active high.

0 = Device automatically switches on at NO

INT_MSK_REG VMBHI_IT_MSK SUPPLY-to-OFF or BACKUP-to-OFF transition. 1

1 = Start-up reason is required before switch-on.

Select threshold for main battery comparator

VMBCH_REG VMBCH_SEL[1:0] 3 V

threshold VMBCH.

Figure 3. Power-Up and Power-Down Timing Diagram

SWCU093C–August 2011–Revised May 2013 TPS65910Ax User's Guide For AM335x Processors

First Initialization

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3 First Initialization

3.1 I/O Polarity/Muxing Configuration

Program DEVCTRL2_REG.SLEEPSIG_POL according to the GPIO level setting on the processor. This

can be set to active low or active high for SLEEP transitions. Software configuration allows specific power

resources to enter a low consumption state.

Set DEVCTRL_REG.DEV_SLP = 1 to allow SLEEP transitions when requested.

Update the GPIO0 configuration (GPIO0_REG) based on your needs.

3.2 Define Wake-Up/Interrupt Event (SLEEP or OFF)

Select the appropriate bits in the INT_MSK_REG and INT_MSK2_REG registers to activate an interrupt to

the processor on the INT1 line.

3.3 Backup Battery Configuration

If a backup battery is used, enable backup battery charging by setting the BBCH_REG.BBCHEN bit to 1.

The maximum charge voltage can be set based on the backup battery specifications by using the BBSEL

bits.

3.4 DCDC and Voltage Scaling Resource Configuration

If the SmarReflex interface is not used for viltage scaling (power saving), these pins can be used to

control the power resources.

Configure two operating voltages for DCDC1 and DCDC2

• VDDx_OP_REG.SEL= Roof voltage (ENx ball high)

• VDDx_SR_REG.SEL = Floor voltage (ENx ball low)

Assign control for DCDC1 to SCLSR_EN1 and DCDC2 to SCLSR_EN2:

• Set EN1_SMPS_ASS_REG.VDD1_EN1 = 1

• Set EN2_SMPS_ASS_REG.VDD2_EN1 = 2

• Set SLEEP_KEEP_RES_ON_REG.VDD1_KEEPON = 1 (allow low-power mode)

• Set SLEEP_KEEP_RES_ON_REG.VDD2_KEEPON = 1 (allow low-power mode)

3.5 Sleep Platform Configuration

Configure the state of the LDOs when the SLEEP signal is used (by default all resources go into SLEEP

state; in SLEEP state the LDO voltage is maintained but transient and load capability are reduced).

Resources that must provide full load capability must be set in the SLEEP_KEEP_LDO_ON_REG register.

Resources that can be set off in SLEEP state to optimize power consumption must be set in the

SLEEP_SET_LDO_OFF_REG register.

10 TPS65910Ax User's Guide For AM335x Processors SWCU093C–August 2011–Revised May 2013

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