Texas Instruments TMS320C6000 DSP User manual
TMS320C6000 DSP
Designing for JTAG Emulation
Reference Guide
Literature Number: SPRU641
July 2003
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27
Designing for JTAG EmulationSPRU641
Preface
Read This First
About This Manual
This document assists you in meeting the design requirements of the
XDS510emulator with respect to JTAG designs and discusses the XDS510
cable (manufacturing part number 2617698-0001). This cable is identified by
a label on the cable pod marked JTAG 3/5 V and supports both standard 3-volt
and 5-volt target system power inputs.
The term JTAG as used in this document refers to Texas Instruments scan-
based emulation, which is based on the IEEE 1149.1 standard.
Notational Conventions
This document uses the following conventions.
-Hexadecimal numbers are shown with the suffix h. For example, the
following number is 40 hexadecimal (decimal 64): 40h.
Related Documentation From Texas Instruments
The following documents describe the C6000devices and related support
tools. Copies of these documents are available on the Internet at www.ti.com.
Tip: Enter the literature number in the search box provided at www.ti.com.
TMS320C6000 CPU and Instruction Set Reference Guide (literature
number SPRU189) describes the TMS320C6000CPU architecture,
instruction set, pipeline, and interrupts for these digital signal processors.
TMS320C6000 Peripherals Reference Guide (literature number SPRU190)
describes the peripherals available on the TMS320C6000DSPs.
TMS320C6000 Technical Brief (literature number SPRU197) gives an
introduction to the TMS320C62xand TMS320C67xDSPs, develop-
ment tools, and third-party support.
TMS320C64x Technical Overview (SPRU395) gives an introduction to the
TMS320C64xDSP and discusses the application areas that are
enhanced by the TMS320C64x VelociTI.
Trademarks
28 Designing for JTAG Emulation SPRU641
TMS320C6000 Programmer’s Guide (literature number SPRU198)
describes ways to optimize C and assembly code for the
TMS320C6000DSPs and includes application program examples.
TMS320C6000 Code Composer Studio Tutorial (literature number
SPRU301) introduces the Code Composer Studiointegrated develop-
ment environment and software tools.
Code Composer Studio Application Programming Interface Reference
Guide (literature number SPRU321) describes the Code Composer
Studioapplication programming interface (API), which allows you to
program custom plug-ins for Code Composer.
TMS320C6x Peripheral Support Library Programmer’s Reference
(literature number SPRU273) describes the contents of the
TMS320C6000peripheral support library of functions and macros. It
lists functions and macros both by header file and alphabetically,
provides a complete description of each, and gives code examples to
show how they are used.
TMS320C6000 Chip Support Library API Reference Guide (literature
number SPRU401) describes a set of application programming interfaces
(APIs) used to configure and control the on-chip peripherals.
Trademarks
Code Composer Studio, C6000, C62x, C64x, C67x, TMS320C6000,
TMS320C62x, TMS320C64x, TMS320C67x, VelociTI, and XDS510 are
trademarks of Texas Instruments.
PALis a registered trademark of Advanced Micro Devices, Inc.
Related Documentation From Texas Instruments / Trademarks
Contents
29
Designing for JTAG EmulationSPRU641
Contents
1 Designing Your Target System’s Emulator Connector (14-Pin Header) 7. . . . . . . . . . . . . . . . .
2 Bus Protocol 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 IEEE 1149.1 Standard 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 JTAG Emulator Cable Pod Logic 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 JTAG Emulator Cable Pod Signal Timing 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 Emulation Timing Calculations 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 Connections Between the Emulator and the Target System 14. . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 Buffering Signals 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2 Using a Target-System Clock 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3 Configuring Multiple Processors 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8 Mechanical Dimensions for the 14-Pin Emulator Connector 18. . . . . . . . . . . . . . . . . . . . . . . . .
9 Emulation Design Considerations 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.1 Using Scan Path Linkers 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2 Emulation Timing Calculations for SPL 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.3 Using Emulation Pins 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4 Performing Diagnostic Applications 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures
30 Designing for JTAG Emulation SPRU641
Figures
1 14-Pin Header Signals and Header Dimensions 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 JTAG Emulator Cable Pod Interface 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 JTAG Emulator Cable Pod Timing Diagram 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Target-System-Generated Test Clock 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Multiprocessor Connections 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 Pod/Connector Dimensions 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 14-Pin Connector Dimensions 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8 Connecting a Secondary JTAG Scan Path to an SPL 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9 EMU0/1 Configuration 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10 EMU0/1 Configuration With Additional AND Gate to Meet Timing Requirements 27. . . . . . . .
11 Suggested Timings for the EMU0 and EMU1 Signals 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12 EMU0/1 Configuration Without Global Stop 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13 TBC Emulation Connections for n JTAG Scan Paths 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tables
1 14-Pin Header Signal Descriptions 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Emulator Cable Pod Timing Parameters 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
Designing for JTAG EmulationSPRU641
Designing for JTAG Emulation
This document assists you in meeting the design requirements of the
XDS510emulator with respect to JTAG designs and discusses the XDS510
cable (manufacturing part number 2617698-0001). This cable is identified by
a label on the cable pod marked JTAG 3/5 V and supports both standard 3-volt
and 5-volt target system power inputs.
The term JTAG as used in this document refers to Texas Instruments scan-
based emulation, which is based on the IEEE 1149.1 standard.
1 Designing Your Target System’s Emulator Connector (14-Pin Header)
JTAG target devices support emulation through a dedicated emulation port.
This port is a superset of the IEEE 1149.1 standard and is accessed by the
emulator. To communicate with the emulator, your target system must have
a 14-pin header (two rows of seven pins) with the connections that are shown
in Figure 1. Table 1 describes the emulation signals.
Figure 1. 14-Pin Header Signals and Header Dimensions
TDO 7 8 GND
TMS 1 2 TRST
TDI 3 4 GND
TCK_RET 9 10 GND
TCK 11 12 GND
Header Dimensions:
Pin-to-pin spacing, 0.100 in. (X,Y
)
Pin width, 0.025-in. square post
Pin length, 0.235-in. nominal
PD (VCC)5 6no pin (key)†
EMU0 13 14 EMU1
†While the corresponding female position on the cable connector is plugged to prevent improper connection, the cable lead for
pin 6 is present in the cable and is grounded, as shown in the schematics and wiring diagrams in this document.
Designing Your Target System’s Emulator Connector (14-Pin Header)
Designing for JTAG Emulation
4SPRU641
Table 1. 14-Pin Header Signal Descriptions
Signal Description Emulator†
State Target†
State
TMS Test mode select O I
TDI Test data input O I
TDO Test data output I O
TCK Test clock. TCK is a 10.368-MHz clock source from the emulation cable
pod. This signal can be used to drive the system test clock OI
TRST‡Test reset O I
EMU0 Emulation pin 0 I I/O
EMU1 Emulation pin 1 I I/O
PD(VCC) Presence detect. Indicates that the emulation cable is connected and
that the target is powered up. PD should be tied to VCC in the target sys-
tem.
IO
TCK_RET Test clock return. Test clock input to the emulator. May be a buffered or
unbuffered version of TCK. IO
GND Ground
†I = input; O = output
‡Do not use pullup resistors on TRST: it has an internal pulldown device. In a low-noise environment, TRST can be left floating.
In a high-noise environment, an additional pulldown resistor may be needed. (The size of this resistor should be based on
electrical current considerations.)
Although you can use other headers, recommended parts include:
straight header, unshrouded DuPont Connector Systems
part numbers: 65610−114
65611−114
67996−114
67997−114
Designing Your Target System’s Emulator Connector (14-Pin Header)
5
Designing for JTAG EmulationSPRU641
2 Bus Protocol
The IEEE 1149.1 specification covers the requirements for the test access port
(TAP) bus slave devices and provides certain rules, summarized as follows:
-The TMS/TDI inputs are sampled on the rising edge of the TCK signal of
the device.
-The TDO output is clocked from the falling edge of the TCK signal of the
device.
When these devices are daisy-chained together, the TDO of one device has
approximately a half TCK cycle setup to the next device’s TDI signal. This type
of timing scheme minimizes race conditions that would occur if both TDO and
TDI were timed from the same TCK edge. The penalty for this timing scheme
is a reduced TCK frequency.
The IEEE 1149.1 specification does not provide rules for bus master (emula-
tor) devices. Instead, it states that it expects a bus master to provide bus slave
compatible timings. The XDS510 provides timings that meet the bus slave
rules.
3 IEEE 1149.1 Standard
For more information concerning the IEEE 1149.1 standard, contact IEEE
Customer Service:
Address:
IEEE Customer Service
445 Hoes Lane, PO Box 1331
Piscataway, NJ 08855-1331
Phone:
in the US and Canada: (800) 678−IEEE
outside the US and Canada: (908) 981−1393
FAX: (908) 981−9667
Telex: 833233
Bus Protocol / IEEE 1149.1 Standard
JTAG Emulator Cable Pod Logic
Designing for JTAG Emulation
6SPRU641
4 JTAG Emulator Cable Pod Logic
Figure 2 shows a portion of the emulator cable pod. These are the functional
features of the pod:
-Signals TDO and TCK_RET can be parallel-terminated inside the pod if
required by the application. By default, these signals are not terminated.
-Signal TCK is driven with a 74LVT240 device. Because of the high-current
drive (32 mA IOL/IOH), this signal can be parallel-terminated. If TCK is tied
to TCK_RET, then you can use the parallel terminator in the pod.
-Signals TMS and TDI can be generated from the falling edge of TCK_RET,
according to the IEEE 1149.1 bus slave device timing rules.
-Signals TMS and TDI are series-terminated to reduce signal reflections.
-A 10.368-MHz test clock source is provided. You may also provide your
own test clock for greater flexibility.
Figure 2. JTAG Emulator Cable Pod Interface
100 Ω
TL7705A
RESIN
270 Ω
JP2
180 Ω
TCK_RET (Pin 9){
EMU1 (Pin 14)
EMU0 (Pin 13) 74AS1034
GND (Pins 4,6,8,10,12)
TRST (Pin 2)
TCK (Pin 11){
10.368 MHz
33 Ω
33 Ω
TDI (Pin 3)
TMS (Pin 1)
TDO (Pin 7)
74LVT240
180 Ω
JP1
270 Ω74F175
Q
Q
D
PD(VCC) (Pin 5)
+5 V
+5 V
74AS1004
Y
Y
Y
Y
A
†The emulator pod uses TCK_RET as its clock source for internal synchronization. TCK is provided as an optional target system
test clock source.
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