Texas Instruments TMS320 DSP User manual

TMS320 DSP Algorithm Standard

Rules and Guidelines

User's Guide

Literature Number: SPRU352GJune 2005 – Revised February 2007

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Contents

Preface ............................................................................................................................... 7

1 Overview ................................................................................................................... 91.1 Scope of the Standard ............................................................................................ 101.1.1 Rules and Guidelines .................................................................................... 111.2 Requirements of the Standard .................................................................................. 111.3 Goals of the Standard ............................................................................................ 121.4 Intentional Omissions ............................................................................................ 121.5 System Architecture ............................................................................................... 131.5.1 Frameworks ............................................................................................... 131.5.2 Algorithms ................................................................................................. 141.5.3 Core Run-Time Support ................................................................................. 14

2 General Programming Guidelines ............................................................................... 152.1 Use of C Language ............................................................................................... 162.2 Threads and Reentrancy ......................................................................................... 162.2.1 Threads .................................................................................................... 162.2.2 Preemptive vs. Non-Preemptive Multitasking......................................................... 172.2.3 Reentrancy ................................................................................................ 172.2.4 Example ................................................................................................... 182.3 Data Memory....................................................................................................... 192.3.1 Memory Spaces .......................................................................................... 202.3.2 Scratch versus Persistent ............................................................................... 202.3.3 Algorithm versus Application ............................................................................ 222.4 Program Memory ................................................................................................. 232.5 ROM-ability ........................................................................................................ 232.6 Use of Peripherals ................................................................................................ 24

3 Algorithm Component Model ..................................................................................... 253.1 Interfaces and Modules ........................................................................................... 263.1.1 External Identifiers ....................................................................................... 273.1.2 Naming Conventions ..................................................................................... 283.1.3 Module Initialization and Finalization .................................................................. 283.1.4 Module Instance Objects ................................................................................ 283.1.5 Design-Time Object Creation ........................................................................... 293.1.6 Run-Time Object Creation and Deletion .............................................................. 293.1.7 Module Configuration .................................................................................... 303.1.8 Example Module .......................................................................................... 303.1.9 Multiple Interface Support ............................................................................... 313.1.10 Interface Inheritance .................................................................................... 323.1.11 Summary ................................................................................................. 323.2 Algorithms .......................................................................................................... 333.3 Packaging .......................................................................................................... 343.3.1 Object Code ............................................................................................... 343.3.2 Header Files .............................................................................................. 353.3.3 Debug Verses Release .................................................................................. 35

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4 Algorithm Performance Characterization ..................................................................... 374.1 Data Memory....................................................................................................... 384.1.1 Heap Memory ............................................................................................. 384.1.2 Stack Memory ............................................................................................ 394.1.3 Static Local and Global Data Memory ................................................................. 394.2 Program Memory .................................................................................................. 404.3 Interrupt Latency .................................................................................................. 414.4 Execution Time .................................................................................................... 414.4.1 MIPS Is Not Enough ..................................................................................... 414.4.2 Execution Time Model ................................................................................... 42

5 DSP-Specific Guidelines ............................................................................................ 455.1 CPU Register Types .............................................................................................. 465.2 Use of Floating Point .............................................................................................. 475.3 TMS320C6xxx Rules and Guidelines........................................................................... 475.3.1 Endian Byte Ordering .................................................................................... 475.3.2 Data Models ............................................................................................... 475.3.3 Program Model ........................................................................................... 475.3.4 Register Conventions .................................................................................... 485.3.5 Status Register ........................................................................................... 485.3.6 Interrupt Latency ......................................................................................... 495.4 TMS320C54xx Rules and Guidelines .......................................................................... 495.4.1 Data Models ............................................................................................... 495.4.2 Program Models .......................................................................................... 495.4.3 Register Conventions .................................................................................... 515.4.4 Status Registers .......................................................................................... 515.4.5 Interrupt Latency ......................................................................................... 525.5 TMS320C55x Rules and Guidelines ............................................................................ 525.5.1 Stack Architecture ........................................................................................ 525.5.2 Data Models ............................................................................................... 525.5.3 Program Models .......................................................................................... 535.5.4 Relocatability .............................................................................................. 535.5.5 Register Conventions .................................................................................... 545.5.6 Status Bits ................................................................................................. 555.6 TMS320C24xx Guidelines ....................................................................................... 575.6.1 General .................................................................................................... 575.6.2 Data Models ............................................................................................... 575.6.3 Program Models .......................................................................................... 575.6.4 Register Conventions .................................................................................... 575.6.5 Status Registers .......................................................................................... 585.6.6 Interrupt Latency ......................................................................................... 585.7 TMS320C28x Rules and Guidelines ............................................................................ 585.7.1 Data Models ............................................................................................... 585.7.2 Program Models .......................................................................................... 595.7.3 Register Conventions .................................................................................... 595.7.4 Status Registers .......................................................................................... 595.7.5 Interrupt Latency ......................................................................................... 60

6 Use of the DMA Resource .......................................................................................... 616.1 Overview ............................................................................................................ 62

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6.2 Algorithm and Framework ........................................................................................ 626.3 Requirements for the Use of the DMA Resource ............................................................. 636.4 Logical Channel ................................................................................................... 636.5 Data Transfer Properties ......................................................................................... 646.6 Data Transfer Synchronization .................................................................................. 646.7 Abstract Interface .................................................................................................. 656.8 Resource Characterization ....................................................................................... 666.9 Runtime APIs ...................................................................................................... 676.10 Strong Ordering of DMA Transfer Requests ................................................................... 676.11 Submitting DMA Transfer Requests ............................................................................ 686.12 Device Independent DMA Optimization Guideline ............................................................ 686.13 C6xxx Specific DMA Rules and Guidelines .................................................................... 696.13.1 Cache Coherency Issues for Algorithm Producers ................................................. 696.14 C55x Specific DMA Rules and Guidelines ..................................................................... 706.14.1 Supporting Packed/Burst Mode DMA Transfers .................................................... 706.14.2 Minimizing Logical Channel Reconfiguration Overhead ........................................... 716.14.3 Addressing Automatic Endianism Conversion Issues ............................................. 716.15 Inter-Algorithm Synchronization ................................................................................. 716.15.1 Non-Preemptive System ............................................................................... 716.15.3 Preemptive System ..................................................................................... 72

A Rules and Guidelines ................................................................................................ 75A.1 General Rules ..................................................................................................... 76A.2 Performance Characterization Rules ........................................................................... 77A.3 DMA Rules ......................................................................................................... 77A.4 General Guidelines ................................................................................................ 78A.5 DMA Guidelines ................................................................................................... 79

B Core Run-Time APIs ................................................................................................. 81B.1 TI C-Language Run-Time Support Library ..................................................................... 82B.2 DSP/BIOS Run-time Support Library ........................................................................... 82

C Bibliography ............................................................................................................ 83C.1 Books ............................................................................................................... 83C.2 URLS ................................................................................................................ 83

D Glossary .................................................................................................................. 85D.1 Glossary of Terms ................................................................................................. 85

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List of Figures

1-1 TMS320 DSP Algorithm Standard Elements ........................................................................... 101-2 DSP Software Architecture ................................................................................................ 132-1 Scratch vs Persistent Memory Allocation ............................................................................... 212-2 Data Memory Types ....................................................................................................... 223-1 Module Interface and Implementation ................................................................................... 263-2 Module Object Creation ................................................................................................... 293-3 Example Module Object ................................................................................................... 293-4 Example Implementation of IALG Interface ............................................................................. 334-1 Execution Timeline for Two Periodic Tasks ............................................................................ 425-1 Register Types .............................................................................................................. 466-1 Transfer Properties for a 1-D Frame ..................................................................................... 646-2 Frame Index and 2-D Transfer of N-1 Frames ......................................................................... 64

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PrefaceSPRU352G – June 2005 – Revised February 2007

Read This First

This document defines a set of requirements for DSP algorithms that, if followed, allowsystem integrators to quickly assemble production-quality systems from one or moresuch algorithms. Thus, this standard is intended to enable a rich commercialoff-the-shelf (COTS) marketplace for DSP algorithm technology and to significantlyreduce the time-to-market for new DSP-based products.

The TMS320 DSP Algorithm Standard is part of TI's eXpressDSP technology initiative.Algorithms that comply with the standard are tested and awarded an"eXpressDSP-compliant" mark upon successful completion of the test.

In describing these requirements and their purpose, it is often necessary to describehow applications might be structured to take advantage of eXpressDSP-compliantalgorithms. It is important to keep in mind, however, that the TMS320 DSP AlgorithmStandards make no substantive demands on the clients of these algorithms.

Intended Audience

This document assumes that the reader is fluent in the C programming language, has a good workingknowledge of digital signal processing (DSP) and the requirements of DSP applications, and has someexposure to the principles and practices of object-oriented programming.

This document describes the rules that must be followed by all eXpressDSP-compliant algorithm softwareand interfaces between algorithms and applications that use these algorithms. There are two audiencesfor this document:

•Algorithm writers learn how to ensure that an algorithm can coexist with other algorithms in a singlesystem and how to package an algorithm for deployment into a wide variety of systems.•System integrators learn how to incorporate multiple algorithms from separate sources into a completesystem.

Document Overview

Throughout this document, the rules and guidelines of the TMS320 DSP Algorithm Standard (referred toas XDAIS) are highlighted. Rules must be followed to be compliant with the TMS320 DSP AlgorithmStandard Guidelines. Guidelines should be obeyed but may be violated by eXpressDSP-compliantsoftware. A complete list of all rules and guidelines is provided in Appendix A. Electronic versions of thisdocument contain hyperlinks from each rule and guideline in Appendix A to the main body of thedocument.

This document contains the following chapters:•Chapter 1 - Overview, provides the motivation for the standard and describes how algorithms (asdefined by the TMS320 DSP Algorithm Standard) are used in DSP systems.•Chapter 2 - General Programming Guidelines, describes a general programming model for DSPsoftware and contains rules and guidelines that apply to all eXpressDSP-compliant software.•Chapter 3 - Algorithm Component Model, describes rules and guidelines that enableeXpressDSP-compliant algorithms from multiple sources to operate harmoniously in a single system.•Chapter 4 - Algorithm Performance Characterization, describes how an eXpressDSP-compliantalgorithm's performance must be characterized.•Chapter 5 - DSP-Specific Guidelines, defines a model for describing the DSP's on-chip registers andcontains rules and guidelines for each specific DSP architecture covered by this specification.

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Related Documentation

The TMS320 DSP Algorithm Standard is documented in the following manuals:•TMS320 DSP Algorithm Standard Rules and Guidelines (this document). Describes all the rulesand guidelines that make up the TMS320 DSP Algorithm Standard (may be referred to as XDAISthroughout this document).•TMS320 DSP Algorithm Standard API Reference (SPRU360). Contains APIs that are required bythe TMS320 DSP Algorithm Standard and full source examples of eXpressDSP-compliant algorithmcomponents.

•TMS320 DSP Algorithm Standard Developer's Guide (SPRU424). Contains examples that assist thedeveloper in implementing the XDAIS interface and to create a test application.•Using DMA with Framework Components for C64x+ Application Report (SPRAAG1). Describesthe standard DMA software abstractions and interfaces for TMS320 DSP Algorithm Standard (XDAIS)compliant algorithms designed for the C64x+ EDMA3 controller using DMA Framework Componentsutilities.

Although these documents are largely self-contained, there are times when it is best not to duplicatedocumentation that exists in other documents. The following documents contain supplementaryinformation necessary to adhere to the TMS320 DSP Algorithm Standards.•DSP/BIOS User's Guide•TMS320 C54x/C6x/C2x Optimizing C Compiler User's Guide

Text Conventions

The following typographical conventions are used in this specification:•Text inside back-quotes (") represents pseudo-code•Program source code, function and macro names, parameters, and command line commands areshown in a mono-spaced font.

Rule n

Text is shown like this to indicate a requirement of the TMS320 DSP Algorithm Standard.

Guideline n

Text is shown like this to indicate a recommendation of the TMS320 DSP Algorithm Standard.

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Chapter 1SPRU352G – June 2005 – Revised February 2007

Overview

This chapter provides an overview of the TMS320 DSP Algorithm Standard.

Topic .................................................................................................. Page

1.1 Scope of the Standard ............................................................... 101.2 Requirements of the Standard ................................................... 111.3 Goals of the Standard ................................................................ 121.4 Intentional Omissions ............................................................... 121.5 System Architecture .................................................................. 13

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1.1 Scope of the Standard

Rules for TMS320C2x

Level 1

Level 2

Level 3

Level 4 Telecom

Rules for TMS320C5x Rules for TMS320C6x

Imaging Audio Automotive Other

Algorithm Component Model

General Programming Guidelines

SC callable

SNo hard coded addresses

SReentrant

Setc.

SModules

SGeneric interfaces

SPackaging

Setc.

SInterrupt usage

SMemory usage

SRegister usage

Setc.

SInterrupt usage

SMemory usage

SRegister usage

Setc.

SInterrupt usage

SMemory usage

SRegister usage

Setc.

Svocoders

Secho cancel

Setc.

SJPEG

Setc.

Scoders

Setc.

Scope of the Standard

Digital Signal Processors (DSPs) are often programmed like "traditional" embedded microprocessors. Thatis, they are programmed in a mix of C and assembly language, they directly access hardware peripherals,and, for performance reasons, almost always have little or no standard operating system support. Thus,like traditional microprocessors, there is very little use of commercial off-the-shelf (COTS) softwarecomponents for DSPs.

However, unlike general-purpose embedded microprocessors, DSPs are designed to run sophisticatedsignal processing algorithms and heuristics. For example, they may be used to detect DTMF digits in thepresence of noise, to compress toll quality speech by a factor of 20, or for speech recognition in a noisyautomobile traveling at 65 miles per hour.

Such algorithms are often the result of many years of doctoral research. However, because of the lack ofconsistent standards, it is not possible to use an algorithm in more than one system without significantreengineering. Since few companies can afford a team of DSP PhDs, and the reuse of DSP algorithms isso labor intensive, the time-to-market for a new DSP-based product is measured in years rather than inmonths.

This document defines a set of requirements for DSP algorithms that, if followed, allow system integratorsto quickly assemble production-quality systems from one or more such algorithms. Thus, this standard isintended to enable a rich COTS marketplace for DSP algorithm technology and to significantly reduce thetime-to-market for new DSP-based products.

The TMS320 DSP Algorithm Standard defines three levels of guidelines.

Figure 1-1. TMS320 DSP Algorithm Standard Elements

Level 1 contains programming guidelines that apply to all algorithms on all DSP architectures regardlessof application area. Almost all recently developed software modules follow these common senseguidelines already, so this level just formalizes them.

Level 2 contains rules and guidelines that enable all algorithms to operate harmoniously within a singlesystem. Conventions are established for the algorithm's use of data memory and names for externalidentifiers, for example. In addition, simple rules for how algorithms are packaged are also specified.

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